| Vinod Polimera | 0af24f7 | 2022-05-31 06:49:15 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/mmio.h> |
| 4 | #include <soc/display/mdssreg.h> |
| 5 | |
| 6 | void mdss_intf_tg_setup(struct edid *edid) |
| 7 | { |
| 8 | uint32_t hsync_period, vsync_period, hsync_start_x, hsync_end_x; |
| 9 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
| Vinod Polimera | 0af24f7 | 2022-05-31 06:49:15 +0530 | [diff] [blame] | 10 | |
| Vinod Polimera | 0af24f7 | 2022-05-31 06:49:15 +0530 | [diff] [blame] | 11 | hsync_period = edid->mode.ha + edid->mode.hbl; |
| 12 | vsync_period = edid->mode.va + edid->mode.vbl; |
| 13 | hsync_start_x = edid->mode.hbl - edid->mode.hso; |
| 14 | hsync_end_x = hsync_period - edid->mode.hso - 1; |
| 15 | display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period; |
| 16 | display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1; |
| 17 | hsync_ctl = (hsync_period << 16) | edid->mode.hspw; |
| 18 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 19 | |
| 20 | write32(&mdp_intf->intf_hsync_ctl, hsync_ctl); |
| 21 | write32(&mdp_intf->intf_vysnc_period_f0, vsync_period * hsync_period); |
| 22 | write32(&mdp_intf->intf_vysnc_pulse_width_f0, edid->mode.vspw * hsync_period); |
| 23 | write32(&mdp_intf->intf_disp_hctl, display_hctl); |
| 24 | write32(&mdp_intf->intf_disp_v_start_f0, display_vstart); |
| 25 | write32(&mdp_intf->intf_disp_v_end_f0, display_vend); |
| 26 | write32(&mdp_intf->intf_underflow_color, 0x00); |
| 27 | write32(&mdp_intf->intf_panel_format, 0x2100); |
| 28 | } |
| 29 | |
| 30 | void mdss_ctrl_config(void) |
| 31 | { |
| 32 | /* Select Video Mode Interface */ |
| 33 | write32(&mdp_ctl->ctl_top, 0x0); |
| 34 | |
| 35 | /* PPB0 to INTF1 */ |
| 36 | write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_1); |
| 37 | } |