| Felix Held | ea32c52 | 2021-02-13 01:42:44 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/data_fabric.h> |
| 4 | #include <console/console.h> |
| 5 | #include <cpu/x86/lapic_def.h> |
| 6 | #include <soc/data_fabric.h> |
| 7 | #include <soc/iomap.h> |
| 8 | #include <types.h> |
| 9 | |
| 10 | void data_fabric_set_mmio_np(void) |
| 11 | { |
| 12 | /* |
| 13 | * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. |
| 14 | * |
| 15 | * AGESA has already programmed the NB MMIO routing, however nothing |
| 16 | * is yet marked as non-posted. |
| 17 | * |
| 18 | * If there exists an overlapping routing base/limit pair, trim its |
| 19 | * base or limit to avoid the new NP region. If any pair exists |
| 20 | * completely within HPET-LAPIC range, remove it. If any pair surrounds |
| 21 | * HPET-LAPIC, it must be split into two regions. |
| 22 | * |
| 23 | * TODO(b/156296146): Remove the settings from AGESA and allow coreboot |
| 24 | * to own everything. If not practical, consider erasing all settings |
| 25 | * and have coreboot reprogram them. At that time, make the source |
| 26 | * below more flexible. |
| 27 | * * Note that the code relies on the granularity of the HPET and |
| 28 | * LAPIC addresses being sufficiently large that the shifted limits |
| 29 | * +/-1 are always equivalent to the non-shifted values +/-1. |
| 30 | */ |
| 31 | |
| 32 | unsigned int i; |
| 33 | int reg; |
| 34 | uint32_t base, limit, ctrl; |
| 35 | const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; |
| 36 | const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; |
| 37 | |
| 38 | data_fabric_print_mmio_conf(); |
| 39 | |
| 40 | for (i = 0; i < NUM_NB_MMIO_REGS; i++) { |
| 41 | /* Adjust all registers that overlap */ |
| 42 | ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); |
| 43 | if (!(ctrl & (MMIO_WE | MMIO_RE))) |
| 44 | continue; /* not enabled */ |
| 45 | |
| 46 | base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); |
| 47 | limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); |
| 48 | |
| 49 | if (base > np_top || limit < np_bot) |
| 50 | continue; /* no overlap at all */ |
| 51 | |
| 52 | if (base >= np_bot && limit <= np_top) { |
| 53 | data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ |
| 54 | continue; |
| 55 | } |
| 56 | |
| 57 | if (base < np_bot && limit > np_top) { |
| 58 | /* Split the configured region */ |
| 59 | data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); |
| 60 | reg = data_fabric_find_unused_mmio_reg(); |
| 61 | if (reg < 0) { |
| 62 | /* Although a pair could be freed later, this condition is |
| 63 | * very unusual and deserves analysis. Flag an error and |
| 64 | * leave the topmost part unconfigured. */ |
| 65 | printk(BIOS_ERR, |
| 66 | "Error: Not enough NB MMIO routing registers\n"); |
| 67 | continue; |
| 68 | } |
| 69 | data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); |
| 70 | data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); |
| 71 | data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); |
| 72 | continue; |
| 73 | } |
| 74 | |
| 75 | /* If still here, adjust only the base or limit */ |
| 76 | if (base <= np_bot) |
| 77 | data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); |
| 78 | else |
| 79 | data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); |
| 80 | } |
| 81 | |
| 82 | reg = data_fabric_find_unused_mmio_reg(); |
| 83 | if (reg < 0) { |
| 84 | printk(BIOS_ERR, "Error: cannot configure region as NP\n"); |
| 85 | return; |
| 86 | } |
| 87 | |
| 88 | data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); |
| 89 | data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); |
| 90 | data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), |
| 91 | (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE |
| 92 | | MMIO_RE); |
| 93 | |
| 94 | data_fabric_print_mmio_conf(); |
| 95 | } |