Rex-BC Chen | 9c098e2 | 2021-06-29 09:44:31 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3 | #include "dramc_common.h" |
| 4 | #include "dramc_dv_init.h" |
| 5 | #include "dramc_int_global.h" |
| 6 | #include "x_hal_io.h" |
| 7 | #include "sv_c_data_traffic.h" |
| 8 | #include "dramc_pi_api.h" |
| 9 | #if (FOR_DV_SIMULATION_USED == 0) |
| 10 | #include "dramc_top.h" |
| 11 | #endif |
| 12 | #include <emi.h> |
| 13 | |
| 14 | DRAMC_CTX_T dram_ctx_chb; |
| 15 | |
| 16 | #if (FOR_DV_SIMULATION_USED == 1) |
| 17 | U8 gu1BroadcastIsLP4 = TRUE; |
| 18 | #endif |
| 19 | |
| 20 | bool gAndroid_DVFS_en = TRUE; |
| 21 | bool gUpdateHighestFreq = FALSE; |
| 22 | |
| 23 | #define DV_SIMULATION_BYTEMODE 0 |
| 24 | #define DV_SIMULATION_LP5_TRAINING_MODE1 1 |
| 25 | #define DV_SIMULATION_LP5_CBT_PHASH_R 1 |
| 26 | |
| 27 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 28 | SAVE_TIME_FOR_CALIBRATION_T SavetimeData; |
| 29 | #endif |
| 30 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 31 | U8 gHQA_Test_Freq_Vcore_Level = 0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 32 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 33 | u8 ett_fix_freq = 0xff; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 34 | |
| 35 | DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 36 | {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, |
| 37 | {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 38 | #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION |
| 39 | {LP4_DDR400 /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF, OPEN_LOOP_MODE}, |
| 40 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 41 | {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, |
| 42 | {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, |
| 43 | {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, |
| 44 | {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, |
| 45 | {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | DRAMC_CTX_T DramCtx_LPDDR4 = |
| 49 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 50 | CHANNEL_SINGLE, |
| 51 | CHANNEL_A, |
| 52 | RANK_DUAL, |
| 53 | RANK_0, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 54 | |
| 55 | #ifdef MTK_FIXDDR1600_SUPPORT |
| 56 | LP4_DDR1600, |
| 57 | #else |
| 58 | #if __FLASH_TOOL_DA__ |
| 59 | LP4_DDR1600, |
| 60 | #else |
| 61 | #if (DV_SIMULATION_LP4 == 1) |
| 62 | LP4_DDR1600, |
| 63 | #else |
| 64 | LP5_DDR3200, |
| 65 | #endif |
| 66 | #endif |
| 67 | #endif |
| 68 | #if DV_SIMULATION_LP4 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 69 | TYPE_LPDDR4X, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 70 | #else |
| 71 | TYPE_LPDDR5, |
| 72 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 73 | FSP_0 , |
| 74 | FSP_0 , |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 75 | ODT_OFF, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 76 | {CBT_NORMAL_MODE, CBT_NORMAL_MODE}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 77 | #if ENABLE_READ_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 78 | {DBI_OFF,DBI_ON}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 79 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 80 | {DBI_OFF,DBI_OFF}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 81 | #endif |
| 82 | #if ENABLE_WRITE_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 83 | {DBI_OFF,DBI_ON}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 84 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 85 | {DBI_OFF,DBI_OFF}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 86 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 87 | DATA_WIDTH_16BIT, |
| 88 | DEFAULT_TEST2_1_CAL, |
| 89 | DEFAULT_TEST2_2_CAL, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 90 | #if ENABLE_K_WITH_WORST_SI_UI_SHIFT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 91 | TEST_WORST_SI_PATTERN, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 92 | #else |
| 93 | TEST_XTALK_PATTERN, |
| 94 | #endif |
| 95 | #if (DV_SIMULATION_LP4 == 1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 96 | 800, |
| 97 | 800, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 98 | #else |
| 99 | 1600, |
| 100 | 1600, |
| 101 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 102 | 0x88, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 103 | REVISION_ID_MAGIC, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 104 | 0xff, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 105 | {0,0}, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 106 | 270, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 107 | |
| 108 | #if PRINT_CALIBRATION_SUMMARY |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 109 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 110 | {{0,0,}}, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 111 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 112 | {{0,0,}}, |
| 113 | 1, |
| 114 | 0, |
| 115 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 116 | {0}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 117 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 118 | FALSE, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 119 | 0, |
| 120 | 0, |
| 121 | 0, |
| 122 | &SavetimeData, |
| 123 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 124 | &gFreqTbl[DRAM_DFS_SRAM_MAX-1], |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 125 | DRAM_DFS_REG_SHU0, |
| 126 | TRAINING_MODE2, |
| 127 | CBT_PHASE_RISING, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 128 | 0, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 129 | PHYPLL_MODE, |
| 130 | DBI_OFF, |
| 131 | FSP_MAX, |
| 132 | PINMUX_EMCP, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 133 | {DISABLE,DISABLE}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 134 | 0, |
| 135 | }; |
| 136 | |
| 137 | |
| 138 | |
| 139 | #if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION) |
| 140 | DRAMC_CTX_T gTimeProfilingDramCtx; |
| 141 | U8 gtime_profiling_flag = 0; |
| 142 | #endif |
| 143 | |
| 144 | void vSetVcoreByFreq(DRAMC_CTX_T *p) |
| 145 | { |
| 146 | #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) |
| 147 | #if __FLASH_TOOL_DA__ |
| 148 | dramc_set_vcore_voltage(750000); |
| 149 | #else |
| 150 | unsigned int vio18, vcore, vdram, vddq, vmddr; |
| 151 | //int ret; |
| 152 | |
| 153 | vio18 = vcore = vdram = vddq = vmddr = 0; |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame^] | 154 | (void)vio18; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 155 | |
| 156 | #if __ETT__ |
| 157 | hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr); |
| 158 | #elif defined(VCORE_BIN) |
| 159 | switch (vGet_Current_SRAMIdx(p)) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 160 | case SRAM_SHU0: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 161 | #ifdef VOLTAGE_SEL |
| 162 | vcore = vcore_voltage_select(KSHU0); |
| 163 | if (!vcore) |
| 164 | #endif |
| 165 | vcore = get_vcore_uv_table(0); |
| 166 | break; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 167 | case SRAM_SHU1: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 168 | #ifdef VOLTAGE_SEL |
| 169 | vcore = vcore_voltage_select(KSHU1); |
| 170 | if (!vcore) |
| 171 | #endif |
| 172 | vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(1)) >> 1; |
| 173 | break; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 174 | case SRAM_SHU2: |
| 175 | case SRAM_SHU3: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 176 | #ifdef VOLTAGE_SEL |
| 177 | vcore = vcore_voltage_select(KSHU2); |
| 178 | if (!vcore) |
| 179 | #endif |
| 180 | vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(2)) >> 1; |
| 181 | break; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 182 | case SRAM_SHU4: |
| 183 | case SRAM_SHU5: |
| 184 | case SRAM_SHU6: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 185 | #ifdef VOLTAGE_SEL |
| 186 | vcore = vcore_voltage_select(KSHU4); |
| 187 | if (!vcore) |
| 188 | #endif |
| 189 | vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(3)) >> 1; |
| 190 | break; |
| 191 | } |
| 192 | #else |
| 193 | switch (vGet_Current_SRAMIdx(p)) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 194 | case SRAM_SHU0: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 195 | #ifdef VOLTAGE_SEL |
| 196 | vcore = vcore_voltage_select(KSHU0); |
| 197 | #else |
| 198 | vcore = SEL_PREFIX_VCORE(LP4, KSHU0); |
| 199 | #endif |
| 200 | break; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 201 | case SRAM_SHU1: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 202 | #ifdef VOLTAGE_SEL |
| 203 | vcore = vcore_voltage_select(KSHU1); |
| 204 | #else |
| 205 | vcore = SEL_PREFIX_VCORE(LP4, KSHU1); |
| 206 | #endif |
| 207 | break; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 208 | case SRAM_SHU2: |
| 209 | case SRAM_SHU3: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 210 | #ifdef VOLTAGE_SEL |
| 211 | vcore = vcore_voltage_select(KSHU2); |
| 212 | #else |
| 213 | vcore = SEL_PREFIX_VCORE(LP4, KSHU2); |
| 214 | #endif |
| 215 | break; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 216 | case SRAM_SHU4: |
| 217 | case SRAM_SHU5: |
| 218 | case SRAM_SHU6: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 219 | #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 220 | case SRAM_SHU7: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 221 | #endif |
| 222 | #ifdef VOLTAGE_SEL |
| 223 | vcore = vcore_voltage_select(KSHU4); |
| 224 | #else |
| 225 | vcore = SEL_PREFIX_VCORE(LP4, KSHU4); |
| 226 | #endif |
| 227 | break; |
| 228 | default: |
| 229 | return; |
| 230 | } |
| 231 | #endif |
| 232 | |
Ryan Chuang | 4572727 | 2021-08-10 10:08:49 +0800 | [diff] [blame] | 233 | if (CONFIG(MEDIATEK_DRAM_DVFS)) |
| 234 | if (vcore) |
| 235 | dramc_set_vcore_voltage(vcore); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 236 | |
| 237 | #if defined(DRAM_HQA) |
| 238 | if (vio18) |
| 239 | dramc_set_vio18_voltage(vio18); |
| 240 | |
| 241 | if (vdram) |
| 242 | dramc_set_vmdd_voltage(p->dram_type, vdram); |
| 243 | |
| 244 | if (vddq) |
| 245 | dramc_set_vmddq_voltage(p->dram_type, vddq); |
| 246 | |
| 247 | if (vmddr) |
| 248 | dramc_set_vmddr_voltage(vmddr); |
| 249 | #endif |
| 250 | |
| 251 | #ifdef FOR_HQA_REPORT_USED |
| 252 | switch (vGet_Current_SRAMIdx(p)) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 253 | case SRAM_SHU0: |
| 254 | case SRAM_SHU1: |
| 255 | case SRAM_SHU2: |
| 256 | case SRAM_SHU3: |
| 257 | case SRAM_SHU4: |
| 258 | case SRAM_SHU5: |
| 259 | case SRAM_SHU6: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 260 | #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 261 | case SRAM_SHU7: |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 262 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 263 | gHQA_Test_Freq_Vcore_Level = 0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 264 | break; |
| 265 | default: |
| 266 | print("[HQA] undefined shuffle level for Vcore (SHU%d)\r\n", vGet_Current_SRAMIdx(p)); |
| 267 | #if __ETT__ |
| 268 | while(1); |
| 269 | #endif |
| 270 | break; |
| 271 | } |
| 272 | #endif |
| 273 | |
| 274 | |
| 275 | #ifndef DDR_INIT_TIME_PROFILING |
| 276 | print("Read voltage for %d, %d\n", p->frequency, vGet_Current_SRAMIdx(p)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 277 | print("Vcore = %d\n", dramc_get_vcore_voltage()); |
Ryan Chuang | 43a3aa0 | 2021-08-06 11:04:23 +0800 | [diff] [blame] | 278 | #ifdef FOR_HQA_REPORT_USED |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 279 | print("Vdram = %d\n", dramc_get_vmdd_voltage(p->dram_type)); |
| 280 | print("Vddq = %d\n", dramc_get_vmddq_voltage(p->dram_type)); |
| 281 | print("Vmddr = %d\n", dramc_get_vmddr_voltage()); |
| 282 | #endif |
Ryan Chuang | 43a3aa0 | 2021-08-06 11:04:23 +0800 | [diff] [blame] | 283 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 284 | |
| 285 | #endif |
| 286 | #endif |
| 287 | } |
| 288 | |
| 289 | U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type) |
| 290 | { |
| 291 | #if (defined(DRAM_HQA) || defined(__ETT__)) && (FOR_DV_SIMULATION_USED == 0) |
| 292 | if (get_voltage_type==0) |
| 293 | return dramc_get_vcore_voltage(); |
| 294 | |
| 295 | if (get_voltage_type==1) |
| 296 | return dramc_get_vmdd_voltage(p->dram_type); |
| 297 | |
| 298 | if (get_voltage_type==2) |
| 299 | return dramc_get_vmddq_voltage(p->dram_type); |
| 300 | |
| 301 | if (get_voltage_type==3) |
| 302 | return dramc_get_vio18_voltage(); |
| 303 | if (get_voltage_type==4) |
| 304 | return dramc_get_vmddr_voltage(); |
| 305 | |
| 306 | #endif |
| 307 | |
| 308 | return 0; |
| 309 | } |
| 310 | |
| 311 | |
| 312 | #if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 313 | #define RUNTIME_SHMOO_ON_GOING 0x00 |
| 314 | #define RUNTIME_SHMOO_END 0xff |
| 315 | void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) |
| 316 | { |
| 317 | U8 backup_channel, backup_rank; |
| 318 | U16 tx_pi_delay, tx_dqm_pi_delay; |
| 319 | S16 rx_first_delay=0x1fff, rx_first_delay_bit=0xff, rx_last_delay=-0x1fff, rx_last_delay_bit=0xff; |
| 320 | U8 u1BitIdx; |
| 321 | U32 u4value; |
| 322 | PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH]; |
| 323 | U8 ui_large_value, ui_small_value, pi_value; |
| 324 | U8 ui_dqm_large_value, ui_dqm_small_value, pi_dqm_value; |
| 325 | #if 0 |
| 326 | U8 ui_oen_large_value, ui_oen_small_value, pi_oen_value; |
| 327 | U8 ui_dqm_oen_large_value, ui_dqm_oen_small_value, pi_dqm_oen_value; |
| 328 | #endif |
| 329 | U8 scan_invert_flag=0; |
| 330 | |
| 331 | backup_channel = p->channel; |
| 332 | backup_rank = p->rank; |
| 333 | |
| 334 | p->channel = RUNTIME_SHMOO_TEST_CHANNEL; |
| 335 | p->rank = RUNTIME_SHMOO_TEST_RANK; |
| 336 | |
| 337 | #if RUNTIME_SHMOO_TX |
| 338 | if (RUNTIME_SHMOO_TEST_BYTE == 0) |
| 339 | { |
| 340 | tx_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ0) * 256 + |
| 341 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ0) * 32 + |
| 342 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQ_B0); |
| 343 | |
| 344 | tx_dqm_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM0) * 256 + |
| 345 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM0) * 32 + |
| 346 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQM_B0); |
| 347 | } |
| 348 | else |
| 349 | { |
| 350 | tx_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ1) * 256 + |
| 351 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ1) * 32 + |
| 352 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQ_B1); |
| 353 | |
| 354 | tx_dqm_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM1) * 256 + |
| 355 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM1) * 32 + |
| 356 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQM_B1); |
| 357 | } |
| 358 | #endif |
| 359 | |
| 360 | #if RUNTIME_SHMOO_RX |
| 361 | // vAutoRefreshSwitch(p, ENABLE); |
| 362 | |
| 363 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 364 | { |
| 365 | FinalWinPerBit[u1BitIdx].first_pass=p->pSavetimeData->u1RxWinPerbitDQ_firsbypass_Save[p->channel][p->rank][u1BitIdx+RUNTIME_SHMOO_TEST_BYTE*8]; |
| 366 | FinalWinPerBit[u1BitIdx].last_pass=p->pSavetimeData->u1RxWinPerbitDQ_lastbypass_Save[p->channel][p->rank][u1BitIdx+RUNTIME_SHMOO_TEST_BYTE*8]; |
| 367 | } |
| 368 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 369 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 370 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 371 | { |
| 372 | if (FinalWinPerBit[u1BitIdx].first_pass < rx_first_delay) |
| 373 | { |
| 374 | rx_first_delay = FinalWinPerBit[u1BitIdx].first_pass; |
| 375 | rx_first_delay_bit = u1BitIdx; |
| 376 | } |
| 377 | if (FinalWinPerBit[u1BitIdx].last_pass > rx_last_delay) |
| 378 | { |
| 379 | rx_last_delay = FinalWinPerBit[u1BitIdx].last_pass; |
| 380 | rx_last_delay_bit = u1BitIdx; |
| 381 | } |
| 382 | } |
| 383 | #endif |
| 384 | |
| 385 | #if __ETT__ |
| 386 | mcSHOW_ERR_MSG(("fra dramc_get_rshmoo_pass_cnt = %x\n",dramc_get_rshmoo_pass_cnt())); |
| 387 | mcSHOW_ERR_MSG(("fra femmc_Ready = %d ==\n",p->femmc_Ready)); |
| 388 | #else |
| 389 | print("fra dramc_get_rshmoo_pass_cnt = %x\n",dramc_get_rshmoo_pass_cnt()); |
| 390 | print("fra femmc_Ready = %d ==\n",p->femmc_Ready); |
| 391 | #endif |
| 392 | |
| 393 | if (p->femmc_Ready==0 || |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 394 | ((p->pSavetimeData->Runtime_Shmoo_para.TX_Channel!=RUNTIME_SHMOO_TEST_CHANNEL) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Rank!=RUNTIME_SHMOO_TEST_RANK) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Byte!=RUNTIME_SHMOO_TEST_BYTE))) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 395 | { |
| 396 | #if RUNTIME_SHMOO_TX |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 397 | p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 398 | p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; |
| 399 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = tx_pi_delay-32+RUNTIME_SHMOO_TEST_PI_DELAY_START; |
| 400 | p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay; |
| 401 | p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = tx_dqm_pi_delay-32+RUNTIME_SHMOO_TEST_PI_DELAY_START; |
| 402 | p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay; |
| 403 | if (RUNTIME_SHMOO_TEST_VREF_START<51) |
| 404 | { |
| 405 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 0; |
| 406 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = RUNTIME_SHMOO_TEST_VREF_START; |
| 407 | } |
| 408 | else |
| 409 | { |
| 410 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1; |
| 411 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = RUNTIME_SHMOO_TEST_VREF_START-51+21; |
| 412 | } |
| 413 | p->pSavetimeData->Runtime_Shmoo_para.TX_Channel = RUNTIME_SHMOO_TEST_CHANNEL; |
| 414 | p->pSavetimeData->Runtime_Shmoo_para.TX_Rank = RUNTIME_SHMOO_TEST_RANK; |
| 415 | p->pSavetimeData->Runtime_Shmoo_para.TX_Byte = RUNTIME_SHMOO_TEST_BYTE; |
| 416 | #endif |
| 417 | |
| 418 | #if RUNTIME_SHMOO_RX |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 419 | p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 420 | p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; |
| 421 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 0; |
| 422 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = 0; |
| 423 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 424 | { |
| 425 | p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].first_pass- RUNTIME_SHMOO_RX_TEST_MARGIN; |
| 426 | } |
| 427 | p->pSavetimeData->Runtime_Shmoo_para.RX_Original_delay = p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]; |
| 428 | p->pSavetimeData->Runtime_Shmoo_para.TX_Channel = RUNTIME_SHMOO_TEST_CHANNEL; |
| 429 | p->pSavetimeData->Runtime_Shmoo_para.TX_Rank = RUNTIME_SHMOO_TEST_RANK; |
| 430 | p->pSavetimeData->Runtime_Shmoo_para.TX_Byte = RUNTIME_SHMOO_TEST_BYTE; |
| 431 | #endif |
| 432 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 433 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 434 | else if ((dramc_get_rshmoo_step()) && (p->pSavetimeData->Runtime_Shmoo_para.flag != RUNTIME_SHMOO_END)) |
| 435 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 436 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 437 | if (RUNTIME_SHMOO_FAST_K == 0) |
| 438 | { |
| 439 | p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; |
| 440 | } |
| 441 | else |
| 442 | { |
| 443 | if (dramc_get_rshmoo_pass_cnt() > (RUNTIME_SHMOO_FAST_K-1)) |
| 444 | { |
| 445 | if (p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction==0) |
| 446 | { |
| 447 | p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=1; |
| 448 | } |
| 449 | else |
| 450 | { |
| 451 | p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; |
| 452 | } |
| 453 | |
| 454 | scan_invert_flag = 1; |
| 455 | } |
| 456 | } |
| 457 | |
| 458 | if (scan_invert_flag == 0) |
| 459 | { |
| 460 | if (p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction==0) |
| 461 | { |
| 462 | #if RUNTIME_SHMOO_TX |
| 463 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay += RUNTIME_SHMOO_TEST_PI_DELAY_STEP; |
| 464 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay > p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+RUNTIME_SHMOO_TEST_PI_DELAY_END) |
| 465 | { |
| 466 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay; |
| 467 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; |
| 468 | |
| 469 | if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) |
| 470 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 471 | p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 472 | } |
| 473 | else |
| 474 | { |
| 475 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range==0) |
| 476 | { |
| 477 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value > 50) |
| 478 | { |
| 479 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1; |
| 480 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value -= 30; |
| 481 | } |
| 482 | } |
| 483 | } |
| 484 | } |
| 485 | |
| 486 | p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay += RUNTIME_SHMOO_TEST_PI_DELAY_STEP; |
| 487 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay > p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay+RUNTIME_SHMOO_TEST_PI_DELAY_END) |
| 488 | { |
| 489 | p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay; |
| 490 | } |
| 491 | #endif |
| 492 | |
| 493 | #if RUNTIME_SHMOO_RX |
| 494 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 495 | { |
| 496 | p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] += RUNTIME_SHMOO_TEST_PI_DELAY_STEP; |
| 497 | } |
| 498 | if (p->pSavetimeData->Runtime_Shmoo_para.RX_delay[rx_last_delay_bit] > rx_last_delay+RUNTIME_SHMOO_RX_TEST_MARGIN) |
| 499 | { |
| 500 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 501 | { |
| 502 | p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].first_pass - RUNTIME_SHMOO_RX_TEST_MARGIN; |
| 503 | } |
| 504 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; |
| 505 | if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) |
| 506 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 507 | p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 508 | } |
| 509 | } |
| 510 | #endif |
| 511 | } |
| 512 | else |
| 513 | { |
| 514 | #if RUNTIME_SHMOO_TX |
| 515 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay -= RUNTIME_SHMOO_TEST_PI_DELAY_STEP; |
| 516 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay < p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay) |
| 517 | { |
| 518 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay + (RUNTIME_SHMOO_TEST_PI_DELAY_END+1); |
| 519 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; |
| 520 | |
| 521 | if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) |
| 522 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 523 | p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 524 | } |
| 525 | else |
| 526 | { |
| 527 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range==0) |
| 528 | { |
| 529 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value > 50) |
| 530 | { |
| 531 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1; |
| 532 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value -= 30; |
| 533 | } |
| 534 | } |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay -= RUNTIME_SHMOO_TEST_PI_DELAY_STEP; |
| 539 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay < p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay) |
| 540 | { |
| 541 | p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay + (RUNTIME_SHMOO_TEST_PI_DELAY_END+1); |
| 542 | } |
| 543 | #endif |
| 544 | |
| 545 | #if RUNTIME_SHMOO_RX |
| 546 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 547 | { |
| 548 | p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] -= RUNTIME_SHMOO_TEST_PI_DELAY_STEP; |
| 549 | } |
| 550 | if (p->pSavetimeData->Runtime_Shmoo_para.RX_delay[rx_first_delay_bit] < rx_first_delay-RUNTIME_SHMOO_RX_TEST_MARGIN) |
| 551 | { |
| 552 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 553 | { |
| 554 | p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].last_pass + RUNTIME_SHMOO_RX_TEST_MARGIN; |
| 555 | } |
| 556 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; |
| 557 | if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) |
| 558 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 559 | p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 560 | } |
| 561 | } |
| 562 | #endif |
| 563 | |
| 564 | } |
| 565 | } |
| 566 | else |
| 567 | { |
| 568 | if (p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction==0) |
| 569 | { |
| 570 | #if RUNTIME_SHMOO_TX |
| 571 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay; |
| 572 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; |
| 573 | |
| 574 | if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) |
| 575 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 576 | p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 577 | } |
| 578 | else |
| 579 | { |
| 580 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range==0) |
| 581 | { |
| 582 | if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value > 50) |
| 583 | { |
| 584 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1; |
| 585 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value -= 30; |
| 586 | } |
| 587 | } |
| 588 | } |
| 589 | |
| 590 | p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay; |
| 591 | #endif |
| 592 | |
| 593 | #if RUNTIME_SHMOO_RX |
| 594 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 595 | { |
| 596 | p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].first_pass - RUNTIME_SHMOO_RX_TEST_MARGIN; |
| 597 | } |
| 598 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; |
| 599 | |
| 600 | if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) |
| 601 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 602 | p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 603 | } |
| 604 | #endif |
| 605 | } |
| 606 | else |
| 607 | { |
| 608 | #if RUNTIME_SHMOO_TX |
| 609 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay + (RUNTIME_SHMOO_TEST_PI_DELAY_END+1); |
| 610 | //p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; |
| 611 | |
| 612 | p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay + (RUNTIME_SHMOO_TEST_PI_DELAY_END+1); |
| 613 | #endif |
| 614 | |
| 615 | #if RUNTIME_SHMOO_RX |
| 616 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) |
| 617 | { |
| 618 | p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].last_pass + RUNTIME_SHMOO_RX_TEST_MARGIN; |
| 619 | } |
| 620 | #endif |
| 621 | } |
| 622 | } |
| 623 | } |
| 624 | |
| 625 | #if __ETT__ |
| 626 | mcSHOW_ERR_MSG(("Fra RunTime Shmoo CH%d, Rank%d, Byte%d\n",RUNTIME_SHMOO_TEST_CHANNEL, RUNTIME_SHMOO_TEST_RANK, RUNTIME_SHMOO_TEST_BYTE )); |
| 627 | #else |
| 628 | print("Fra RunTime Shmoo CH%d, Rank%d, Byte%d\n",RUNTIME_SHMOO_TEST_CHANNEL, RUNTIME_SHMOO_TEST_RANK, RUNTIME_SHMOO_TEST_BYTE ); |
| 629 | #endif |
| 630 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 631 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 632 | { |
| 633 | #if RUNTIME_SHMOO_TX |
| 634 | #if __ETT__ |
| 635 | mcSHOW_ERR_MSG(("Fra RunTime Shmoo original K TX Vref = (%d, %d)\n", (u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp]>>6) & 1, u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp] & 0x3f)); |
| 636 | mcSHOW_ERR_MSG(("Fra RunTime Shmoo original K TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+32-RUNTIME_SHMOO_TEST_PI_DELAY_START)); |
| 637 | |
| 638 | mcSHOW_ERR_MSG(("Fra RunTime Shmoo TX Vref = (%d, %d)\n", p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value)); |
| 639 | mcSHOW_ERR_MSG(("Fra RunTime Shmoo TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay)); |
| 640 | #else |
| 641 | print("Fra RunTime Shmoo original K TX Vref = (%d, %d)\n", (u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp]>>6) & 1, u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp] & 0x3f); |
| 642 | print("Fra RunTime Shmoo original K TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+32-RUNTIME_SHMOO_TEST_PI_DELAY_START); |
| 643 | |
| 644 | print("Fra RunTime Shmoo TX Vref = (%d, %d)\n", p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value); |
| 645 | print("Fra RunTime Shmoo TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay); |
| 646 | #endif |
| 647 | #endif |
| 648 | |
| 649 | #if RUNTIME_SHMOO_RX |
| 650 | mcSHOW_ERR_MSG(("Fra RunTime Shmoo K RX Vref = %d\n", p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value)); |
| 651 | mcSHOW_ERR_MSG(("Fra RunTime Shmoo RX Byte%d Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0])); |
| 652 | #endif |
| 653 | |
| 654 | #if RUNTIME_SHMOO_TX |
| 655 | TxWinTransferDelayToUIPI(p, TX_DQ_DQS_MOVE_DQ_DQM, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay, 1, &ui_large_value, &ui_small_value, &pi_value); |
| 656 | TxWinTransferDelayToUIPI(p, TX_DQ_DQS_MOVE_DQ_DQM, p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay, 1, &ui_dqm_large_value, &ui_dqm_small_value, &pi_dqm_value); |
| 657 | |
| 658 | if (RUNTIME_SHMOO_TEST_BYTE == 0) |
| 659 | { |
| 660 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), ui_large_value, SHURK_SELPH_DQ0_TXDLY_DQ0); |
| 661 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), ui_small_value, SHURK_SELPH_DQ2_DLY_DQ0); |
| 662 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), pi_value, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0); |
| 663 | |
| 664 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), ui_dqm_large_value, SHURK_SELPH_DQ1_TXDLY_DQM0); |
| 665 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), ui_dqm_small_value, SHURK_SELPH_DQ3_DLY_DQM0); |
| 666 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), pi_dqm_value, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0); |
| 667 | } |
| 668 | else |
| 669 | { |
| 670 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), ui_large_value, SHURK_SELPH_DQ0_TXDLY_DQ1); |
| 671 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), ui_small_value, SHURK_SELPH_DQ2_DLY_DQ1); |
| 672 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), pi_value, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1); |
| 673 | |
| 674 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), ui_dqm_large_value, SHURK_SELPH_DQ1_TXDLY_DQM1); |
| 675 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), ui_dqm_small_value, SHURK_SELPH_DQ3_DLY_DQM1); |
| 676 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), pi_dqm_value, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1); |
| 677 | } |
| 678 | DramcTXSetVref(p, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value); |
| 679 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 680 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 681 | #if 0 |
| 682 | #if ENABLE_MCK8X_MODE |
| 683 | vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_SHU_CA_DLL0), 0x0, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU); |
| 684 | vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DLL0), 0x0, SHU_B0_DLL0_RG_ARDLL_PHDET_EN_B0_SHU); |
| 685 | vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_SHU_B1_DLL0), 0x0, SHU_B1_DLL0_RG_ARDLL_PHDET_EN_B1_SHU); |
| 686 | #else |
| 687 | vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_CA_DLL_ARPI2), 0x0, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA); |
| 688 | vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_B0_DLL_ARPI2), 0x0, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0); |
| 689 | vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_B1_DLL_ARPI2), 0x0, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1); |
| 690 | #endif |
| 691 | #endif |
| 692 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL1, 0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0); |
| 693 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL1, 0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1); |
| 694 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DLL1, 0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA); |
| 695 | |
| 696 | #endif |
| 697 | |
| 698 | |
| 699 | |
| 700 | #if RUNTIME_SHMOO_RX |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 701 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 702 | if (p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0] <=0) |
| 703 | { |
| 704 | #if 0 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 705 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 706 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ |
| 707 | P_Fld((-p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]),SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) |P_Fld((-p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]),SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0)); |
| 708 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 709 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 710 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ |
| 711 | P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0) |P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0)); |
| 712 | |
| 713 | DramPhyReset(p); |
| 714 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 715 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 716 | for (u1BitIdx=0; u1BitIdx<4; u1BitIdx++) |
| 717 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 718 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE + u1BitIdx*4), 0); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 719 | } |
| 720 | } |
| 721 | else |
| 722 | { |
| 723 | #if 0 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 724 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 725 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ |
| 726 | P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) |P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0)); |
| 727 | |
| 728 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 729 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 730 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ |
| 731 | P_Fld(p->pSavetimeData->Runtime_Shmoo_para.RX_delay,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0) |P_Fld(p->pSavetimeData->Runtime_Shmoo_para.RX_delay,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0)); |
| 732 | |
| 733 | DramPhyReset(p); |
| 734 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 735 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 736 | for (u1BitIdx=0; u1BitIdx<8; u1BitIdx+=2) |
| 737 | { |
| 738 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0+ (DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE) +u1BitIdx*2), \ |
| 739 | P_Fld(((U32)p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx]),SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |\ |
| 740 | P_Fld(((U32)p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx+1]),SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); |
| 741 | |
| 742 | } |
| 743 | } |
| 744 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 745 | |
| 746 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE), p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 747 | #endif |
| 748 | } |
| 749 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 750 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 751 | #if EMMC_READY |
| 752 | write_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData); |
| 753 | #endif |
| 754 | mcSHOW_ERR_MSG(("Fra Save calibration result to emmc\n")); |
| 755 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 756 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 757 | #if RUNTIME_SHMOO_TX |
| 758 | dramc_set_rshmoo_info(p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, p->pSavetimeData->Runtime_Shmoo_para.TX_Channel, |
| 759 | p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, |
| 760 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay, 1, (p->pSavetimeData->Runtime_Shmoo_para.flag == RUNTIME_SHMOO_END) ? 1 : 0); |
| 761 | #endif |
| 762 | |
| 763 | #if RUNTIME_SHMOO_RX |
| 764 | dramc_set_rshmoo_info(p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, p->pSavetimeData->Runtime_Shmoo_para.TX_Channel, |
| 765 | p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, |
| 766 | p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0], 1, (p->pSavetimeData->Runtime_Shmoo_para.flag == RUNTIME_SHMOO_END) ? 1 : 0); |
| 767 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 768 | // vAutoRefreshSwitch(p, DISABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 769 | |
| 770 | #endif |
| 771 | |
| 772 | p->channel = backup_channel; |
| 773 | p->rank = backup_rank; |
| 774 | } |
| 775 | #endif |
| 776 | |
| 777 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 778 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 779 | #ifdef FIRST_BRING_UP |
| 780 | void Test_Broadcast_Feature(DRAMC_CTX_T *p) |
| 781 | { |
| 782 | U32 u4RegBackupAddress[] = |
| 783 | { |
| 784 | (DRAMC_REG_SHURK_SELPH_DQ2), |
| 785 | (DRAMC_REG_SHURK_SELPH_DQ2 + SHIFT_TO_CHB_ADDR), |
| 786 | |
| 787 | (DDRPHY_REG_SHU_RK_B0_DQ0), |
| 788 | (DDRPHY_REG_SHU_RK_B0_DQ0 + SHIFT_TO_CHB_ADDR), |
| 789 | }; |
| 790 | U32 read_value; |
| 791 | U32 backup_broadcast; |
| 792 | |
| 793 | backup_broadcast = GetDramcBroadcast(); |
| 794 | |
| 795 | DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); |
| 796 | |
| 797 | DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 798 | |
| 799 | DramcBroadcastOnOff(DRAMC_BROADCAST_ON); |
| 800 | |
| 801 | vIO32Write4B(DRAMC_REG_SHURK_SELPH_DQ2, 0xA55A00FF); |
| 802 | vIO32Write4B(DDRPHY_REG_SHU_RK_B0_DQ0, 0xA55A00FF); |
| 803 | |
| 804 | read_value = u4IO32Read4B(DRAMC_REG_SHURK_SELPH_DQ2 + SHIFT_TO_CHB_ADDR); |
| 805 | if (read_value != 0xA55A00FF) |
| 806 | { |
| 807 | mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n")); |
| 808 | while (1); |
| 809 | } |
| 810 | |
| 811 | read_value = u4IO32Read4B(DDRPHY_REG_SHU_RK_B0_DQ0 + SHIFT_TO_CHB_ADDR); |
| 812 | if (read_value != 0xA55A00FF) |
| 813 | { |
| 814 | mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n")); |
| 815 | while (1); |
| 816 | } |
| 817 | |
| 818 | DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); |
| 819 | |
| 820 | DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 821 | |
| 822 | DramcBroadcastOnOff(backup_broadcast); |
| 823 | } |
| 824 | #endif |
| 825 | |
| 826 | #if __ETT__ |
| 827 | void ett_set_emi_rank1_address(void) |
| 828 | { |
| 829 | static unsigned int remap_rank1_done = 0; |
| 830 | |
| 831 | if (!remap_rank1_done) |
| 832 | { |
| 833 | #ifndef MT6880_FPGA |
| 834 | set_emi_before_rank1_mem_test(); |
| 835 | #endif |
| 836 | remap_rank1_done = 1; |
| 837 | } |
| 838 | } |
| 839 | #endif |
| 840 | |
| 841 | static void mem_test_address_calculation(DRAMC_CTX_T * p, U32 uiSrcAddr, U32*pu4Dest) |
| 842 | { |
| 843 | #if __ETT__ |
| 844 | ett_set_emi_rank1_address(); |
| 845 | |
| 846 | *pu4Dest = uiSrcAddr - RANK0_START_VA + RANK1_START_VA; |
| 847 | #else |
| 848 | *pu4Dest = uiSrcAddr + p->ranksize[RANK_0]; |
| 849 | #endif |
| 850 | } |
| 851 | |
| 852 | #if CPU_RW_TEST_AFTER_K |
| 853 | static void vDramCPUReadWriteTestAfterCalibration(DRAMC_CTX_T *p) |
| 854 | { |
| 855 | U8 u1DumpInfo=0, u1RankIdx; |
| 856 | U32 uiLen, uiRankdAddr[RANK_MAX]; |
| 857 | U32 pass_count, err_count; |
| 858 | U64 count, uiFixedAddr; //[FOR_CHROMEOS] Change type from U32 to U64 |
| 859 | uiLen = 0xffff; |
| 860 | |
| 861 | #if GATING_ONLY_FOR_DEBUG |
| 862 | DramcGatingDebugInit(p); |
| 863 | #endif |
| 864 | |
| 865 | uiRankdAddr[0] = DDR_BASE; |
| 866 | mem_test_address_calculation(p, DDR_BASE, &uiRankdAddr[1]); |
| 867 | |
| 868 | for(u1RankIdx =0; u1RankIdx< p->support_rank_num; u1RankIdx++) |
| 869 | { |
| 870 | u1DumpInfo=0; |
| 871 | err_count=0; |
| 872 | pass_count=0; |
| 873 | |
| 874 | #if !__ETT__ |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 875 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 876 | if (u1RankIdx >= 1) |
| 877 | continue; |
| 878 | #endif |
| 879 | |
| 880 | #if GATING_ONLY_FOR_DEBUG |
| 881 | DramcGatingDebugRankSel(p, u1RankIdx); |
| 882 | #endif |
| 883 | |
| 884 | uiFixedAddr = uiRankdAddr[u1RankIdx]; |
| 885 | |
| 886 | for (count= 0; count<uiLen; count+=4) |
| 887 | { |
| 888 | *(volatile unsigned int *)(count +uiFixedAddr) = count + (0x5a5a <<16); |
| 889 | } |
| 890 | |
| 891 | for (count=0; count<uiLen; count+=4) |
| 892 | { |
| 893 | if (*(volatile unsigned int *)(count +uiFixedAddr) != count + (0x5a5a <<16)) |
| 894 | { |
| 895 | //mcSHOW_DBG_MSG(("[Fail] Addr %xh = %xh\n",count, *(volatile unsigned int *)(count))); |
| 896 | err_count++; |
| 897 | } |
| 898 | else |
| 899 | pass_count ++; |
| 900 | } |
| 901 | |
| 902 | #if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 903 | if (err_count==0) |
| 904 | { |
| 905 | #if __ETT__ |
| 906 | mcSHOW_ERR_MSG(("CH %c,RANK %d,BYTE %d,VRANGE %d,VREF %d,PI %d,MEM_RESULT PASS\n", |
| 907 | p->pSavetimeData->Runtime_Shmoo_para.TX_Channel == 0 ? 'A' : 'B', |
| 908 | p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, |
| 909 | p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, |
| 910 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, |
| 911 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, |
| 912 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay)); |
| 913 | #else |
| 914 | print("CH %c,RANK %d,BYTE %d,VRANGE %d,VREF %d,PI %d,MEM_RESULT PASS\n", |
| 915 | p->pSavetimeData->Runtime_Shmoo_para.TX_Channel == 0 ? 'A' : 'B', |
| 916 | p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, |
| 917 | p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, |
| 918 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, |
| 919 | p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, |
| 920 | p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay); |
| 921 | #endif |
| 922 | } |
| 923 | #else |
| 924 | if(err_count) |
| 925 | { |
| 926 | mcSHOW_DBG_MSG2(("[MEM_TEST] Rank %d Fail.", u1RankIdx)); |
| 927 | u1DumpInfo =1; |
| 928 | #if defined(SLT) |
| 929 | mcSHOW_ERR_MSG(("\n[EMI] EMI_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__)); |
| 930 | while(1); |
| 931 | #endif |
| 932 | } |
| 933 | else |
| 934 | { |
| 935 | mcSHOW_DBG_MSG2(("[MEM_TEST] Rank %d OK.", u1RankIdx)); |
| 936 | } |
| 937 | mcSHOW_DBG_MSG2(("(uiFixedAddr 0x%llX, Pass count =%d, Fail count =%d)\n", uiFixedAddr, pass_count, err_count)); //[FOR_CHROMEOS] |
| 938 | #endif |
| 939 | } |
| 940 | |
| 941 | if(u1DumpInfo) |
| 942 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 943 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 944 | #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) |
| 945 | DramcDumpDebugInfo(p); |
| 946 | #endif |
| 947 | } |
| 948 | |
| 949 | #if GATING_ONLY_FOR_DEBUG |
| 950 | DramcGatingDebugExit(p); |
| 951 | #endif |
| 952 | } |
| 953 | #endif |
| 954 | |
| 955 | |
| 956 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 957 | #if !EMMC_READY |
| 958 | u32 g_dram_save_time_init_done[DRAM_DFS_SRAM_MAX] = {0}; |
| 959 | SAVE_TIME_FOR_CALIBRATION_T SaveTimeDataByShuffle[DRAM_DFS_SRAM_MAX]; |
| 960 | #endif |
| 961 | static DRAM_STATUS_T DramcSave_Time_For_Cal_End(DRAMC_CTX_T *p) |
| 962 | { |
| 963 | if (!u1IsLP4Family(p->dram_type)) |
| 964 | return DRAM_FAIL; |
| 965 | |
| 966 | if (p->femmc_Ready == 0) |
| 967 | { |
| 968 | #if EMMC_READY |
| 969 | write_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData); |
| 970 | mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to emmc\n")); |
| 971 | #else |
| 972 | g_dram_save_time_init_done[vGet_Current_SRAMIdx(p)] = 1; |
| 973 | memcpy(&(SaveTimeDataByShuffle[vGet_Current_SRAMIdx(p)]), p->pSavetimeData, sizeof(SAVE_TIME_FOR_CALIBRATION_T)); |
| 974 | mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to SW memory\n")); |
| 975 | #endif |
| 976 | } |
| 977 | else |
| 978 | { |
| 979 | mcSHOW_DBG_MSG(("[FAST_K] Bypass saving calibration result to emmc\n")); |
| 980 | } |
| 981 | |
| 982 | return DRAM_OK; |
| 983 | } |
| 984 | |
| 985 | static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p) |
| 986 | { |
| 987 | if (!u1IsLP4Family(p->dram_type)) |
| 988 | return DRAM_FAIL; |
| 989 | |
| 990 | if (doe_get_config("fullk")) |
| 991 | return DRAM_FAIL; |
| 992 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 993 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 994 | #if EMMC_READY |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 995 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 996 | if (read_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData) < 0) |
| 997 | { |
| 998 | p->femmc_Ready = 0; |
| 999 | memset(p->pSavetimeData, 0, sizeof(SAVE_TIME_FOR_CALIBRATION_T)); |
| 1000 | } |
| 1001 | else |
| 1002 | { |
| 1003 | p->femmc_Ready = 1; |
| 1004 | } |
| 1005 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1006 | #else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1007 | |
| 1008 | if (g_dram_save_time_init_done[vGet_Current_SRAMIdx(p)] == 0) |
| 1009 | { |
| 1010 | p->femmc_Ready = 0; |
| 1011 | memset(p->pSavetimeData, 0, sizeof(SAVE_TIME_FOR_CALIBRATION_T)); |
| 1012 | } |
| 1013 | else |
| 1014 | { |
| 1015 | memcpy(p->pSavetimeData, &(SaveTimeDataByShuffle[vGet_Current_SRAMIdx(p)]), sizeof(SAVE_TIME_FOR_CALIBRATION_T)); |
| 1016 | p->femmc_Ready = 1; |
| 1017 | } |
| 1018 | #endif |
| 1019 | |
| 1020 | if (p->femmc_Ready == 1) |
| 1021 | { |
| 1022 | if (p->frequency < 1600) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1023 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1024 | p->Bypass_RDDQC = 1; |
| 1025 | p->Bypass_RXWINDOW = 1; |
| 1026 | p->Bypass_TXWINDOW = 1; |
| 1027 | } |
| 1028 | else |
| 1029 | { |
| 1030 | p->Bypass_RDDQC = 1; |
| 1031 | p->Bypass_RXWINDOW = !ENABLE_RX_TRACKING; |
| 1032 | p->Bypass_TXWINDOW = 0; |
| 1033 | } |
| 1034 | |
| 1035 | #if RUNTIME_SHMOO_RELEATED_FUNCTION |
| 1036 | p->Bypass_RDDQC = 1; |
| 1037 | p->Bypass_RXWINDOW = 1; |
| 1038 | p->Bypass_TXWINDOW = 1; |
| 1039 | #endif |
| 1040 | } |
| 1041 | |
| 1042 | #if EMMC_READY |
| 1043 | mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SRAM_SHU%d, femmc_Ready=%d\n", vGet_Current_SRAMIdx(p), p->femmc_Ready)); |
| 1044 | #else |
| 1045 | mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SRAM_SHU%d, Init_done=%d, femmc_Ready=%d\n", vGet_Current_SRAMIdx(p), g_dram_save_time_init_done[vGet_Current_SRAMIdx(p)], p->femmc_Ready)); |
| 1046 | #endif |
| 1047 | mcSHOW_DBG_MSG(("[FAST_K] Bypass_RDDQC %d, Bypass_RXWINDOW=%d, Bypass_TXWINDOW=%d\n", p->Bypass_RDDQC, p->Bypass_RXWINDOW, p->Bypass_TXWINDOW)); |
| 1048 | |
| 1049 | return DRAM_OK; |
| 1050 | } |
| 1051 | #endif |
| 1052 | |
| 1053 | #if ENABLE_RANK_NUMBER_AUTO_DETECTION |
| 1054 | static void DramRankNumberDetection(DRAMC_CTX_T *p) |
| 1055 | { |
| 1056 | U8 u1RankBak; |
| 1057 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1058 | u1RankBak = u1GetRank(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1059 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1060 | vSetPHY2ChannelMapping(p, CHANNEL_A); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1061 | vSetRank(p, RANK_1); |
| 1062 | |
| 1063 | if (DramcWriteLeveling(p, AUTOK_ON, PI_BASED) == DRAM_OK) |
| 1064 | { |
| 1065 | p->support_rank_num = RANK_DUAL; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1066 | vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 0, SA_RESERVE_SINGLE_RANK); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1067 | } |
| 1068 | else |
| 1069 | { |
| 1070 | p->support_rank_num = RANK_SINGLE; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1071 | vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SINGLE_RANK); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1072 | } |
| 1073 | mcSHOW_DBG_MSG2(("[RankNumberDetection] %d\n", p->support_rank_num)); |
| 1074 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1075 | vSetRank(p, u1RankBak); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1076 | } |
| 1077 | #endif |
| 1078 | |
| 1079 | #if (FOR_DV_SIMULATION_USED == 0) |
| 1080 | static void UpdateGlobal10GBEnVariables(DRAMC_CTX_T *p) |
| 1081 | { |
| 1082 | p->u110GBEn[RANK_0] = (get_row_width_by_emi(RANK_0) >= 18) ? ENABLE : DISABLE; |
| 1083 | p->u110GBEn[RANK_1] = (get_row_width_by_emi(RANK_1) >= 18) ? ENABLE : DISABLE; |
| 1084 | //mcSHOW_DBG_MSG(("[10GBEn] RANK0=%d, RANK1=%d\n", p->u110GBEn[RANK_0], p->u110GBEn[RANK_1])); |
| 1085 | } |
| 1086 | #endif |
| 1087 | |
| 1088 | void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p) |
| 1089 | { |
| 1090 | U8 u1RankMax; |
| 1091 | S8 s1RankIdx; |
| 1092 | |
| 1093 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 1094 | DramcRxdqsGatingPreProcess(p); |
| 1095 | #endif |
| 1096 | |
| 1097 | if (p->support_rank_num == RANK_DUAL) |
| 1098 | u1RankMax = RANK_MAX; |
| 1099 | else |
| 1100 | u1RankMax = RANK_1; |
| 1101 | |
| 1102 | for (s1RankIdx = RANK_0; s1RankIdx < u1RankMax; s1RankIdx++) |
| 1103 | { |
| 1104 | vSetRank(p, s1RankIdx); |
| 1105 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1106 | vAutoRefreshSwitch(p, ENABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1107 | dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0); |
| 1108 | DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF, NORMAL_K); |
| 1109 | |
| 1110 | #if MRW_CHECK_ONLY |
| 1111 | mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); |
| 1112 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1113 | vAutoRefreshSwitch(p, DISABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1114 | } |
| 1115 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1116 | vSetRank(p, RANK_0); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1117 | |
| 1118 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 1119 | DramcRxdqsGatingPostProcess(p); |
| 1120 | #endif |
| 1121 | } |
| 1122 | |
| 1123 | static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInfo) |
| 1124 | { |
| 1125 | U8 u1RankIdx, u1DieNumber = 0; //u1ChannelIdx, u1RankMax, |
| 1126 | U16 u2Density; |
| 1127 | U16 u2MR7; |
| 1128 | U16 u2MR8 = 0; |
| 1129 | U64 u8Size = 0, u8Size_backup = 0; |
| 1130 | //U64 u8ChannelSize; |
| 1131 | //U32 u4ChannelNumber = 1, u4RankNumber = 1; |
| 1132 | |
| 1133 | if (p->revision_id != REVISION_ID_MAGIC) |
| 1134 | return 0; |
| 1135 | |
| 1136 | vSetPHY2ChannelMapping(p, CHANNEL_A); |
| 1137 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1138 | |
| 1139 | DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1140 | p->vendor_id &= 0xFF; |
| 1141 | mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Vendor %x.\n", p->vendor_id)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1142 | |
| 1143 | DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1144 | mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Revision %x.\n", p->revision_id)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1145 | |
| 1146 | DramcModeRegReadByRank(p, RANK_0, 7, &u2MR7); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1147 | mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Revision 2 %x.\n", u2MR7)); |
| 1148 | #if (!__ETT__) && (FOR_DV_SIMULATION_USED==0) |
| 1149 | set_dram_mr(5, p->vendor_id); |
| 1150 | set_dram_mr(6, p->revision_id); |
| 1151 | set_dram_mr(7, u2MR7); |
| 1152 | #endif |
| 1153 | if (DramInfo != NULL) |
| 1154 | { |
| 1155 | DramInfo->u2MR5VendorID = p->vendor_id; |
| 1156 | DramInfo->u2MR6RevisionID = p->revision_id; |
| 1157 | |
| 1158 | for(u1RankIdx =0; u1RankIdx<RANK_MAX; u1RankIdx++) |
| 1159 | DramInfo->u8MR8Density[u1RankIdx] =0; |
| 1160 | } |
| 1161 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1162 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1163 | for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++) |
| 1164 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1165 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1166 | if ((p->aru4CalExecuteFlag[u1ChannelIdx][u1RankIdx] != 0) && \ |
| 1167 | (p->aru4CalResultFlag[u1ChannelIdx][u1RankIdx] == 0)) |
| 1168 | #endif |
| 1169 | { |
| 1170 | DramcModeRegReadByRank(p, u1RankIdx, 0, &(gu2MR0_Value[u1RankIdx])); |
| 1171 | mcSHOW_DBG_MSG2(("MR0 0x%x\n", gu2MR0_Value[u1RankIdx])); |
| 1172 | |
| 1173 | DramcModeRegReadByRank(p, u1RankIdx, 8, &u2Density); |
| 1174 | mcSHOW_DBG_MSG2(("MR8 0x%x\n", u2Density)); |
| 1175 | u2MR8 |= (u2Density & 0xFF) << (u1RankIdx * 8); |
| 1176 | |
| 1177 | u1DieNumber = 1; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1178 | if (((u2Density >> 6) & 0x3) == 1) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1179 | u1DieNumber = 2; |
| 1180 | |
| 1181 | if (DramInfo != NULL) |
| 1182 | DramInfo->u1DieNum[u1RankIdx] = u1DieNumber; |
| 1183 | |
| 1184 | u2Density = (u2Density >> 2) & 0xf; |
| 1185 | |
| 1186 | switch (u2Density) |
| 1187 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1188 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1189 | case 0x0: |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1190 | u8Size = 0x20000000; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1191 | //mcSHOW_DBG_MSG(("[EMI]DRAM density = 4Gb\n")); |
| 1192 | break; |
| 1193 | case 0x1: |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1194 | u8Size = 0x30000000; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1195 | //mcSHOW_DBG_MSG(("[EMI]DRAM density = 6Gb\n")); |
| 1196 | break; |
| 1197 | case 0x2: |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1198 | u8Size = 0x40000000; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1199 | //mcSHOW_DBG_MSG(("[EMI]DRAM density = 8Gb\n")); |
| 1200 | break; |
| 1201 | case 0x3: |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1202 | u8Size = 0x60000000; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1203 | //mcSHOW_DBG_MSG(("[EMI]DRAM density = 12Gb\n")); |
| 1204 | break; |
| 1205 | case 0x4: |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1206 | u8Size = 0x80000000; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1207 | //mcSHOW_DBG_MSG(("[EMI]DRAM density = 16Gb\n")); |
| 1208 | break; |
| 1209 | case 0x5: |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1210 | u8Size = 0xc0000000; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1211 | //mcSHOW_DBG_MSG(("[EMI]DRAM density = 24Gb\n")); |
| 1212 | break; |
| 1213 | case 0x6: |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1214 | u8Size = 0x100000000L; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1215 | //mcSHOW_DBG_MSG(("[EMI]DRAM density = 32Gb\n")); |
| 1216 | break; |
| 1217 | default: |
| 1218 | u8Size = 0; //reserved |
| 1219 | } |
| 1220 | |
| 1221 | #if (fcFOR_CHIP_ID == fc8195) |
| 1222 | if (p->support_channel_num == CHANNEL_SINGLE) |
| 1223 | u8Size >>= 1; |
| 1224 | #endif |
| 1225 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1226 | if (u8Size_backup < u8Size) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1227 | { |
| 1228 | u8Size_backup = u8Size; |
| 1229 | p->density = u2Density; |
| 1230 | } |
| 1231 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1232 | p->ranksize[u1RankIdx] = u8Size * u1DieNumber; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1233 | |
| 1234 | if (DramInfo != NULL) |
| 1235 | { |
| 1236 | DramInfo->u8MR8Density[u1RankIdx] = p->ranksize[u1RankIdx]; |
| 1237 | } |
| 1238 | } |
| 1239 | DramInfo->u4RankNum = p->support_rank_num; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1240 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1241 | mcSHOW_DBG_MSG2(("RK%d, DieNum %d, Density %dGb, RKsize %dGb.\n\n", u1RankIdx, u1DieNumber, (U32)(u8Size >> 27), (U32)(p->ranksize[u1RankIdx] >> 27))); |
| 1242 | } |
| 1243 | #if (!__ETT__) && (FOR_DV_SIMULATION_USED==0) |
| 1244 | set_dram_mr(8, u2MR8); |
| 1245 | #endif |
| 1246 | return 0; |
| 1247 | } |
| 1248 | |
| 1249 | static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) |
| 1250 | { |
| 1251 | U8 u1RankMax; |
| 1252 | S8 s1RankIdx; |
| 1253 | //DRAM_STATUS_T VrefStatus; |
| 1254 | |
| 1255 | #ifdef DDR_INIT_TIME_PROFILING |
| 1256 | U32 CPU_Cycle; |
| 1257 | TimeProfileBegin(); |
| 1258 | #endif |
| 1259 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1260 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1261 | if((p->frequency >= 2133) && (p->rank == RANK_0)) |
| 1262 | //if (p->rank == RANK_0) |
| 1263 | DramcRXInputBufferOffsetCal(p); |
| 1264 | |
| 1265 | #ifdef DDR_INIT_TIME_PROFILING |
| 1266 | CPU_Cycle=TimeProfileEnd(); |
| 1267 | mcSHOW_TIME_MSG(("\tRX input cal takes %d us\n", CPU_Cycle)); |
| 1268 | TimeProfileBegin(); |
| 1269 | #endif |
| 1270 | #endif |
| 1271 | |
| 1272 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 1273 | DramcRxdqsGatingPreProcess(p); |
| 1274 | #endif |
| 1275 | |
| 1276 | if (p->support_rank_num==RANK_DUAL) |
| 1277 | u1RankMax = RANK_MAX; |
| 1278 | else |
| 1279 | u1RankMax = RANK_1; |
| 1280 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1281 | //vAutoRefreshSwitch(p, DISABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1282 | vAutoRefreshSwitch(p, DISABLE); |
| 1283 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1284 | #if 1 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1285 | for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) |
| 1286 | { |
| 1287 | vSetRank(p, s1RankIdx); |
| 1288 | #if PINMUX_AUTO_TEST_PER_BIT_CA |
| 1289 | CheckCAPinMux(p); |
| 1290 | #endif |
| 1291 | |
| 1292 | CmdBusTrainingLP45(p, AUTOK_OFF, NORMAL_K); |
| 1293 | |
| 1294 | #if ENABLE_EYESCAN_GRAPH |
| 1295 | if (GetEyeScanEnable(p, EYESCAN_TYPE_CBT) == ENABLE) |
| 1296 | { |
| 1297 | CmdBusTrainingLP45(p, AUTOK_OFF, EYESCAN_K); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1298 | print_EYESCAN_LOG_message(p, EYESCAN_TYPE_CBT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1299 | } |
| 1300 | #endif |
| 1301 | |
| 1302 | #ifdef DDR_INIT_TIME_PROFILING |
| 1303 | CPU_Cycle=TimeProfileEnd(); |
| 1304 | mcSHOW_TIME_MSG(("\tRank %d CBT takes %d us\n", s1RankIdx, CPU_Cycle)); |
| 1305 | TimeProfileBegin(); |
| 1306 | #endif |
| 1307 | } |
| 1308 | vSetRank(p, RANK_0); |
| 1309 | |
| 1310 | #if __Petrus_TO_BE_PORTING__ |
| 1311 | No_Parking_On_CLRPLL(p); |
| 1312 | #endif |
| 1313 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1314 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1315 | ShuffleDfsToOriginalFSP(p); |
| 1316 | #endif |
| 1317 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1318 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1319 | for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) |
| 1320 | { |
| 1321 | vSetRank(p, s1RankIdx); |
| 1322 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1323 | vAutoRefreshSwitch(p, DISABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1324 | |
| 1325 | #if (!WCK_LEVELING_FM_WORKAROUND) |
| 1326 | if (u1IsLP4Family(p->dram_type)) |
| 1327 | #endif |
| 1328 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1329 | if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1330 | { |
| 1331 | mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); |
| 1332 | |
| 1333 | DramcWriteLeveling(p, AUTOK_OFF, PI_BASED); |
| 1334 | |
| 1335 | mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n")); |
| 1336 | } |
| 1337 | } |
| 1338 | |
| 1339 | #ifdef DDR_INIT_TIME_PROFILING |
| 1340 | CPU_Cycle=TimeProfileEnd(); |
| 1341 | mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle)); |
| 1342 | TimeProfileBegin(); |
| 1343 | #endif |
| 1344 | } |
| 1345 | vSetRank(p, RANK_0); |
| 1346 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1347 | #if ENABLE_WDQS_MODE_2 |
| 1348 | if (!(u1IsLP4Div4DDR800(p)) && (p->frequency <= 800) && (p->support_rank_num == RANK_DUAL)) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1349 | WriteLevelingPosCal(p, PI_BASED); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1350 | #elif ENABLE_TX_WDQS |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1351 | if (!(u1IsLP4Div4DDR800(p)) && (p->support_rank_num == RANK_DUAL)) |
| 1352 | WriteLevelingPosCal(p, PI_BASED); |
| 1353 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1354 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1355 | |
| 1356 | for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) |
| 1357 | { |
| 1358 | vSetRank(p, s1RankIdx); |
| 1359 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1360 | #if 1 |
| 1361 | vAutoRefreshSwitch(p, DISABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1362 | |
| 1363 | #if (!WCK_LEVELING_FM_WORKAROUND) |
| 1364 | if (u1IsLP4Family(p->dram_type)) |
| 1365 | #endif |
| 1366 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1367 | if ((!((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (p->rank == RANK_1))) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1368 | && (!(vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE))) // skip for DDR400 |
| 1369 | { |
| 1370 | //mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); |
| 1371 | |
| 1372 | DramcWriteLeveling(p, AUTOK_ON, PI_BASED); |
| 1373 | |
| 1374 | //mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n")); |
| 1375 | } |
| 1376 | |
| 1377 | #ifdef DDR_INIT_TIME_PROFILING |
| 1378 | CPU_Cycle=TimeProfileEnd(); |
| 1379 | mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle)); |
| 1380 | TimeProfileBegin(); |
| 1381 | #endif |
| 1382 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1383 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1384 | |
| 1385 | #if LJPLL_FREQ_DEBUG_LOG |
| 1386 | DDRPhyFreqMeter(p); |
| 1387 | #endif |
| 1388 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1389 | vAutoRefreshSwitch(p, ENABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1390 | |
| 1391 | dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0); |
| 1392 | |
| 1393 | #ifdef DDR_INIT_TIME_PROFILING |
| 1394 | CPU_Cycle=TimeProfileEnd(); |
| 1395 | mcSHOW_TIME_MSG(("\tRank %d Gating takes %d us\n", s1RankIdx, CPU_Cycle)); |
| 1396 | TimeProfileBegin(); |
| 1397 | #endif |
| 1398 | |
| 1399 | #if LJPLL_FREQ_DEBUG_LOG |
| 1400 | DDRPhyFreqMeter(p); |
| 1401 | #endif |
| 1402 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1403 | #if ENABLE_RX_INPUT_BUFF_OFF_K |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1404 | if((p->frequency >= 2133) && (p->rank == RANK_0)) |
| 1405 | DramcRXInputBufferOffsetCal(p); |
| 1406 | |
| 1407 | #ifdef DDR_INIT_TIME_PROFILING |
| 1408 | CPU_Cycle=TimeProfileEnd(); |
| 1409 | mcSHOW_TIME_MSG(("\tRX input cal takes %d us\n", CPU_Cycle)); |
| 1410 | TimeProfileBegin(); |
| 1411 | #endif |
| 1412 | #endif |
| 1413 | |
| 1414 | DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF, NORMAL_K); |
| 1415 | |
| 1416 | #ifdef DDR_INIT_TIME_PROFILING |
| 1417 | CPU_Cycle=TimeProfileEnd(); |
| 1418 | mcSHOW_TIME_MSG(("\tRank %d RX RDDQC takes %d us\n", s1RankIdx, CPU_Cycle)); |
| 1419 | TimeProfileBegin(); |
| 1420 | #endif |
| 1421 | |
| 1422 | #if LJPLL_FREQ_DEBUG_LOG |
| 1423 | DDRPhyFreqMeter(p); |
| 1424 | #endif |
| 1425 | |
| 1426 | #if MRW_CHECK_ONLY |
| 1427 | mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); |
| 1428 | #endif |
| 1429 | |
| 1430 | DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_DQM, FALSE, AUTOK_OFF); |
| 1431 | |
| 1432 | if (Get_Vref_Calibration_OnOff(p)==VREF_CALI_ON) |
| 1433 | { |
| 1434 | DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, TRUE, AUTOK_OFF); |
| 1435 | } |
| 1436 | |
| 1437 | #if PINMUX_AUTO_TEST_PER_BIT_TX |
| 1438 | CheckTxPinMux(p); |
| 1439 | #endif |
| 1440 | DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, FALSE, AUTOK_OFF); |
| 1441 | |
| 1442 | #if TX_K_DQM_WITH_WDBI |
| 1443 | if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON)) |
| 1444 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1445 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1446 | //mcSHOW_DBG_MSG(("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n")); |
| 1447 | vSwitchWriteDBISettings(p, DBI_ON); |
| 1448 | DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQM_ONLY, FALSE, AUTOK_OFF); |
| 1449 | vSwitchWriteDBISettings(p, DBI_OFF); |
| 1450 | } |
| 1451 | #endif |
| 1452 | |
| 1453 | #if ENABLE_EYESCAN_GRAPH |
| 1454 | if (GetEyeScanEnable(p, EYESCAN_TYPE_TX) == ENABLE) |
| 1455 | { |
| 1456 | Dramc_K_TX_EyeScan_Log(p); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1457 | print_EYESCAN_LOG_message(p, EYESCAN_TYPE_TX); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1458 | } |
| 1459 | #endif |
| 1460 | |
| 1461 | #ifdef DDR_INIT_TIME_PROFILING |
| 1462 | CPU_Cycle=TimeProfileEnd(); |
| 1463 | mcSHOW_TIME_MSG(("\tRank %d TX calibration takes %d us\n", s1RankIdx, CPU_Cycle)); |
| 1464 | TimeProfileBegin(); |
| 1465 | #endif |
| 1466 | |
| 1467 | #if LJPLL_FREQ_DEBUG_LOG |
| 1468 | DDRPhyFreqMeter(p); |
| 1469 | #endif |
| 1470 | |
| 1471 | DramcRxdatlatCal(p); |
| 1472 | |
| 1473 | #ifdef DDR_INIT_TIME_PROFILING |
| 1474 | CPU_Cycle=TimeProfileEnd(); |
| 1475 | mcSHOW_TIME_MSG(("\tRank %d Datlat takes %d us\n", s1RankIdx, CPU_Cycle)); |
| 1476 | TimeProfileBegin(); |
| 1477 | #endif |
| 1478 | |
| 1479 | #if LJPLL_FREQ_DEBUG_LOG |
| 1480 | DDRPhyFreqMeter(p); |
| 1481 | #endif |
| 1482 | |
| 1483 | #if PINMUX_AUTO_TEST_PER_BIT_RX |
| 1484 | CheckRxPinMux(p); |
| 1485 | #endif |
| 1486 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1487 | DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, NORMAL_K); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1488 | |
| 1489 | #ifdef DDR_INIT_TIME_PROFILING |
| 1490 | CPU_Cycle=TimeProfileEnd(); |
| 1491 | mcSHOW_TIME_MSG(("\tRank %d RX calibration takes %d us\n", s1RankIdx, CPU_Cycle)); |
| 1492 | TimeProfileBegin(); |
| 1493 | #endif |
| 1494 | // DramcRxdqsGatingCal(p); |
| 1495 | |
| 1496 | #if ENABLE_EYESCAN_GRAPH |
| 1497 | if (GetEyeScanEnable(p, EYESCAN_TYPE_RX) == ENABLE) |
| 1498 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1499 | DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, EYESCAN_K); |
| 1500 | print_EYESCAN_LOG_message(p, EYESCAN_TYPE_RX); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1501 | } |
| 1502 | #endif |
| 1503 | |
| 1504 | #if (SIMULATION_RX_DVS == 1) |
| 1505 | if (p->frequency >=2133) |
| 1506 | DramcRxDVSWindowCal(p); |
| 1507 | #endif |
| 1508 | |
| 1509 | #if TX_OE_CALIBATION && !ENABLE_WDQS_MODE_2 |
| 1510 | if(p->frequency >= 1600) |
| 1511 | { |
| 1512 | DramcTxOECalibration(p); |
| 1513 | } |
| 1514 | #endif |
| 1515 | |
| 1516 | vAutoRefreshSwitch(p, DISABLE); |
| 1517 | |
| 1518 | #if ENABLE_TX_TRACKING |
| 1519 | DramcDQSOSCSetMR18MR19(p); |
| 1520 | DramcDQSOSCMR23(p); |
| 1521 | #endif |
| 1522 | |
| 1523 | } |
| 1524 | |
| 1525 | #if __Petrus_TO_BE_PORTING__ |
| 1526 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 1527 | if(p->femmc_Ready==0) |
| 1528 | #endif |
| 1529 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1530 | if(p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1531 | { |
| 1532 | U8 u1ByteIdx, u1HighFreqRXVref[2]; |
| 1533 | for(u1ByteIdx =0 ; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++) |
| 1534 | { |
| 1535 | u1HighFreqRXVref[u1ByteIdx] = (gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx] + gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx]) >> 1; |
| 1536 | mcSHOW_DBG_MSG(("RX Vref Byte%d (u1HighFreqRXVref) = %d = (%d+ %d)>>1\n", u1ByteIdx, u1HighFreqRXVref[u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx])); |
| 1537 | } |
| 1538 | |
| 1539 | for(s1RankIdx=RANK_0; s1RankIdx < u1RankMax; s1RankIdx++) |
| 1540 | { |
| 1541 | vSetRank(p, s1RankIdx); |
| 1542 | DramcRxWindowPerbitCal((DRAMC_CTX_T *) p, 1, u1HighFreqRXVref); |
| 1543 | } |
| 1544 | } |
| 1545 | } |
| 1546 | #endif |
| 1547 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1548 | vSetRank(p, RANK_0); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1549 | |
| 1550 | #if ENABLE_TX_TRACKING |
| 1551 | DramcDQSOSCShuSettings(p); |
| 1552 | #endif |
| 1553 | |
| 1554 | #if (SIMULATION_GATING && GATING_ADJUST_TXDLY_FOR_TRACKING) |
| 1555 | DramcRxdqsGatingPostProcess(p); |
| 1556 | #endif |
| 1557 | |
| 1558 | #if TDQSCK_PRECALCULATION_FOR_DVFS |
| 1559 | DramcDQSPrecalculation_preset(p); |
| 1560 | #endif |
| 1561 | |
| 1562 | #if SIMULATION_RX_DVS |
| 1563 | if (p->frequency >=2133) |
| 1564 | DramcDramcRxDVSCalPostProcess(p); |
| 1565 | #endif |
| 1566 | |
| 1567 | DramcDualRankRxdatlatCal(p); |
| 1568 | |
| 1569 | #if RDSEL_TRACKING_EN |
| 1570 | if (p->frequency >= RDSEL_TRACKING_TH) |
| 1571 | RDSELRunTimeTracking_preset(p); |
| 1572 | #endif |
| 1573 | |
| 1574 | #if XRTWTW_NEW_CROSS_RK_MODE |
| 1575 | if(p->support_rank_num == RANK_DUAL) |
| 1576 | { |
| 1577 | XRTWTW_SHU_Setting(p); |
| 1578 | } |
| 1579 | #endif |
| 1580 | |
| 1581 | #if __Petrus_TO_BE_PORTING__ |
| 1582 | #if LJPLL_FREQ_DEBUG_LOG |
| 1583 | DDRPhyFreqMeter(p); |
| 1584 | #endif |
| 1585 | #endif |
| 1586 | |
| 1587 | #ifdef DDR_INIT_TIME_PROFILING |
| 1588 | CPU_Cycle=TimeProfileEnd(); |
| 1589 | mcSHOW_TIME_MSG(("\tMisc takes %d us\n\n", s1RankIdx, CPU_Cycle)); |
| 1590 | #endif |
| 1591 | } |
| 1592 | |
| 1593 | static void vDramCalibrationSingleChannel(DRAMC_CTX_T *p) |
| 1594 | { |
| 1595 | vCalibration_Flow_LP4(p); |
| 1596 | } |
| 1597 | |
| 1598 | void vDramCalibrationAllChannel(DRAMC_CTX_T *p) |
| 1599 | { |
| 1600 | U8 channel_idx, rank_idx; |
| 1601 | |
| 1602 | #ifdef FOR_HQA_REPORT_USED |
| 1603 | print_HQA_message_before_CalibrationAllChannel(p); |
| 1604 | #endif |
| 1605 | |
| 1606 | #ifdef DDR_INIT_TIME_PROFILING |
| 1607 | PROFILING_TIME_T ptime; |
| 1608 | |
| 1609 | TimeProfileGetTick(&ptime); |
| 1610 | #endif |
| 1611 | |
| 1612 | CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL); |
| 1613 | for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) |
| 1614 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1615 | vSetPHY2ChannelMapping(p, channel_idx); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1616 | CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL); |
| 1617 | vDramCalibrationSingleChannel(p); |
| 1618 | } |
| 1619 | |
| 1620 | vSetPHY2ChannelMapping(p, CHANNEL_A); |
| 1621 | |
| 1622 | #if PRINT_CALIBRATION_SUMMARY |
| 1623 | vPrintCalibrationResult(p); |
| 1624 | #endif |
| 1625 | |
| 1626 | #ifdef FOR_HQA_TEST_USED |
| 1627 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 1628 | if (p->femmc_Ready == 1) |
| 1629 | { |
| 1630 | mcSHOW_DBG_MSG(("\nCalibration fast K is enable, cannot show HQA measurement information\n")); |
| 1631 | } |
| 1632 | else |
| 1633 | #endif |
| 1634 | print_HQA_measure_message(p); |
| 1635 | #endif |
| 1636 | |
| 1637 | #if defined(DEVIATION) |
| 1638 | if(p->frequency == u2DFSGetHighestFreq(p)) |
| 1639 | { |
| 1640 | SetDeviationVref(p); |
| 1641 | #if !__ETT__ |
| 1642 | vSetDeviationVariable(); |
| 1643 | #endif |
| 1644 | } |
| 1645 | #endif |
| 1646 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1647 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1648 | #if ENABLE_READ_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1649 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1650 | vSetRank(p, RANK_0); |
| 1651 | vSetPHY2ChannelMapping(p, CHANNEL_A); |
| 1652 | |
| 1653 | DramcReadDBIOnOff(p, p->DBI_R_onoff[p->dram_fsp]); |
| 1654 | #endif |
| 1655 | |
| 1656 | #if ENABLE_WRITE_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1657 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1658 | if (p->DBI_W_onoff[p->dram_fsp]) |
| 1659 | { |
| 1660 | for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) |
| 1661 | { |
| 1662 | vSetPHY2ChannelMapping(p, channel_idx); |
| 1663 | |
| 1664 | for (rank_idx = RANK_0; rank_idx < RANK_MAX; rank_idx++) |
| 1665 | { |
| 1666 | vSetRank(p, rank_idx); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1667 | DramcWriteShiftMCKForWriteDBI(p, -1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1668 | } |
| 1669 | vSetRank(p, RANK_0); |
| 1670 | } |
| 1671 | vSetPHY2ChannelMapping(p, CHANNEL_A); |
| 1672 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1673 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1674 | ApplyWriteDBIPowerImprove(p, ENABLE); |
| 1675 | |
| 1676 | #if ENABLE_WRITE_DBI_Protect |
| 1677 | ApplyWriteDBIProtect(p, ENABLE); |
| 1678 | #endif |
| 1679 | } |
| 1680 | |
| 1681 | DramcWriteDBIOnOff(p, p->DBI_W_onoff[p->dram_fsp]); |
| 1682 | #endif |
| 1683 | |
| 1684 | #if TX_PICG_NEW_MODE |
| 1685 | TXPICGSetting(p); |
| 1686 | #endif |
| 1687 | |
| 1688 | #if XRTRTR_NEW_CROSS_RK_MODE |
| 1689 | if (p->support_rank_num == RANK_DUAL) |
| 1690 | { |
| 1691 | XRTRTR_SHU_Setting(p); |
| 1692 | } |
| 1693 | #endif |
| 1694 | |
| 1695 | #if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS) |
| 1696 | FreqJumpRatioCalculation(p); |
| 1697 | #endif |
| 1698 | |
| 1699 | #ifdef TEMP_SENSOR_ENABLE |
| 1700 | DramcHMR4_Presetting(p); |
| 1701 | #endif |
| 1702 | |
| 1703 | #if DRAMC_MODIFIED_REFRESH_MODE |
| 1704 | DramcModifiedRefreshMode(p); |
| 1705 | #endif |
| 1706 | |
| 1707 | #if DRAMC_CKE_DEBOUNCE |
| 1708 | DramcCKEDebounce(p); |
| 1709 | #endif |
| 1710 | |
| 1711 | #if ENABLE_TX_TRACKING |
| 1712 | U8 backup_channel = p->channel; |
| 1713 | U8 channelIdx; |
| 1714 | |
| 1715 | for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++) |
| 1716 | { |
| 1717 | vSetPHY2ChannelMapping(p, channelIdx); |
| 1718 | DramcHwDQSOSC(p); |
| 1719 | } |
| 1720 | |
| 1721 | vSetPHY2ChannelMapping(p, backup_channel); |
| 1722 | //mcSHOW_DBG_MSG(("TX_TRACKING: ON\n")); |
| 1723 | //#else |
| 1724 | //mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n")); |
| 1725 | #endif |
| 1726 | |
| 1727 | #if ENABLE_DFS_RUNTIME_MRW |
| 1728 | DFSRuntimeMRW_preset_AfterK(p, vGet_Current_SRAMIdx(p)); |
| 1729 | #endif |
| 1730 | |
| 1731 | #ifdef DDR_INIT_TIME_PROFILING |
| 1732 | mcSHOW_TIME_MSG((" (4) vDramCalibrationAllChannel() take %d ms\n\r", TimeProfileDiffUS(&ptime) / 1000)); |
| 1733 | #endif |
| 1734 | } |
| 1735 | |
| 1736 | U8 gGet_MDL_Used_Flag = 0; |
| 1737 | void Set_MDL_Used_Flag(U8 value) |
| 1738 | { |
| 1739 | gGet_MDL_Used_Flag = value; |
| 1740 | } |
| 1741 | |
| 1742 | U8 Get_MDL_Used_Flag(void) |
| 1743 | { |
| 1744 | return gGet_MDL_Used_Flag; |
| 1745 | } |
| 1746 | |
| 1747 | DRAMC_CTX_T *psCurrDramCtx; |
| 1748 | U8 gfirst_init_flag = 0; |
| 1749 | //extern int MustStop; |
| 1750 | int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used) |
| 1751 | { |
| 1752 | #if !SW_CHANGE_FOR_SIMULATION |
| 1753 | |
| 1754 | //int mem_start, len, s4value; |
| 1755 | DRAMC_CTX_T * p; |
| 1756 | //U8 ucstatus = 0; |
| 1757 | //U32 u4value; |
| 1758 | //U8 chIdx; |
| 1759 | U8 final_shu; |
| 1760 | |
| 1761 | #ifdef DDR_INIT_TIME_PROFILING |
| 1762 | U32 CPU_Cycle; |
| 1763 | TimeProfileBegin(); |
| 1764 | #endif |
| 1765 | |
| 1766 | psCurrDramCtx = &DramCtx_LPDDR4; |
| 1767 | |
| 1768 | #if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION) |
| 1769 | if (gtime_profiling_flag == 0) |
| 1770 | { |
| 1771 | memcpy(&gTimeProfilingDramCtx, psCurrDramCtx, sizeof(DRAMC_CTX_T)); |
| 1772 | gtime_profiling_flag = 1; |
| 1773 | } |
| 1774 | |
| 1775 | p = &gTimeProfilingDramCtx; |
| 1776 | gfirst_init_flag = 0; |
| 1777 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1778 | //DramcConfInfraReset(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1779 | #else |
| 1780 | p = psCurrDramCtx; |
| 1781 | #endif |
| 1782 | |
| 1783 | p->new_cbt_mode = 1; |
| 1784 | |
| 1785 | Set_MDL_Used_Flag(get_mdl_used); |
| 1786 | |
| 1787 | p->dram_type = dram_type; |
| 1788 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1789 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1790 | switch ((int)dram_cbt_mode_extern) |
| 1791 | { |
| 1792 | case CBT_R0_R1_NORMAL: |
| 1793 | p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; |
| 1794 | p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; |
| 1795 | break; |
| 1796 | case CBT_R0_R1_BYTE: |
| 1797 | p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1; |
| 1798 | p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1; |
| 1799 | break; |
| 1800 | case CBT_R0_NORMAL_R1_BYTE: |
| 1801 | p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; |
| 1802 | p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1; |
| 1803 | break; |
| 1804 | case CBT_R0_BYTE_R1_NORMAL: |
| 1805 | p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1; |
| 1806 | p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; |
| 1807 | break; |
| 1808 | default: |
| 1809 | mcSHOW_ERR_MSG(("Error!")); |
| 1810 | break; |
| 1811 | } |
| 1812 | mcSHOW_DBG_MSG2(("dram_cbt_mode_extern: %d\n" |
| 1813 | "dram_cbt_mode [RK0]: %d, [RK1]: %d\n", |
| 1814 | (int)dram_cbt_mode_extern, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1])); |
| 1815 | |
| 1816 | #if ENABLE_APB_MASK_WRITE |
| 1817 | U32 u4GPTTickCnt; |
| 1818 | TimeProfileBegin(); |
| 1819 | |
| 1820 | EnableDramcAPBMaskWrite(p); |
| 1821 | DramcRegAPBWriteMask(p); |
| 1822 | |
| 1823 | u4GPTTickCnt = TimeProfileEnd(); |
| 1824 | mcSHOW_TIME_MSG(("[DramcRegAPBWriteMask] take %d ms\n", u4GPTTickCnt / 1000)); |
| 1825 | |
| 1826 | TestAPBMaskWriteFunc(p); |
| 1827 | |
| 1828 | while (1); |
| 1829 | #endif |
| 1830 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1831 | DramcBroadcastOnOff(DRAMC_BROADCAST_ON); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1832 | |
| 1833 | if (gfirst_init_flag == 0) |
| 1834 | { |
| 1835 | MPLLInit(); |
| 1836 | Global_Option_Init(p); |
| 1837 | gfirst_init_flag = 1; |
| 1838 | } |
| 1839 | |
| 1840 | #ifdef FIRST_BRING_UP |
| 1841 | if (p->support_channel_num != CHANNEL_SINGLE) |
| 1842 | Test_Broadcast_Feature(p); |
| 1843 | #endif |
| 1844 | |
| 1845 | #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) |
| 1846 | { |
| 1847 | U32 backup_broadcast; |
| 1848 | backup_broadcast = GetDramcBroadcast(); |
| 1849 | DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); |
| 1850 | mdl_setting(p); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1851 | UpdateGlobal10GBEnVariables(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1852 | TA2_Test_Run_Time_HW_Set_Column_Num(p); |
| 1853 | DramcBroadcastOnOff(backup_broadcast); |
| 1854 | } |
| 1855 | #endif |
| 1856 | |
| 1857 | mcSHOW_DBG_MSG(("\n\n[Bian_co] %s\n dram_type %d, R0 cbt_mode %d, R1 cbt_mode %d VENDOR=%d\n\n", _VERSION_, p->dram_type, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1], p->vendor_id)); |
| 1858 | |
| 1859 | #if __Petrus_TO_BE_PORTING__ |
| 1860 | vDramcInit_PreSettings(p); |
| 1861 | #endif |
| 1862 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1863 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1864 | |
| 1865 | #if defined(DUMP_INIT_RG_LOG_TO_DE) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1866 | vSetDFSFreqSelByTable(p, &gFreqTbl[1]); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1867 | #else |
| 1868 | vSetDFSFreqSelByTable(p, &gFreqTbl[DRAM_DFS_SRAM_MAX-1]); |
| 1869 | //vSetDFSFreqSelByTable(p, &gFreqTbl[1]); |
| 1870 | #endif |
| 1871 | |
| 1872 | #if (DUAL_FREQ_K==0) || (__FLASH_TOOL_DA__) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1873 | gAndroid_DVFS_en = FALSE; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1874 | #endif |
| 1875 | |
| 1876 | #if RUNTIME_SHMOO_RELEATED_FUNCTION |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1877 | ett_fix_freq = 1; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1878 | #endif |
| 1879 | |
Ryan Chuang | 4572727 | 2021-08-10 10:08:49 +0800 | [diff] [blame] | 1880 | if (!CONFIG(MEDIATEK_DRAM_DVFS)) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1881 | ett_fix_freq = 0x1; |
Ryan Chuang | eb94a4a | 2021-08-06 11:00:25 +0800 | [diff] [blame] | 1882 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1883 | if (ett_fix_freq != 0xff) |
| 1884 | gAndroid_DVFS_en = FALSE; |
| 1885 | |
| 1886 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 1887 | DramcSave_Time_For_Cal_Init(p); |
| 1888 | #endif |
| 1889 | #ifndef LOOPBACK_TEST |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1890 | if (p->dram_type == TYPE_LPDDR4X) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1891 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1892 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1893 | DramcImpedanceCal(p, 1, IMP_LOW_FREQ); |
| 1894 | DramcImpedanceCal(p, 1, IMP_HIGH_FREQ); |
| 1895 | #if ENABLE_SAMSUNG_NT_ODT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1896 | DramcImpedanceCal(p, 1, IMP_NT_ODTN); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1897 | #endif |
| 1898 | } |
| 1899 | else |
| 1900 | { |
| 1901 | mcSHOW_ERR_MSG(("[DramcImpedanceCal] Warnning: Need confirm DRAM type for SW IMP Calibration !!!\n")); |
| 1902 | #if __ETT__ |
| 1903 | while (1); |
| 1904 | #endif |
| 1905 | } |
| 1906 | #endif |
| 1907 | |
| 1908 | #ifdef DDR_INIT_TIME_PROFILING |
| 1909 | CPU_Cycle = TimeProfileEnd(); |
| 1910 | mcSHOW_TIME_MSG(("(0)Pre_Init + SwImdepance takes %d ms\n\r", CPU_Cycle / 1000)); |
| 1911 | #endif |
| 1912 | |
| 1913 | #ifdef DUMP_INIT_RG_LOG_TO_DE |
| 1914 | gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1; |
| 1915 | mcSHOW_DUMP_INIT_RG_MSG(("\n\n//=== DDR\033[1;32m%d\033[m\n",p->frequency<<1)); |
| 1916 | #endif |
| 1917 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1918 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1919 | //EnableDramcPhyDCM(p, 0); |
| 1920 | |
| 1921 | DFSInitForCalibration(p); |
| 1922 | |
| 1923 | #ifdef TEST_MODE_MRS |
| 1924 | if (global_which_test == 0) |
| 1925 | TestModeTestMenu(); |
| 1926 | #endif |
| 1927 | |
| 1928 | |
| 1929 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 1930 | if (p->femmc_Ready==1) |
| 1931 | { |
| 1932 | p->support_rank_num = p->pSavetimeData->support_rank_num; |
| 1933 | } |
| 1934 | else |
| 1935 | #endif |
| 1936 | { |
| 1937 | #if ENABLE_RANK_NUMBER_AUTO_DETECTION |
| 1938 | if (Get_MDL_Used_Flag()==GET_MDL_USED) |
| 1939 | { |
| 1940 | DramRankNumberDetection(p); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1941 | DFSInitForCalibration(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1942 | } |
| 1943 | #endif |
| 1944 | |
| 1945 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 1946 | p->pSavetimeData->support_rank_num = p->support_rank_num; |
| 1947 | #endif |
| 1948 | } |
| 1949 | |
Ryan Chuang | 9f10950 | 2021-11-25 16:15:27 +0800 | [diff] [blame] | 1950 | if (p->support_rank_num == RANK_SINGLE){ |
| 1951 | CKEFixOnOff(p, RANK_1, CKE_DYNAMIC, TO_ALL_CHANNEL); |
| 1952 | mcSHOW_DBG_MSG(("Set RANK1 CKE to DYNAMIC\n")); |
| 1953 | } |
| 1954 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1955 | #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) |
| 1956 | U32 backup_broadcast; |
| 1957 | backup_broadcast = GetDramcBroadcast(); |
| 1958 | DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); |
| 1959 | emi_init2(); |
| 1960 | DramcBroadcastOnOff(backup_broadcast); |
| 1961 | #endif |
| 1962 | |
| 1963 | if (Get_MDL_Used_Flag()==GET_MDL_USED) |
| 1964 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1965 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1966 | vSetPHY2ChannelMapping(p, CHANNEL_A); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1967 | vCalibration_Flow_For_MDL(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1968 | GetDramInforAfterCalByMRR(p, DramInfo); |
| 1969 | return 0; |
| 1970 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1971 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1972 | { |
| 1973 | vDramCalibrationAllChannel(p); |
| 1974 | GetDramInforAfterCalByMRR(p, DramInfo); |
| 1975 | vDramcACTimingOptimize(p); |
| 1976 | } |
| 1977 | |
| 1978 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 1979 | DramcSave_Time_For_Cal_End(p); |
| 1980 | #endif |
| 1981 | |
| 1982 | |
| 1983 | #if (DUAL_FREQ_K) && (!__FLASH_TOOL_DA__) |
| 1984 | DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, vGet_Current_SRAMIdx(p)); |
| 1985 | |
| 1986 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 1987 | DramcSave_Time_For_Cal_End(p); |
| 1988 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1989 | LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1990 | |
| 1991 | S8 u1ShuIdx; |
| 1992 | S8 s1ShuStart, s1ShuEnd; |
| 1993 | |
| 1994 | if (ett_fix_freq != 0xff) { |
| 1995 | s1ShuStart = ett_fix_freq; |
| 1996 | s1ShuEnd = ett_fix_freq; |
| 1997 | gFreqTbl[ett_fix_freq].vref_calibartion_enable = VREF_CALI_ON; |
| 1998 | } else { |
| 1999 | s1ShuStart = DRAM_DFS_SRAM_MAX - 2; |
| 2000 | s1ShuEnd = SRAM_SHU0; |
| 2001 | } |
| 2002 | |
| 2003 | for (u1ShuIdx = s1ShuStart; u1ShuIdx >= s1ShuEnd; u1ShuIdx--) |
| 2004 | { |
| 2005 | vSetDFSFreqSelByTable(p, &gFreqTbl[u1ShuIdx]); |
| 2006 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 2007 | DramcSave_Time_For_Cal_Init(p); |
| 2008 | #endif |
| 2009 | DFSInitForCalibration(p); |
| 2010 | vDramCalibrationAllChannel(p); |
| 2011 | vDramcACTimingOptimize(p); |
| 2012 | |
| 2013 | #if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 2014 | if (p->frequency == u2DFSGetHighestFreq(p)) |
| 2015 | { |
| 2016 | DramcRunTimeShmooRG_BackupRestore(p); |
| 2017 | RunTime_Shmoo_update_parameters(p); |
| 2018 | } |
| 2019 | #endif |
| 2020 | |
| 2021 | DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, gFreqTbl[u1ShuIdx].SRAMIdx); |
| 2022 | |
| 2023 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 2024 | DramcSave_Time_For_Cal_End(p); |
| 2025 | #endif |
| 2026 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2027 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2028 | |
| 2029 | |
| 2030 | #ifdef DDR_INIT_TIME_PROFILING |
| 2031 | TimeProfileBegin(); |
| 2032 | #endif |
| 2033 | |
| 2034 | vAfterCalibration(p); |
| 2035 | |
| 2036 | #ifdef ENABLE_POST_PACKAGE_REPAIR |
| 2037 | PostPackageRepair(); |
| 2038 | #endif |
| 2039 | |
| 2040 | #if __Petrus_TO_BE_PORTING__ |
| 2041 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2042 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2043 | U8 u1ChannelIdx, u1RankIdx; |
| 2044 | for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++) |
| 2045 | for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++) |
| 2046 | { |
| 2047 | vSetPHY2ChannelMapping(p, u1ChannelIdx); |
| 2048 | vSetRank(p, u1RankIdx); |
| 2049 | DramcTxOECalibration(p); |
| 2050 | } |
| 2051 | |
| 2052 | vSetPHY2ChannelMapping(p, CHANNEL_A); |
| 2053 | vSetRank(p, RANK_0); |
| 2054 | |
| 2055 | U32 u4err_value; |
| 2056 | DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_PREPARE_DATA_ONLY, p->support_channel_num); |
| 2057 | u4err_value = DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_CHECK_DATA_ACCESS_AND_COMPARE, p->support_channel_num); |
| 2058 | mcSHOW_DBG_MSG(("DramC_TX_OE_Calibration 0x%X\n", u4err_value)); |
| 2059 | #endif |
| 2060 | |
| 2061 | #if !LCPLL_IC_SCAN |
| 2062 | #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) |
| 2063 | print_DBG_info(p); |
| 2064 | Dump_EMIRegisters(p); |
| 2065 | #endif |
| 2066 | #endif |
| 2067 | |
| 2068 | #if 0 |
| 2069 | DramcRegDump(p, SRAM_SHU0); |
| 2070 | #endif |
| 2071 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2072 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2073 | |
| 2074 | #if ETT_NO_DRAM |
| 2075 | //NoDramDramcRegDump(p); |
| 2076 | NoDramRegFill(); |
| 2077 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2078 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2079 | |
| 2080 | #if DRAMC_MODEREG_CHECK |
| 2081 | DramcModeReg_Check(p); |
| 2082 | #endif |
| 2083 | |
| 2084 | #if PIN_CHECK_TOOL |
| 2085 | vPrintPinInfoResult(p); |
| 2086 | vGetErrorTypeResult(p); |
| 2087 | #endif |
| 2088 | |
| 2089 | #if CPU_RW_TEST_AFTER_K |
| 2090 | mcSHOW_DBG_MSG2(("\n[MEM_TEST] 02: After DFS, before run time config\n")); |
| 2091 | vDramCPUReadWriteTestAfterCalibration(p); |
| 2092 | #endif |
| 2093 | |
| 2094 | #if TA2_RW_TEST_AFTER_K |
| 2095 | mcSHOW_DBG_MSG2(("\n[TA2_TEST]\n")); |
| 2096 | TA2_Test_Run_Time_HW(p); |
| 2097 | #endif |
| 2098 | |
| 2099 | #if __ETT__ |
| 2100 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 2101 | if (!(p->femmc_Ready == 0)) |
| 2102 | #elif defined(DDR_INIT_TIME_PROFILING) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2103 | if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2104 | #endif |
| 2105 | #endif |
| 2106 | { |
| 2107 | EnableDFSHwModeClk(p); |
| 2108 | mcSHOW_DBG_MSG2(("DFS_SHUFFLE_HW_MODE: ON\n")); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2109 | if (gAndroid_DVFS_en == TRUE) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2110 | { |
| 2111 | #if defined(SLT) |
| 2112 | #ifdef SLT_2400_EXIT_PRELOADER |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2113 | final_shu = SRAM_SHU0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2114 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2115 | final_shu = SRAM_SHU0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2116 | #endif |
| 2117 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2118 | final_shu = SRAM_SHU0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2119 | #endif |
| 2120 | |
| 2121 | vSetDFSFreqSelByTable(p, get_FreqTbl_by_SRAMIndex(p, final_shu)); |
| 2122 | #if REPLACE_DFS_RG_MODE |
| 2123 | DramcDFSDirectJump_SPMMode(p, SRAM_SHU1); |
| 2124 | DramcDFSDirectJump_SPMMode(p, final_shu); |
| 2125 | #else |
| 2126 | DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU1); |
| 2127 | DramcDFSDirectJump_SRAMShuRGMode(p, final_shu); |
| 2128 | #endif |
| 2129 | } |
| 2130 | |
| 2131 | |
| 2132 | #if __Petrus_TO_BE_PORTING__ |
| 2133 | #if (DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM && defined(DUMMY_READ_FOR_TRACKING)) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2134 | DramcDummyReadForSPMSideBand(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2135 | #endif |
| 2136 | |
| 2137 | EnableDramcTrackingBySPMControl(p); |
| 2138 | |
| 2139 | mcSHOW_DBG_MSG2(("\n\nSettings after calibration\n\n")); |
| 2140 | //mcDUMP_REG_MSG(("\n\nSettings after calibration\n\n")); |
| 2141 | #endif |
| 2142 | |
| 2143 | |
| 2144 | DramcRunTimeConfig(p); |
| 2145 | |
| 2146 | #if DUMP_ALLSUH_RG |
| 2147 | DumpAllChAllShuRG(p); |
| 2148 | #endif |
| 2149 | } |
| 2150 | |
| 2151 | #if CPU_RW_TEST_AFTER_K |
| 2152 | mcSHOW_DBG_MSG2(("\n[MEM_TEST] 03: After run time config\n")); |
| 2153 | vDramCPUReadWriteTestAfterCalibration(p); |
| 2154 | #endif |
| 2155 | |
| 2156 | #if TA2_RW_TEST_AFTER_K |
| 2157 | mcSHOW_DBG_MSG2(("\n[TA2_TEST]\n")); |
| 2158 | TA2_Test_Run_Time_HW(p); |
| 2159 | #endif |
| 2160 | |
| 2161 | |
| 2162 | #if (__ETT__ && CPU_RW_TEST_AFTER_K) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2163 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2164 | //while(1) |
| 2165 | { |
| 2166 | //if ((s4value = dramc_complex_mem_test (0x46000000, 0x2000)) == 0) |
| 2167 | if ((s4value = dramc_complex_mem_test (0x40024000, 0x20000)) == 0) |
| 2168 | { |
| 2169 | mcSHOW_DBG_MSG3(("1st complex R/W mem test pass\n")); |
| 2170 | } |
| 2171 | else |
| 2172 | { |
| 2173 | mcSHOW_DBG_MSG3(("1st complex R/W mem test fail :-%d\n", -s4value)); |
| 2174 | #if defined(SLT) |
| 2175 | mcSHOW_ERR_MSG(("[EMI] EMI_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__)); |
| 2176 | while (1); |
| 2177 | #endif |
| 2178 | } |
| 2179 | } |
| 2180 | #endif |
| 2181 | |
| 2182 | #if MRW_CHECK_ONLY |
| 2183 | vPrintFinalModeRegisterSetting(p); |
| 2184 | #endif |
| 2185 | |
| 2186 | #ifdef DDR_INIT_TIME_PROFILING |
| 2187 | CPU_Cycle = TimeProfileEnd(); |
| 2188 | mcSHOW_TIME_MSG((" (5) After calibration takes %d ms\n\r", CPU_Cycle / 1000)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2189 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2190 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2191 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2192 | |
| 2193 | #if defined(FOR_HQA_REPORT_USED) |
| 2194 | print_HQA_SLT_BIN_message(p); |
| 2195 | #endif |
| 2196 | |
| 2197 | #if DVT_TEST_RX_FIFO_MISMATCH_IRQ_CLEAN |
| 2198 | DVTRxFifoMismatchIrqClean(p); |
| 2199 | #endif |
| 2200 | |
| 2201 | //final_shu = SRAM_SHU7; |
| 2202 | //vSetDFSFreqSelByTable(p, get_FreqTbl_by_SRAMIndex(p, final_shu)); |
| 2203 | //DramcDFSDirectJump(p, SRAM_SHU1);//Switch to CLRPLL |
| 2204 | //DramcDFSDirectJump(p, final_shu);//Switch to CLRPLL |
| 2205 | //if(MustStop) |
| 2206 | // while(1); |
| 2207 | //ETT_DRM(p); |
| 2208 | |
| 2209 | return 0; |
| 2210 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2211 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2212 | |
| 2213 | |
| 2214 | #if FOR_DV_SIMULATION_USED |
| 2215 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2216 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2217 | void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t *psra) |
| 2218 | { |
| 2219 | U8 ii; |
| 2220 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2221 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2222 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 2223 | DramcRxdqsGatingPreProcess(DramConfig); |
| 2224 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2225 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2226 | |
| 2227 | vAutoRefreshSwitch(DramConfig, DISABLE); |
| 2228 | |
| 2229 | #if (SIMUILATION_CBT == 1) |
| 2230 | for (ii = RANK_0; ii < DramConfig->support_rank_num; ii++) |
| 2231 | { |
| 2232 | vSetRank(DramConfig, ii); |
| 2233 | |
| 2234 | if (!psra || psra->cbt) { |
| 2235 | mcSHOW_DBG_MSG6(("\n----->DramcCBT begin...\n")); |
| 2236 | timestamp_show(); |
| 2237 | #if CBT_O1_PINMUX_WORKAROUND |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2238 | CmdBusTrainingLP45(DramConfig, AUTOK_OFF); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2239 | #else |
| 2240 | if (psra) |
| 2241 | CmdBusTrainingLP45(DramConfig, psra->cbt_autok, NORMAL_K); |
| 2242 | else |
| 2243 | CmdBusTrainingLP45(DramConfig, AUTOK_OFF, NORMAL_K); |
| 2244 | #endif |
| 2245 | timestamp_show(); |
| 2246 | mcSHOW_DBG_MSG6(("DramcCBT end<-----\n\n")); |
| 2247 | } |
| 2248 | #if ENABLE_EYESCAN_GRAPH |
| 2249 | if (GetEyeScanEnable(DramConfig, EYESCAN_TYPE_CBT) == ENABLE) |
| 2250 | { |
| 2251 | mcSHOW_DBG_MSG6(("CBT EYESCAN start<-----\n\n")); |
| 2252 | CmdBusTrainingLP45(DramConfig, AUTOK_OFF, EYESCAN_K); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2253 | print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_CBT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2254 | mcSHOW_DBG_MSG6(("CBT EYESCAN end<-----\n\n")); |
| 2255 | } |
| 2256 | #endif |
| 2257 | } |
| 2258 | |
| 2259 | vSetRank(DramConfig, RANK_0); |
| 2260 | |
| 2261 | ShuffleDfsToOriginalFSP(DramConfig); |
| 2262 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2263 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2264 | #if __A60868_TO_BE_PORTING__ |
| 2265 | No_Parking_On_CLRPLL(DramConfig); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2266 | #endif |
| 2267 | |
| 2268 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2269 | |
| 2270 | for (ii = RANK_0; ii < DramConfig->support_rank_num; ii++) |
| 2271 | { |
| 2272 | vSetRank(DramConfig, ii); |
| 2273 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2274 | vAutoRefreshSwitch(DramConfig, DISABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2275 | |
| 2276 | #if (SIMULATION_WRITE_LEVELING == 1) |
| 2277 | #if (!WCK_LEVELING_FM_WORKAROUND) |
| 2278 | if (u1IsLP4Family(DramConfig->dram_type)) |
| 2279 | #endif |
| 2280 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2281 | if (!(u1IsPhaseMode(DramConfig) && (DramConfig->rank == RANK_1))) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2282 | { |
| 2283 | if (!psra || psra->wl) { |
| 2284 | mcSHOW_DBG_MSG6(("\n----->DramcWriteLeveling(PI) begin...\n")); |
| 2285 | timestamp_show(); |
| 2286 | if (psra) |
| 2287 | { |
| 2288 | DramcWriteLeveling(DramConfig, psra->wl_autok, PI_BASED); |
| 2289 | } |
| 2290 | else |
| 2291 | DramcWriteLeveling(DramConfig, AUTOK_OFF, PI_BASED); |
| 2292 | |
| 2293 | timestamp_show(); |
| 2294 | mcSHOW_DBG_MSG6(("DramcWriteLeveling(PI) end<-----\n\n")); |
| 2295 | } |
| 2296 | } |
| 2297 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2298 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2299 | |
| 2300 | vAutoRefreshSwitch(DramConfig, ENABLE); |
| 2301 | |
| 2302 | #if (SIMULATION_GATING == 1) |
| 2303 | if (!psra || psra->gating) { |
| 2304 | mcSHOW_DBG_MSG6(("\n----->DramcGating begin...\n")); |
| 2305 | timestamp_show(); |
| 2306 | if (psra) |
| 2307 | dramc_rx_dqs_gating_cal(DramConfig, psra->gating_autok, 0); |
| 2308 | else |
| 2309 | dramc_rx_dqs_gating_cal(DramConfig, AUTOK_OFF, 0); |
| 2310 | timestamp_show(); |
| 2311 | mcSHOW_DBG_MSG6(("DramcGating end < -----\n\n")); |
| 2312 | } |
| 2313 | #endif |
| 2314 | |
| 2315 | #if (SIMULATION_RX_RDDQC == 1) |
| 2316 | if (!psra || psra->rddqc) { |
| 2317 | mcSHOW_DBG_MSG6(("\n----->DramcRxWindowPerbitCal RDDQC begin...\n")); |
| 2318 | timestamp_show(); |
| 2319 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2320 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2321 | p->rank = 1; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2322 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2323 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL), 0, SHU_WCKCTRL_WCKDUAL); |
| 2324 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), |
| 2325 | P_Fld(1, SHU_COMMON0_LP5WCKON) | |
| 2326 | P_Fld(1, SHU_COMMON0_LP5HEFF_MODE)); |
| 2327 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 0, CKECTRL_CKE2RANK_OPT8); |
| 2328 | #endif |
| 2329 | DramcRxWindowPerbitCal(DramConfig, PATTERN_RDDQC, NULL, AUTOK_OFF, NORMAL_K); |
| 2330 | timestamp_show(); |
| 2331 | mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal end<-----\n\n")); |
| 2332 | } |
| 2333 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2334 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2335 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2336 | #if (SIMULATION_TX_PERBIT == 1) |
| 2337 | if (!psra || psra->tx_perbit) { |
| 2338 | mcSHOW_DBG_MSG6(("\n----->DramcTxWindowPerbitCal begin...\n")); |
| 2339 | timestamp_show(); |
| 2340 | if (psra) |
| 2341 | DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM, |
| 2342 | FALSE, psra->tx_auto_cal); |
| 2343 | else |
| 2344 | DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM, |
| 2345 | FALSE, AUTOK_OFF); |
| 2346 | if (Get_Vref_Calibration_OnOff(DramConfig) == VREF_CALI_ON) { |
| 2347 | if (psra) |
| 2348 | DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY, |
| 2349 | TRUE, psra->tx_auto_cal); |
| 2350 | else |
| 2351 | DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY, |
| 2352 | TRUE, AUTOK_OFF); |
| 2353 | } |
| 2354 | if (psra) |
| 2355 | DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY, |
| 2356 | FALSE, psra->tx_auto_cal); |
| 2357 | else |
| 2358 | DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY, |
| 2359 | FALSE, AUTOK_OFF); |
| 2360 | timestamp_show(); |
| 2361 | mcSHOW_DBG_MSG6(("DramcTxWindowPerbitCal end<-----\n\n")); |
| 2362 | |
| 2363 | #if ENABLE_EYESCAN_GRAPH |
| 2364 | if (GetEyeScanEnable(DramConfig, EYESCAN_TYPE_TX) == ENABLE) |
| 2365 | { |
| 2366 | mcSHOW_DBG_MSG6(("\n----->DramcTxEYESCAN begin...\n")); |
| 2367 | Dramc_K_TX_EyeScan_Log(DramConfig); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2368 | print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_TX); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2369 | mcSHOW_DBG_MSG6(("\n----->DramcTxEYESCAN end...\n")); |
| 2370 | } |
| 2371 | #endif |
| 2372 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2373 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2374 | |
| 2375 | #if (SIMULATION_DATLAT == 1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2376 | if (1) { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2377 | mcSHOW_DBG_MSG6(("\n----->DramcRxdatlatCal begin...\n")); |
| 2378 | timestamp_show(); |
| 2379 | |
| 2380 | DramcRxdatlatCal(DramConfig); |
| 2381 | |
| 2382 | timestamp_show(); |
| 2383 | mcSHOW_DBG_MSG6(("DramcRxdatlatCal end<-----\n\n")); |
| 2384 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2385 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2386 | |
| 2387 | #if (SIMULATION_RX_PERBIT == 1) |
| 2388 | if (!psra || psra->rx_perbit) { |
| 2389 | mcSHOW_DBG_MSG6(("\n----->DramcRxWindowPerbitCal begin...\n")); |
| 2390 | timestamp_show(); |
| 2391 | if (psra) |
| 2392 | DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2393 | NULL , psra->rx_auto_cal, NORMAL_K); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2394 | else |
| 2395 | DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2396 | NULL , AUTOK_OFF, NORMAL_K); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2397 | timestamp_show(); |
| 2398 | mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal end<-----\n\n")); |
| 2399 | |
| 2400 | #if ENABLE_EYESCAN_GRAPH |
| 2401 | if (GetEyeScanEnable(DramConfig, EYESCAN_TYPE_RX) == ENABLE) |
| 2402 | { |
| 2403 | mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal EYESCAN start<-----\n\n")); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2404 | DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, EYESCAN_K); |
| 2405 | print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_RX); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2406 | mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal EYESCAN end<-----\n\n")); |
| 2407 | } |
| 2408 | #endif |
| 2409 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2410 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2411 | |
| 2412 | #if (SIMULATION_RX_DVS == 1) |
| 2413 | if (DramConfig->frequency >=2133) |
| 2414 | DramcRxDVSWindowCal(DramConfig); |
| 2415 | #endif |
| 2416 | |
| 2417 | #if TX_OE_CALIBATION |
| 2418 | if (DramConfig->frequency >= 1600) |
| 2419 | { |
| 2420 | DramcTxOECalibration(DramConfig); |
| 2421 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2422 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2423 | |
| 2424 | #if ENABLE_TX_TRACKING |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2425 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2426 | if (gu1MR23Done == FALSE) |
| 2427 | { |
| 2428 | DramcDQSOSCAuto(p); |
| 2429 | } |
| 2430 | #endif |
| 2431 | DramcDQSOSCAuto(DramConfig); |
| 2432 | DramcDQSOSCMR23(DramConfig); |
| 2433 | DramcDQSOSCSetMR18MR19(DramConfig); |
| 2434 | #endif |
| 2435 | } |
| 2436 | |
| 2437 | vSetRank(DramConfig, RANK_0); |
| 2438 | |
| 2439 | #if ENABLE_TX_TRACKING |
| 2440 | DramcDQSOSCShuSettings(DramConfig); |
| 2441 | #endif |
| 2442 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2443 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2444 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 2445 | DramcRxdqsGatingPostProcess(DramConfig); |
| 2446 | #endif |
| 2447 | |
| 2448 | #if TDQSCK_PRECALCULATION_FOR_DVFS |
| 2449 | DramcDQSPrecalculation_preset(DramConfig); |
| 2450 | #endif |
| 2451 | |
| 2452 | #if SIMULATION_RX_DVS |
| 2453 | if (DramConfig->frequency >=2133) |
| 2454 | DramcDramcRxDVSCalPostProcess(DramConfig); |
| 2455 | #endif |
| 2456 | |
| 2457 | #if XRTWTW_NEW_CROSS_RK_MODE |
| 2458 | if (DramConfig->support_rank_num == RANK_DUAL) |
| 2459 | { |
| 2460 | XRTWTW_SHU_Setting(DramConfig); |
| 2461 | } |
| 2462 | #endif |
| 2463 | |
| 2464 | #if DV_SIMULATION_DATLAT |
| 2465 | DramcDualRankRxdatlatCal(DramConfig); |
| 2466 | #endif |
| 2467 | |
| 2468 | #if RDSEL_TRACKING_EN |
| 2469 | if (DramConfig->frequency != 400) |
| 2470 | RDSELRunTimeTracking_preset(DramConfig); |
| 2471 | #endif |
| 2472 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2473 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2474 | |
| 2475 | } |
| 2476 | |
| 2477 | void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t *psra) |
| 2478 | { |
| 2479 | U8 channel_idx, rank_idx; |
| 2480 | |
| 2481 | CKEFixOnOff(DramConfig, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL); |
| 2482 | for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++) |
| 2483 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2484 | vSetPHY2ChannelMapping(DramConfig, channel_idx); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2485 | CKEFixOnOff(DramConfig, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL); |
| 2486 | DPI_vDramCalibrationSingleChannel(DramConfig, psra); |
| 2487 | } |
| 2488 | |
| 2489 | vSetPHY2ChannelMapping(DramConfig, CHANNEL_A); |
| 2490 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2491 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2492 | #if ENABLE_READ_DBI |
| 2493 | DramcReadDBIOnOff(DramConfig, DramConfig->DBI_R_onoff[DramConfig->dram_fsp]); |
| 2494 | #endif |
| 2495 | |
| 2496 | #if ENABLE_WRITE_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2497 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2498 | if (DramConfig->DBI_W_onoff[DramConfig->dram_fsp]) |
| 2499 | { |
| 2500 | for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++) |
| 2501 | { |
| 2502 | vSetPHY2ChannelMapping(DramConfig, channel_idx); |
| 2503 | |
| 2504 | for (rank_idx = RANK_0; rank_idx < DramConfig->support_rank_num; rank_idx++) |
| 2505 | { |
| 2506 | vSetRank(DramConfig, rank_idx); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2507 | DramcWriteShiftMCKForWriteDBI(DramConfig, -1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2508 | } |
| 2509 | vSetRank(DramConfig, RANK_0); |
| 2510 | } |
| 2511 | vSetPHY2ChannelMapping(DramConfig, CHANNEL_A); |
| 2512 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2513 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2514 | ApplyWriteDBIPowerImprove(DramConfig, ENABLE); |
| 2515 | |
| 2516 | #if ENABLE_WRITE_DBI_Protect |
| 2517 | ApplyWriteDBIProtect(DramConfig, ENABLE); |
| 2518 | #endif |
| 2519 | } |
| 2520 | DramcWriteDBIOnOff(DramConfig, DramConfig->DBI_W_onoff[DramConfig->dram_fsp]); |
| 2521 | |
| 2522 | |
| 2523 | #endif |
| 2524 | |
| 2525 | #if XRTRTR_NEW_CROSS_RK_MODE |
| 2526 | if (DramConfig->support_rank_num == RANK_DUAL) |
| 2527 | { |
| 2528 | XRTRTR_SHU_Setting(DramConfig); |
| 2529 | } |
| 2530 | #endif |
| 2531 | |
| 2532 | #if DV_SIMULATION_DFS |
| 2533 | #if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS) |
| 2534 | FreqJumpRatioCalculation(DramConfig); |
| 2535 | #endif |
| 2536 | #endif |
| 2537 | |
| 2538 | #ifdef TEMP_SENSOR_ENABLE |
| 2539 | DramcHMR4_Presetting(DramConfig); |
| 2540 | #endif |
| 2541 | |
| 2542 | #if ENABLE_TX_TRACKING |
| 2543 | U8 backup_channel = DramConfig->channel; |
| 2544 | U8 channelIdx; |
| 2545 | |
| 2546 | for (channelIdx = CHANNEL_A; channelIdx < DramConfig->support_channel_num; channelIdx++) |
| 2547 | { |
| 2548 | vSetPHY2ChannelMapping(DramConfig, channelIdx); |
| 2549 | DramcHwDQSOSC(DramConfig); |
| 2550 | } |
| 2551 | |
| 2552 | vSetPHY2ChannelMapping(DramConfig, backup_channel); |
| 2553 | mcSHOW_DBG_MSG6(("TX_TRACKING: ON\n")); |
| 2554 | #else |
| 2555 | mcSHOW_DBG_MSG6(("TX_TRACKING: OFF\n")); |
| 2556 | #endif |
| 2557 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2558 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2559 | |
| 2560 | } |
| 2561 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2562 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2563 | #if __A60868_TO_BE_PORTING__ |
| 2564 | void RG_dummy_write(DRAMC_CTX_T *p, U32 pattern) |
| 2565 | { |
| 2566 | unsigned int ii; |
| 2567 | for (ii = 0; ii < 20; ii++) |
| 2568 | vIO32WriteFldAlign(DDRPHY_RFU_0X1D4, pattern, RFU_0X1D4_RESERVED_0X1D4); |
| 2569 | } |
| 2570 | |
| 2571 | void EnablePLLtoSPMControl(DRAMC_CTX_T *p) |
| 2572 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2573 | vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2574 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2575 | #endif |
| 2576 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2577 | |
| 2578 | void dump_dramc_ctx(DRAMC_CTX_T *p) |
| 2579 | { |
| 2580 | mcSHOW_DBG_MSG6(("== DRAMC_CTX_T ==\n")); |
| 2581 | mcSHOW_DBG_MSG6(("support_channel_num: %d\n", p->support_channel_num)); |
| 2582 | mcSHOW_DBG_MSG6(("channel: %d\n", p->channel)); |
| 2583 | mcSHOW_DBG_MSG6(("support_rank_num: %d\n", p->support_rank_num)); |
| 2584 | mcSHOW_DBG_MSG6(("rank: %d\n", p->rank)); |
| 2585 | mcSHOW_DBG_MSG6(("freq_sel: %d\n", p->freq_sel)); |
| 2586 | mcSHOW_DBG_MSG6(("SRAMIdx: %d\n", vGet_Current_SRAMIdx(p))); |
| 2587 | mcSHOW_DBG_MSG6(("dram_type: %d\n", p->dram_type)); |
| 2588 | mcSHOW_DBG_MSG6(("dram_fsp: %d\n", p->dram_fsp)); |
| 2589 | mcSHOW_DBG_MSG6(("odt_onoff: %d\n", p->odt_onoff)); |
| 2590 | mcSHOW_DBG_MSG6(("dram_cbt_mode: %d, %d\n", (int)p->dram_cbt_mode[0], (int)p->dram_cbt_mode[1])); |
| 2591 | mcSHOW_DBG_MSG6(("DBI_R_onoff: %d, %d\n", (int)p->DBI_R_onoff[0], (int)p->DBI_R_onoff[1])); |
| 2592 | mcSHOW_DBG_MSG6(("DBI_W_onoff: %d, %d\n", (int)p->DBI_W_onoff[0], (int)p->DBI_W_onoff[1])); |
| 2593 | mcSHOW_DBG_MSG6(("data_width: %d\n", p->data_width)); |
| 2594 | mcSHOW_DBG_MSG6(("test2_1: 0x%x\n", p->test2_1)); |
| 2595 | mcSHOW_DBG_MSG6(("test2_2: 0x%x\n", p->test2_2)); |
| 2596 | mcSHOW_DBG_MSG6(("frequency: %d\n", p->frequency)); |
| 2597 | mcSHOW_DBG_MSG6(("freqGroup: %d\n", p->freqGroup)); |
| 2598 | mcSHOW_DBG_MSG6(("lp5_training_mode: %d\n", p->lp5_training_mode)); |
| 2599 | mcSHOW_DBG_MSG6(("lp5_cbt_phase: %d\n", p->lp5_cbt_phase)); |
| 2600 | mcSHOW_DBG_MSG6(("new_cbt_mode: %d\n", p->new_cbt_mode)); |
| 2601 | mcSHOW_DBG_MSG6(("u1PLLMode: %d\n", p->u1PLLMode)); |
| 2602 | mcSHOW_DBG_MSG6(("curDBIState: %d\n", p->curDBIState)); |
| 2603 | } |
| 2604 | |
| 2605 | |
| 2606 | void DPI_SW_main_LP4(DRAMC_CTX_T *ExtConfig, cal_sv_rand_args_t *psra) |
| 2607 | { |
| 2608 | u32 value; |
| 2609 | #if DV_SIMULATION_DFS |
| 2610 | S8 s1ShuIdx; |
| 2611 | #endif |
| 2612 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2613 | DRAMC_CTX_T *p = &DramCtx_LPDDR4; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2614 | |
| 2615 | p->dram_type = ExtConfig->dram_type; |
| 2616 | if(p->dram_type==TYPE_LPDDR5) |
| 2617 | { |
| 2618 | MEM_TYPE = LPDDR5; |
| 2619 | } |
| 2620 | else |
| 2621 | { |
| 2622 | MEM_TYPE = LPDDR4; |
| 2623 | } |
| 2624 | |
| 2625 | p->dram_cbt_mode[0] = ExtConfig->dram_cbt_mode[0]; |
| 2626 | p->dram_cbt_mode[1] = ExtConfig->dram_cbt_mode[1]; |
| 2627 | p->freq_sel = ExtConfig->freq_sel; |
| 2628 | p->frequency = ExtConfig->frequency; |
| 2629 | p->freqGroup = ExtConfig->freqGroup; |
| 2630 | p->new_cbt_mode = ExtConfig->new_cbt_mode; |
| 2631 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2632 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2633 | DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2634 | {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, |
| 2635 | {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, |
| 2636 | {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, |
| 2637 | {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, |
| 2638 | {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, |
| 2639 | {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, |
| 2640 | {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2641 | }; |
| 2642 | #endif |
| 2643 | if (u1IsLP4Family(p->dram_type)) |
| 2644 | { |
| 2645 | if((ExtConfig->freq_sel==LP4_DDR3733) || (ExtConfig->freq_sel==LP4_DDR4266)) |
| 2646 | { |
| 2647 | p->pDFSTable = &gFreqTbl[1]; |
| 2648 | } |
| 2649 | else if(ExtConfig->freq_sel==LP4_DDR1600) |
| 2650 | { |
| 2651 | p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX - 1]; |
| 2652 | } |
| 2653 | else if(ExtConfig->freq_sel==LP4_DDR800) |
| 2654 | { |
| 2655 | p->pDFSTable = &gFreqTbl[2]; |
| 2656 | } |
| 2657 | #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION |
| 2658 | else if(ExtConfig->freq_sel==LP4_DDR400) |
| 2659 | { |
| 2660 | p->pDFSTable = &gFreqTbl[2]; |
| 2661 | } |
| 2662 | #endif |
| 2663 | } |
| 2664 | |
| 2665 | enter_function(); |
| 2666 | |
| 2667 | if (!psra) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2668 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2669 | mcSHOW_DBG_MSG6(("enter SA's simulation flow.\n")); |
| 2670 | p->support_channel_num = CHANNEL_SINGLE; |
| 2671 | p->channel = CHANNEL_A; |
| 2672 | p->support_rank_num = RANK_DUAL; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2673 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2674 | p->rank = RANK_0; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2675 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2676 | #if (fcFOR_CHIP_ID == fcA60868) |
| 2677 | #if DV_SIMULATION_DFS |
| 2678 | p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX-1]; |
| 2679 | #endif |
| 2680 | #endif |
| 2681 | #if 0 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2682 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2683 | #if DV_SIMULATION_LP4 |
| 2684 | p->dram_type = TYPE_LPDDR4X; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2685 | //p->freq_sel = LP4_DDR3200; |
| 2686 | //p->frequency = 1600; |
| 2687 | p->freq_sel = LP4_DDR1600; |
| 2688 | p->frequency = 800; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2689 | #else |
| 2690 | p->dram_type = TYPE_LPDDR5; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2691 | p->freq_sel = LP5_DDR3200; |
| 2692 | p->frequency = 1600; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2693 | #endif |
| 2694 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2695 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2696 | p->dram_fsp = FSP_0; |
| 2697 | |
| 2698 | #if 0 |
| 2699 | #if DV_SIMULATION_BYTEMODE |
| 2700 | p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1; |
| 2701 | p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1; |
| 2702 | #else |
| 2703 | p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; |
| 2704 | p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; |
| 2705 | #endif |
| 2706 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2707 | |
| 2708 | p->DBI_R_onoff[FSP_0] = DBI_OFF; |
| 2709 | p->DBI_R_onoff[FSP_1] = DBI_OFF; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2710 | #if ENABLE_READ_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2711 | p->DBI_R_onoff[FSP_1] = DBI_ON; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2712 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2713 | p->DBI_R_onoff[FSP_1] = DBI_OFF; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2714 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2715 | |
| 2716 | p->DBI_W_onoff[FSP_0] = DBI_OFF; |
| 2717 | p->DBI_W_onoff[FSP_1] = DBI_OFF; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2718 | #if ENABLE_WRITE_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2719 | p->DBI_W_onoff[FSP_1] = DBI_ON; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2720 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2721 | p->DBI_W_onoff[FSP_1] = DBI_OFF; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2722 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2723 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2724 | p->data_width = DATA_WIDTH_16BIT; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2725 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2726 | p->test2_1 = DEFAULT_TEST2_1_CAL; |
| 2727 | p->test2_2 = DEFAULT_TEST2_2_CAL; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2728 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2729 | p->test_pattern = TEST_XTALK_PATTERN; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2730 | |
| 2731 | p->u2DelayCellTimex100 = 250; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2732 | p->vendor_id = 0x1; |
| 2733 | p->density = 0; |
| 2734 | /* p->ranksize = {0,0}; */ |
| 2735 | p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; |
| 2736 | #if DV_SIMULATION_LP5_TRAINING_MODE1 |
| 2737 | p->lp5_training_mode = TRAINING_MODE1; |
| 2738 | #else |
| 2739 | p->lp5_training_mode = TRAINING_MODE2; |
| 2740 | #endif |
| 2741 | |
| 2742 | #if DV_SIMULATION_LP5_CBT_PHASH_R |
| 2743 | p->lp5_cbt_phase = CBT_PHASE_RISING; |
| 2744 | #else |
| 2745 | p->lp5_cbt_phase = CBT_PHASE_FALLING; |
| 2746 | #endif |
| 2747 | } else { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2748 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2749 | mcSHOW_DBG_MSG6(("enter DV's regression flow.\n")); |
| 2750 | p->support_channel_num = CHANNEL_SINGLE; |
| 2751 | p->channel = psra->calibration_channel; |
| 2752 | p->support_rank_num = RANK_DUAL; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2753 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2754 | p->rank = psra->calibration_rank; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2755 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2756 | #if (fcFOR_CHIP_ID == fcA60868) |
| 2757 | #if DV_SIMULATION_DFS |
| 2758 | p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX-1]; |
| 2759 | #endif |
| 2760 | #endif |
| 2761 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2762 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2763 | //p->dram_type = psra->dram_type; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2764 | //p->freq_sel = LP5_DDR4266; |
| 2765 | //p->frequency = 2133; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2766 | set_type_freq_by_svargs(p, psra); |
| 2767 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2768 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2769 | p->dram_fsp = FSP_0; |
| 2770 | |
| 2771 | p->dram_cbt_mode[RANK_0] = psra->rk0_cbt_mode; |
| 2772 | p->dram_cbt_mode[RANK_1] = psra->rk1_cbt_mode; |
| 2773 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2774 | |
| 2775 | p->DBI_R_onoff[FSP_0] = (psra->mr3_value >> 6) & 0x1; |
| 2776 | p->DBI_R_onoff[FSP_1] = (psra->mr3_value >> 6) & 0x1; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2777 | p->DBI_R_onoff[FSP_2] = (psra->mr3_value >> 6) & 0x1; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2778 | |
| 2779 | p->DBI_W_onoff[FSP_0] = (psra->mr3_value >> 7) & 0x1; |
| 2780 | p->DBI_W_onoff[FSP_1] = (psra->mr3_value >> 7) & 0x1; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2781 | p->DBI_W_onoff[FSP_2] = (psra->mr3_value >> 7) & 0x1; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2782 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2783 | p->data_width = DATA_WIDTH_16BIT; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2784 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2785 | p->test2_1 = DEFAULT_TEST2_1_CAL; |
| 2786 | p->test2_2 = DEFAULT_TEST2_2_CAL; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2787 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2788 | p->test_pattern = TEST_XTALK_PATTERN; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2789 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2790 | p->u2DelayCellTimex100 = 0; |
| 2791 | p->vendor_id = 0x1; |
| 2792 | p->density = 0; |
| 2793 | /* p->ranksize = {0,0}; */ |
| 2794 | p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; |
| 2795 | p->lp5_training_mode = psra->cbt_training_mode; |
| 2796 | p->lp5_cbt_phase = psra->cbt_phase; |
| 2797 | p->new_cbt_mode = psra->new_cbt_mode; |
| 2798 | } |
| 2799 | |
| 2800 | #if QT_GUI_Tool |
| 2801 | p->lp5_training_mode = ExtConfig->lp5_training_mode; |
| 2802 | #endif |
| 2803 | |
| 2804 | if (psra && is_lp5_family(p)) { |
| 2805 | p->dram_fsp = (psra->mr16_value >> 2) & 0x3; |
| 2806 | } else if (psra && u1IsLP4Family(p->dram_type)) { |
| 2807 | p->dram_fsp = (psra->mr13_value >> 7) & 0x1; |
| 2808 | } |
| 2809 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2810 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2811 | #define __FW_VER__ "All struct move done, new RX range -- 444" |
| 2812 | |
| 2813 | if (u1IsLP4Family(p->dram_type)) { |
| 2814 | mcSHOW_DBG_MSG6(("%s enter == LP4 == ...%s\n", __FUNCTION__, __FW_VER__)); |
| 2815 | } else { |
| 2816 | mcSHOW_DBG_MSG6(("%s enter == LP5 == ...%s\n", __FUNCTION__, __FW_VER__)); |
| 2817 | } |
| 2818 | mcSHOW_DBG_MSG6((CHK_INCLUDE_LOCAL_HEADER)); |
| 2819 | |
| 2820 | mcSHOW_DBG_MSG6(("SIMULATION_LP4_ZQ ... %d\n", SIMULATION_LP4_ZQ)); |
| 2821 | mcSHOW_DBG_MSG6(("SIMULATION_SW_IMPED ... %d\n", SIMULATION_SW_IMPED)); |
| 2822 | mcSHOW_DBG_MSG6(("SIMULATION_MIOCK_JMETER ... %d\n", SIMULATION_MIOCK_JMETER)); |
| 2823 | mcSHOW_DBG_MSG6(("SIMULATION_8PHASE ... %d\n", SIMULATION_8PHASE)); |
| 2824 | mcSHOW_DBG_MSG6(("SIMULATION_RX_INPUT_BUF ... %d\n", SIMULATION_RX_INPUT_BUF)); |
| 2825 | mcSHOW_DBG_MSG6(("SIMUILATION_CBT ... %d\n", SIMUILATION_CBT)); |
| 2826 | mcSHOW_DBG_MSG6(("SIMULATION_WRITE_LEVELING ... %d\n", SIMULATION_WRITE_LEVELING)); |
| 2827 | mcSHOW_DBG_MSG6(("SIMULATION_DUTY_CYC_MONITOR ... %d\n", SIMULATION_DUTY_CYC_MONITOR)); |
| 2828 | mcSHOW_DBG_MSG6(("SIMULATION_GATING ... %d\n", SIMULATION_GATING)); |
| 2829 | mcSHOW_DBG_MSG6(("SIMULATION_DATLAT ... %d\n", SIMULATION_DATLAT)); |
| 2830 | mcSHOW_DBG_MSG6(("SIMULATION_RX_RDDQC ... %d\n", SIMULATION_RX_RDDQC)); |
| 2831 | mcSHOW_DBG_MSG6(("SIMULATION_RX_PERBIT ... %d\n", SIMULATION_RX_PERBIT)); |
| 2832 | mcSHOW_DBG_MSG6(("SIMULATION_TX_PERBIT ... %d\n", SIMULATION_TX_PERBIT)); |
| 2833 | mcSHOW_DBG_MSG6(("\n\n")); |
| 2834 | |
| 2835 | mcSHOW_DBG_MSG6(("============== CTX before calibration ================\n")); |
| 2836 | dump_dramc_ctx(p); |
| 2837 | |
| 2838 | DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); |
| 2839 | |
| 2840 | //vIO32Write4B_All2(p, DDRPHY_SHU_RK_CA_CMD1, 0x0FFF); |
| 2841 | value = u4Dram_Register_Read(p, DRAMC_REG_DDRCOMMON0); |
| 2842 | mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DRAMC_REG_DDRCOMMON0, value)); |
| 2843 | |
| 2844 | value = u4Dram_Register_Read(p, DDRPHY_REG_SHU_RK_CA_CMD1); |
| 2845 | mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_SHU_RK_CA_CMD1, value)); |
| 2846 | |
| 2847 | value = u4Dram_Register_Read(p, DDRPHY_REG_MISC_DQO1); |
| 2848 | mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_MISC_DQO1, value)); |
| 2849 | |
| 2850 | value = u4Dram_Register_Read(p, DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL ); |
| 2851 | mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL, value)); |
| 2852 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2853 | DramcBroadcastOnOff(DRAMC_BROADCAST_ON); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2854 | |
| 2855 | Global_Option_Init(p); |
| 2856 | |
| 2857 | #if __A60868_TO_BE_PORTING__ |
| 2858 | vDramcInit_PreSettings(p); |
| 2859 | |
| 2860 | DDRPhyFreqSel(p, p->pDFSTable->freq_sel); |
| 2861 | |
| 2862 | vSetPHY2ChannelMapping(p, p->channel); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2863 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2864 | |
| 2865 | |
| 2866 | if (u1IsLP4Family(p->dram_type)) |
| 2867 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2868 | vSetDFSFreqSelByTable(p, p->pDFSTable); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2869 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2870 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2871 | { |
| 2872 | DDRPhyFreqSel(p, p->freq_sel); |
| 2873 | } |
| 2874 | |
| 2875 | #if (SIMULATION_SW_IMPED == 1) |
| 2876 | mcSHOW_DBG_MSG6(("\n----->DramcImpedanceCal begin...\n")); |
| 2877 | timestamp_show(); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2878 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2879 | DramcImpedanceCal(p, 1, IMP_LOW_FREQ); |
| 2880 | DramcImpedanceCal(p, 1, IMP_HIGH_FREQ); |
| 2881 | timestamp_show(); |
| 2882 | mcSHOW_DBG_MSG6(("DramcImpedanceCal end<-----\n\n")); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2883 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2884 | |
| 2885 | #if DV_SIMULATION_INIT_C |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2886 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2887 | DramcInit(p); |
| 2888 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2889 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2890 | vBeforeCalibration(p); |
| 2891 | #if __A60868_TO_BE_PORTING__ |
| 2892 | #if DV_SIMULATION_BEFORE_K |
| 2893 | vApplyConfigBeforeCalibration(p); |
| 2894 | //vMR2InitForSimulationTest(p); |
| 2895 | #endif |
| 2896 | |
| 2897 | #ifdef DUMP_INIT_RG_LOG_TO_DE |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2898 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2899 | mcSHOW_DUMP_INIT_RG_MSG(("\n\n\n\n\n\n===== Save to Shuffle RG ======\n")); |
| 2900 | DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3); |
| 2901 | #endif |
| 2902 | while (1); |
| 2903 | #endif |
| 2904 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2905 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2906 | |
| 2907 | |
| 2908 | #if (SIMULATION_MIOCK_JMETER == 1) |
| 2909 | mcSHOW_DBG_MSG6(("\n----->DramcMiockJmeter begin...\n")); |
| 2910 | timestamp_show(); |
| 2911 | p->u2DelayCellTimex100 = GetVcoreDelayCellTime(p); |
| 2912 | timestamp_show(); |
| 2913 | mcSHOW_DBG_MSG6(("DramcMiockJmeter end<-----\n\n")); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2914 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2915 | |
| 2916 | #if (SIMULATION_8PHASE == 1) |
| 2917 | if(is_lp5_family(p) && (p->frequency >= 2133)) { |
| 2918 | mcSHOW_DBG_MSG6(("\n----->Dramc8PhaseCal begin...\n")); |
| 2919 | timestamp_show(); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2920 | Dramc8PhaseCal(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2921 | timestamp_show(); |
| 2922 | mcSHOW_DBG_MSG6(("Dramc8PhaseCal end<-----\n\n")); |
| 2923 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2924 | #endif |
| 2925 | #if !DV_SIMULATION_DFS |
| 2926 | DPI_vDramCalibrationAllChannel(p, psra); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2927 | #endif |
| 2928 | |
| 2929 | #if DV_SIMULATION_DFS |
| 2930 | DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, vGet_Current_SRAMIdx(p)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2931 | LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2932 | |
| 2933 | #if (fcFOR_CHIP_ID == fcA60868) |
| 2934 | for (s1ShuIdx = DRAM_DFS_SRAM_MAX - 10; s1ShuIdx >= 0; s1ShuIdx--) |
| 2935 | #else |
| 2936 | for (s1ShuIdx = DRAM_DFS_SRAM_MAX - 2; s1ShuIdx >= 0; s1ShuIdx--) |
| 2937 | #endif |
| 2938 | { |
| 2939 | vSetDFSFreqSelByTable(p, &gFreqTbl[s1ShuIdx]); |
| 2940 | DramcInit(p); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2941 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2942 | vBeforeCalibration(p); |
| 2943 | |
| 2944 | #if DV_SIMULATION_BEFORE_K |
| 2945 | vApplyConfigBeforeCalibration(p); |
| 2946 | #endif |
| 2947 | |
| 2948 | #if (SIMULATION_8PHASE == 1) |
| 2949 | if(is_lp5_family(p) && (p->frequency >= 2133)) { |
| 2950 | mcSHOW_DBG_MSG6(("\n----->Dramc8PhaseCal begin...\n")); |
| 2951 | timestamp_show(); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2952 | Dramc8PhaseCal(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2953 | timestamp_show(); |
| 2954 | mcSHOW_DBG_MSG6(("Dramc8PhaseCal end<-----\n\n")); |
| 2955 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2956 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2957 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2958 | #if !DV_SIMULATION_DFS |
| 2959 | DPI_vDramCalibrationAllChannel(p, psra); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2960 | #endif |
| 2961 | DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, gFreqTbl[s1ShuIdx].SRAMIdx); |
| 2962 | } |
| 2963 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2964 | |
| 2965 | |
| 2966 | |
| 2967 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2968 | |
| 2969 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2970 | vAfterCalibration(p); |
| 2971 | |
| 2972 | #if SIMULATION_RUNTIME_CONFIG |
| 2973 | DramcRunTimeConfig(p); |
| 2974 | #endif |
| 2975 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2976 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2977 | #if DV_SIMULATION_AFTER_K |
| 2978 | vApplyConfigAfterCalibration(p); |
| 2979 | #endif |
| 2980 | |
| 2981 | #if DV_SIMULATION_RUN_TIME_MRW |
| 2982 | enter_pasr_dpd_config(0, 0xFF); |
| 2983 | #endif |
| 2984 | |
| 2985 | #if DV_SIMULATION_RUN_TIME_MRR |
| 2986 | DramcModeRegReadByRank(p, RANK_0, 4, &u2val1); |
| 2987 | DramcModeRegReadByRank(p, RANK_0, 5, &u2val2); |
| 2988 | DramcModeRegReadByRank(p, RANK_0, 8, &u2val3); |
| 2989 | mcSHOW_DBG_MSG(("[Runtime time MRR] MR4 = 0x%x, MR5 = 0x%x, MR8 = 0x%x\n", u2val1, u2val2, u2val3)); |
| 2990 | #endif |
| 2991 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2992 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2993 | for (s1ShuIdx = 0; s1ShuIdx < DV_SIMULATION_DFS_SHU_MAX; s1ShuIdx++) |
| 2994 | DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].SRAMIdx); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2995 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2996 | for (s1ShuIdx = DV_SIMULATION_DFS_SHU_MAX - 1; s1ShuIdx >= DRAM_DFS_SHUFFLE_1; s1ShuIdx--) |
| 2997 | DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].SRAMIdx); |
| 2998 | #endif |
| 2999 | |
| 3000 | #if DV_SIMULATION_SPM_CONTROL |
| 3001 | EnablePLLtoSPMControl(p); |
| 3002 | #endif |
| 3003 | |
| 3004 | RG_dummy_write(p, 0xAAAAAAAA); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3005 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3006 | |
| 3007 | //Temp_TA2_Test_After_K(p); |
| 3008 | |
| 3009 | //Ett_Mini_Strss_Test(p); |
| 3010 | #if MRW_CHECK_ONLY |
| 3011 | vPrintFinalModeRegisterSetting(p); |
| 3012 | #endif |
| 3013 | #if PRINT_CALIBRATION_SUMMARY |
| 3014 | vPrintCalibrationResult(p); |
| 3015 | #endif |
| 3016 | |
| 3017 | exit_function(); |
| 3018 | } |
| 3019 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3020 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3021 | void start_dramk(void) |
| 3022 | { |
| 3023 | DRAMC_CTX_T *p; |
| 3024 | |
| 3025 | enter_function(); |
| 3026 | broadcast_off(); |
| 3027 | p = &DramCtx_LPDDR4; |
| 3028 | DPI_SW_main_LP4(p, NULL); |
| 3029 | exit_function(); |
| 3030 | } |
| 3031 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3032 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3033 | void sa_calibration(cal_sv_rand_args_t *psra) |
| 3034 | { |
| 3035 | DRAMC_CTX_T *p; |
| 3036 | |
| 3037 | enter_function(); |
| 3038 | if (psra == NULL) { |
| 3039 | mcSHOW_DBG_MSG6(("psv_args is NULL.\n")); |
| 3040 | goto out; |
| 3041 | } |
| 3042 | |
| 3043 | print_sv_args(psra); |
| 3044 | if (!valid_magic(psra)) { |
| 3045 | mcSHOW_DBG_MSG6(("sv arguments is invalid.\n")); |
| 3046 | goto out; |
| 3047 | } |
| 3048 | |
| 3049 | set_psra(psra); |
| 3050 | broadcast_off(); |
| 3051 | if (psra->calibration_channel == SV_CHN_A) |
| 3052 | p = &DramCtx_LPDDR4; |
| 3053 | else |
| 3054 | p = &dram_ctx_chb; |
| 3055 | |
| 3056 | DPI_SW_main_LP4(p, psra); |
| 3057 | |
| 3058 | out: |
| 3059 | exit_function(); |
| 3060 | return; |
| 3061 | } |
| 3062 | |
| 3063 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3064 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3065 | #if __A60868_TO_BE_PORTING__ |
| 3066 | #if SW_CHANGE_FOR_SIMULATION |
| 3067 | void main(void) |
| 3068 | { |
| 3069 | |
| 3070 | DRAMC_CTX_T DramConfig; |
| 3071 | DramConfig.channel = CHANNEL_A; |
| 3072 | DramConfig.support_rank_num = RANK_DUAL; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3073 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3074 | DramConfig.rank = RANK_0; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3075 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3076 | DramConfig.dram_type = TYPE_LPDDR4X; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3077 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3078 | DramConfig.dram_fsp = FSP_0; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3079 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3080 | DramConfig.dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; |
| 3081 | DramConfig.dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3082 | |
| 3083 | DramConfig.DBI_R_onoff[FSP_0] = DBI_OFF; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3084 | #if ENABLE_READ_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3085 | DramConfig.DBI_R_onoff[FSP_1] = DBI_ON; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3086 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3087 | DramConfig.DBI_R_onoff[FSP_1] = DBI_OFF; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3088 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3089 | |
| 3090 | DramConfig.DBI_W_onoff[FSP_0] = DBI_OFF; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3091 | #if ENABLE_WRITE_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3092 | DramConfig.DBI_W_onoff[FSP_1] = DBI_ON; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3093 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3094 | DramConfig.DBI_W_onoff[FSP_1] = DBI_OFF; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3095 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3096 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3097 | DramConfig.data_width = DATA_WIDTH_32BIT; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3098 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3099 | DramConfig.test2_1 = DEFAULT_TEST2_1_CAL; |
| 3100 | DramConfig.test2_2 = DEFAULT_TEST2_2_CAL; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3101 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3102 | DramConfig.test_pattern = TEST_XTALK_PATTERN; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3103 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3104 | DramConfig.frequency = 800; |
| 3105 | |
| 3106 | //DramConfig.enable_rx_scan_vref =DISABLE; |
| 3107 | //DramConfig.enable_tx_scan_vref =DISABLE; |
| 3108 | //DramConfig.dynamicODT = DISABLE; |
| 3109 | |
| 3110 | MPLLInit(); |
| 3111 | |
| 3112 | Global_Option_Init(&DramConfig); |
| 3113 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3114 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3115 | DDRPhyFreqSel(&DramConfig, LP4_DDR1600); |
| 3116 | |
| 3117 | |
| 3118 | #if WRITE_LEVELING_MOVE_DQS_INSTEAD_OF_CLK |
| 3119 | memset(DramConfig.arfgWriteLevelingInitShif, FALSE, sizeof(DramConfig.arfgWriteLevelingInitShif)); |
| 3120 | //>fgWriteLevelingInitShif= FALSE; |
| 3121 | #endif |
| 3122 | |
| 3123 | DramcInit(&DramConfig); |
| 3124 | |
| 3125 | vApplyConfigBeforeCalibration(&DramConfig); |
| 3126 | vMR2InitForSimulationTest(&DramConfig); |
| 3127 | |
| 3128 | vSetPHY2ChannelMapping(&DramConfig, DramConfig.channel); |
| 3129 | |
| 3130 | #if SIMULATION_SW_IMPED |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3131 | DramcImpedanceCal(&DramConfig, 1, LOW_FREQ); |
| 3132 | //DramcImpedanceCal(&DramConfig, 1, HIGH_FREQ); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3133 | #endif |
| 3134 | |
| 3135 | |
| 3136 | #if SIMULATION_LP4_ZQ |
| 3137 | if (DramConfig.dram_type == TYPE_LPDDR4 || DramConfig.dram_type == TYPE_LPDDR4X || DramConfig.dram_type == TYPE_LPDDR4P) |
| 3138 | { |
| 3139 | DramcZQCalibration(&DramConfig); |
| 3140 | } |
| 3141 | #endif |
| 3142 | |
| 3143 | #if SIMUILATION_LP4_CBT |
| 3144 | CmdBusTrainingLP4(&DramConfig); |
| 3145 | #endif |
| 3146 | |
| 3147 | #if SIMULATION_WRITE_LEVELING |
| 3148 | DramcWriteLeveling(&DramConfig); |
| 3149 | #endif |
| 3150 | |
| 3151 | #if SIMULATION_GATING |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3152 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3153 | DramcRxdqsGatingCal(&DramConfig); |
| 3154 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3155 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3156 | //DualRankDramcRxdqsGatingCal(&DramConfig); |
| 3157 | #endif |
| 3158 | |
| 3159 | #if SIMUILATION_LP4_RDDQC |
| 3160 | DramcRxWindowPerbitCal(&DramConfig, 0, NULL); |
| 3161 | #endif |
| 3162 | |
| 3163 | #if SIMULATION_DATLAT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3164 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3165 | DramcRxdatlatCal(&DramConfig); |
| 3166 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3167 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3168 | //DramcDualRankRxdatlatCal(&DramConfig); |
| 3169 | #endif |
| 3170 | |
| 3171 | #if SIMULATION_RX_PERBIT |
| 3172 | DramcRxWindowPerbitCal(&DramConfig, 1, NULL); |
| 3173 | #endif |
| 3174 | |
| 3175 | #if SIMULATION_TX_PERBIT |
| 3176 | DramcTxWindowPerbitCal(&DramConfig, TX_DQ_DQS_MOVE_DQ_DQM); |
| 3177 | DramcTxWindowPerbitCal(&DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY); |
| 3178 | #endif |
| 3179 | |
| 3180 | #if ENABLE_READ_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3181 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3182 | SetDramModeRegForReadDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_R_onoff[DramConfig.dram_fsp]); |
| 3183 | #endif |
| 3184 | |
| 3185 | #if ENABLE_WRITE_DBI |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3186 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3187 | DramcWriteShiftMCKForWriteDBI(&DramConfig, -1); |
| 3188 | SetDramModeRegForWriteDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]); |
| 3189 | #endif |
| 3190 | |
| 3191 | #if ENABLE_READ_DBI |
| 3192 | DramcReadDBIOnOff(&DramConfig, DramConfig.DBI_R_onoff[DramConfig.dram_fsp]); |
| 3193 | #endif |
| 3194 | |
| 3195 | #if ENABLE_WRITE_DBI |
| 3196 | DramcWriteDBIOnOff(&DramConfig, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]); |
| 3197 | #endif |
| 3198 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3199 | #endif |
| 3200 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3201 | #endif |
| 3202 | |