Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <timer.h> |
| 4 | #include <soc/usb/qmp_usb_phy.h> |
| 5 | #include <soc/addressmap.h> |
| 6 | |
| 7 | |
| 8 | /* Only for QMP V4 PHY - QSERDES COM registers */ |
| 9 | struct usb3_phy_qserdes_com_reg_layout { |
| 10 | u8 _reserved1[16]; |
| 11 | u32 com_ssc_en_center; |
| 12 | u32 com_ssc_adj_per1; |
| 13 | u32 com_ssc_adj_per2; |
| 14 | u32 com_ssc_per1; |
| 15 | u32 com_ssc_per2; |
| 16 | u32 com_ssc_step_size1_mode0; |
| 17 | u32 com_ssc_step_size2_mode0; |
| 18 | u32 com_ssc_step_size3_mode0; |
| 19 | u32 com_ssc_step_size1_mode1; |
| 20 | u32 com_ssc_step_size2_mode1; |
| 21 | u32 com_ssc_step_size3_mode1; |
| 22 | u8 _reserved2[8]; |
| 23 | u32 com_bias_en_clkbuflr_en; |
| 24 | u32 com_sys_clk_enable1; |
| 25 | u32 com_sys_clk_ctrl; |
| 26 | u32 com_sysclk_buf_enable; |
| 27 | u32 com_pll_en; |
| 28 | u32 com_pll_ivco; |
| 29 | u8 _reserved3[4]; |
| 30 | u32 com_cmn_iptrim; |
| 31 | u8 _reserved4[16]; |
| 32 | u32 com_cp_ctrl_mode0; |
| 33 | u32 com_cp_ctrl_mode1; |
| 34 | u32 com_pll_rctrl_mode0; |
| 35 | u32 com_pll_rctrl_mode1; |
| 36 | u32 com_pll_cctrl_mode0; |
| 37 | u32 com_pll_cctrl_mode1; |
| 38 | u8 _reserved6[8]; |
| 39 | u32 com_sysclk_en_sel; |
| 40 | u8 _reserved7[8]; |
| 41 | u32 com_resetsm_ctrl2; |
| 42 | u32 com_lock_cmp_en; |
| 43 | u32 com_lock_cmp_cfg; |
| 44 | u32 com_lock_cmp1_mode0; |
| 45 | u32 com_lock_cmp2_mode0; |
| 46 | u32 com_lock_cmp1_mode1; |
| 47 | u32 com_lock_cmp2_mode1; |
| 48 | u32 com_dec_start_mode0; |
| 49 | u8 _reserved8[4]; |
| 50 | u32 com_dec_start_mode1; |
| 51 | u8 _reserved9[4]; |
| 52 | u32 com_div_frac_start1_mode0; |
| 53 | u32 com_div_frac_start2_mode0; |
| 54 | u32 com_div_frac_start3_mode0; |
| 55 | u32 com_div_frac_start1_mode1; |
| 56 | u32 com_div_frac_start2_mode1; |
| 57 | u32 com_div_frac_start3_mode1; |
| 58 | u8 _reserved10[8]; |
| 59 | u32 com_integloop_gain0_mode0; |
| 60 | u32 com_integloop_gain1_mode0; |
| 61 | u8 _reserved11[24]; |
| 62 | u32 com_vco_tune_map; |
| 63 | u32 com_vco_tune1_mode0; |
| 64 | u32 com_vco_tune2_mode0; |
| 65 | u32 com_vco_tune1_mode1; |
| 66 | u32 com_vco_tune2_mode1; |
| 67 | u8 _reserved12[52]; |
| 68 | u32 com_clk_select; |
| 69 | u32 com_hsclk_sel; |
| 70 | u8 _reserved13[12]; |
| 71 | u32 com_coreclk_div_mode0; |
| 72 | u32 com_coreclk_div_mode1; |
| 73 | u8 _reserved14[4]; |
| 74 | u32 com_core_clk_en; |
| 75 | u32 com_c_ready_status; |
| 76 | u32 com_cmn_config; |
| 77 | u32 com_cmn_rate_override; |
| 78 | u32 com_svs_mode_clk_sel; |
| 79 | u8 _reserved15[36]; |
| 80 | u32 com_bin_vcocal_cmp_code1_mode0; |
| 81 | u32 com_bin_vcocal_cmp_code2_mode0; |
| 82 | u32 com_bin_vcocal_cmp_code1_mode1; |
| 83 | u32 com_bin_vcocal_cmp_code2_mode1; |
| 84 | u32 com_bin_vcocal_hsclk_sel; |
| 85 | }; |
| 86 | |
| 87 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); |
| 88 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); |
| 89 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); |
| 90 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); |
| 91 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); |
| 92 | check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x044); |
| 93 | check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x058); |
| 94 | check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x074); |
| 95 | check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x094); |
| 96 | check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x0a0); |
| 97 | check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0bc); |
| 98 | check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0cc); |
| 99 | check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0ec); |
| 100 | check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x010c); |
| 101 | check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x154); |
| 102 | check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x168); |
| 103 | check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x174); |
| 104 | check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x184); |
| 105 | check_member(usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_hsclk_sel, 0x1bc); |
| 106 | |
| 107 | /* Only for QMP V4 PHY - TX registers */ |
| 108 | struct usb3_phy_qserdes_tx_reg_layout { |
| 109 | u8 _reserved1[52]; |
| 110 | u32 tx_res_code_lane_tx; |
| 111 | u32 tx_res_code_lane_rx; |
| 112 | u32 tx_res_code_lane_offset_tx; |
| 113 | u32 tx_res_code_lane_offset_rx; |
| 114 | u8 _reserved2[64]; |
| 115 | u32 tx_lane_mode_1; |
| 116 | u8 _reserved3[20]; |
| 117 | u32 tx_rcv_detect_lvl_2; |
| 118 | u8 _reserved4[100]; |
| 119 | u32 tx_pi_qec_ctrl; |
| 120 | }; |
| 121 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x03c); |
| 122 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x040); |
| 123 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x084); |
| 124 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x09c); |
| 125 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_pi_qec_ctrl, 0x104); |
| 126 | |
| 127 | /* Only for QMP V4 PHY - RX registers */ |
| 128 | struct usb3_phy_qserdes_rx_reg_layout { |
| 129 | u8 _reserved1[20]; |
| 130 | u32 rx_ucdr_so_gain; |
| 131 | u8 _reserved2[24]; |
| 132 | u32 rx_ucdr_fastlock_fo_gain; |
| 133 | u32 rx_ucdr_so_saturation_and_enable; |
| 134 | u8 _reserved3[4]; |
| 135 | u32 rx_ucdr_fastlock_count_low; |
| 136 | u32 rx_ucdr_fastlock_count_high; |
| 137 | u32 rx_ucdr_pi_controls; |
| 138 | u8 _reserved4[4]; |
| 139 | u32 rx_ucdr_sb2_thresh1; |
| 140 | u32 rx_ucdr_sb2_thresh2; |
| 141 | u32 rx_ucdr_sb2_gain1; |
| 142 | u32 rx_ucdr_sb2_gain2; |
| 143 | u8 _reserved12[4]; |
| 144 | u32 rx_aux_data_tcoarse_tfine; |
| 145 | u8 _reserved5[112]; |
| 146 | u32 rx_vga_cal_cntrl1; |
| 147 | u32 rx_vga_cal_cntrl2; |
| 148 | u32 rx_gm_cal; |
| 149 | u8 _reserved6[12]; |
| 150 | u32 rx_rx_equ_adaptor_cntrl2; |
| 151 | u32 rx_rx_equ_adaptor_cntrl3; |
| 152 | u32 rx_rx_equ_adaptor_cntrl4; |
| 153 | u32 rx_rx_idac_tsettle_low; |
| 154 | u32 rx_rx_idac_tsettle_high; |
| 155 | u8 _reserved7[16]; |
| 156 | u32 rx_rx_eq_offset_adaptor_cntrl1; |
| 157 | u8 _reserved8[8]; |
| 158 | u32 rx_sigdet_cntrl; |
| 159 | u8 _reserved9[4]; |
| 160 | u32 rx_sigdet_deglitch_cntrl; |
| 161 | u8 _reserved10[72]; |
| 162 | u32 rx_rx_mode_00_low; |
| 163 | u32 rx_rx_mode_00_high; |
| 164 | u32 rx_rx_mode_00_high2; |
| 165 | u32 rx_rx_mode_00_high3; |
| 166 | u32 rx_rx_mode_00_high4; |
| 167 | u32 rx_rx_mode_01_low; |
| 168 | u32 rx_rx_mode_01_high; |
| 169 | u32 rx_rx_mode_01_high2; |
| 170 | u32 rx_rx_mode_01_high3; |
| 171 | u32 rx_rx_mode_01_high4; |
| 172 | u8 _reserved11[28]; |
| 173 | u32 rx_dfe_en_timer; |
| 174 | u32 rx_dfe_ctle_post_cal_offset; |
| 175 | u32 rx_dcc_ctrl1; |
| 176 | u8 _reserved13[4]; |
| 177 | u32 rx_vth_code; |
| 178 | }; |
| 179 | |
| 180 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain, 0x014); |
| 181 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); |
| 182 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1, 0x0d4); |
| 183 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl2, 0x0ec); |
| 184 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl3, 0x0f0); |
| 185 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl4, 0x0f4); |
| 186 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl, 0x11c); |
| 187 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_dcc_ctrl1, 0x1bc); |
| 188 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_vth_code, 0x1c4); |
| 189 | |
| 190 | /* Only for QMP V4 PHY - PCS registers */ |
| 191 | struct usb3_phy_pcs_reg_layout { |
| 192 | u32 pcs_sw_reset; |
| 193 | u8 _reserved0[16]; |
| 194 | u32 pcs_ready_status; |
| 195 | u8 _reserved1[40]; |
| 196 | u32 pcs_power_down_control; |
| 197 | u32 pcs_start_control; |
| 198 | u8 _reserved2[124]; |
| 199 | u32 pcs_lock_detect_config1; |
| 200 | u32 pcs_lock_detect_config2; |
| 201 | u32 pcs_lock_detect_config3; |
| 202 | u8 _reserved3[8]; |
| 203 | u32 pcs_lock_detect_config6; |
| 204 | u32 pcs_refgen_req_config1; |
| 205 | u8 _reserved4[168]; |
| 206 | u32 pcs_rx_sigdet_lvl; |
| 207 | u8 _reserved5[36]; |
| 208 | u32 pcs_cdr_reset_time; |
| 209 | u8 _reserved6[12]; |
| 210 | u32 pcs_align_detect_config1; |
| 211 | u32 pcs_align_detect_config2; |
| 212 | u8 _reserved7[8]; |
| 213 | u32 pcs_pcs_tx_rx_config; |
| 214 | u8 _reserved8[8]; |
| 215 | u32 pcs_eq_config1; |
| 216 | u8 _reserved9[12]; |
| 217 | u32 pcs_eq_config5; |
| 218 | u8 _reserved10[296]; |
| 219 | u32 pcs_usb3_lfps_det_high_count_val; |
| 220 | u8 _reserved11[28]; |
| 221 | u32 pcs_usb3_rxeqtraining_dfe_time_s2; |
| 222 | }; |
| 223 | |
| 224 | check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x0c4); |
| 225 | check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x0c8); |
| 226 | check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config6, 0x0d8); |
| 227 | check_member(usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config, 0x1d0); |
| 228 | check_member(usb3_phy_pcs_reg_layout, pcs_eq_config5, 0x1ec); |
| 229 | check_member(usb3_phy_pcs_reg_layout, pcs_usb3_lfps_det_high_count_val, 0x318); |
| 230 | check_member(usb3_phy_pcs_reg_layout, pcs_usb3_rxeqtraining_dfe_time_s2, 0x338); |
| 231 | |
| 232 | static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = |
| 233 | (void *)QMP_PHY_QSERDES_COM_REG_BASE; |
| 234 | static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = |
| 235 | (void *)QMP_PHY_QSERDES_TX_REG_BASE; |
| 236 | static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = |
| 237 | (void *)QMP_PHY_QSERDES_RX_REG_BASE; |
| 238 | static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = |
| 239 | (void *)QMP_PHY_PCS_REG_BASE; |
| 240 | static const struct qmp_phy_init_tbl qmp_v4_usb3_serdes_tbl[] = { |
| 241 | {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, |
| 242 | {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, |
| 243 | {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, |
| 244 | {&qserdes_com_reg_layout->com_ssc_step_size1_mode0, 0xde}, |
| 245 | {&qserdes_com_reg_layout->com_ssc_step_size2_mode0, 0x07}, |
| 246 | {&qserdes_com_reg_layout->com_ssc_step_size1_mode1, 0xde}, |
| 247 | {&qserdes_com_reg_layout->com_ssc_step_size2_mode1, 0x07}, |
| 248 | {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, |
| 249 | {&qserdes_com_reg_layout->com_cmn_iptrim, 0x20}, |
| 250 | {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, |
| 251 | {&qserdes_com_reg_layout->com_cp_ctrl_mode1, 0x06}, |
| 252 | {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, |
| 253 | {&qserdes_com_reg_layout->com_pll_rctrl_mode1, 0x16}, |
| 254 | {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, |
| 255 | {&qserdes_com_reg_layout->com_pll_cctrl_mode1, 0x36}, |
| 256 | {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x1a}, |
| 257 | {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, |
| 258 | {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x14}, |
| 259 | {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, |
| 260 | {&qserdes_com_reg_layout->com_lock_cmp1_mode1, 0x34}, |
| 261 | {&qserdes_com_reg_layout->com_lock_cmp2_mode1, 0x82}, |
| 262 | {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, |
| 263 | {&qserdes_com_reg_layout->com_dec_start_mode1, 0x82}, |
| 264 | {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, |
| 265 | {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, |
| 266 | {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, |
| 267 | {&qserdes_com_reg_layout->com_div_frac_start1_mode1, 0xab}, |
| 268 | {&qserdes_com_reg_layout->com_div_frac_start2_mode1, 0xea}, |
| 269 | {&qserdes_com_reg_layout->com_div_frac_start3_mode1, 0x02}, |
| 270 | {&qserdes_com_reg_layout->com_vco_tune_map, 0x02}, |
| 271 | {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0x24}, |
| 272 | {&qserdes_com_reg_layout->com_vco_tune1_mode1, 0x24}, |
| 273 | {&qserdes_com_reg_layout->com_vco_tune2_mode1, 0x02}, |
| 274 | {&qserdes_com_reg_layout->com_hsclk_sel, 0x01}, |
| 275 | {&qserdes_com_reg_layout->com_coreclk_div_mode1, 0x08}, |
| 276 | {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode0, 0xca}, |
| 277 | {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode0, 0x1e}, |
| 278 | {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode1, 0xca}, |
| 279 | {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode1, 0x1e}, |
| 280 | {&qserdes_com_reg_layout->com_bin_vcocal_hsclk_sel, 0x11}, |
| 281 | }; |
| 282 | |
| 283 | static const struct qmp_phy_init_tbl qmp_v4_usb3_tx_tbl[] = { |
| 284 | {&qserdes_tx_reg_layout->tx_res_code_lane_tx, 0x60}, |
| 285 | {&qserdes_tx_reg_layout->tx_res_code_lane_rx, 0x60}, |
| 286 | {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x11}, |
| 287 | {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x02}, |
| 288 | {&qserdes_tx_reg_layout->tx_lane_mode_1, 0xd5}, |
| 289 | {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, |
| 290 | {&qserdes_tx_reg_layout->tx_pi_qec_ctrl, 0x40}, |
| 291 | }; |
| 292 | |
| 293 | static const struct qmp_phy_init_tbl qmp_v4_usb3_rx_tbl[] = { |
| 294 | {&qserdes_rx_reg_layout->rx_ucdr_so_gain, 0x06}, |
| 295 | {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x2f}, |
| 296 | {&qserdes_rx_reg_layout->rx_ucdr_so_saturation_and_enable, 0x7f}, |
| 297 | {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_low, 0xff}, |
| 298 | {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_high, 0x0f}, |
| 299 | {&qserdes_rx_reg_layout->rx_ucdr_pi_controls, 0x99}, |
| 300 | {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh1, 0x04}, |
| 301 | {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh2, 0x08}, |
| 302 | {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain1, 0x05}, |
| 303 | {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain2, 0x05}, |
| 304 | {&qserdes_rx_reg_layout->rx_vga_cal_cntrl1, 0x54}, |
| 305 | {&qserdes_rx_reg_layout->rx_vga_cal_cntrl2, 0x0c}, |
| 306 | {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl2, 0x0f}, |
| 307 | {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl3, 0x4a}, |
| 308 | {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl4, 0x0a}, |
| 309 | {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_low, 0xc0}, |
| 310 | {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_high, 0x00}, |
| 311 | {&qserdes_rx_reg_layout->rx_rx_eq_offset_adaptor_cntrl1, 0x77}, |
| 312 | {&qserdes_rx_reg_layout->rx_sigdet_cntrl, 0x04}, |
| 313 | {&qserdes_rx_reg_layout->rx_sigdet_deglitch_cntrl, 0x0e}, |
| 314 | {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0xff}, |
| 315 | {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0x7f}, |
| 316 | {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0x7f}, |
| 317 | {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0xff}, |
| 318 | {&qserdes_rx_reg_layout->rx_rx_mode_00_high2, 0x7f}, |
| 319 | {&qserdes_rx_reg_layout->rx_rx_mode_00_high3, 0x7f}, |
| 320 | {&qserdes_rx_reg_layout->rx_rx_mode_00_high4, 0x97}, |
| 321 | {&qserdes_rx_reg_layout->rx_rx_mode_01_low, 0xdc}, |
| 322 | {&qserdes_rx_reg_layout->rx_rx_mode_01_high, 0xdc}, |
| 323 | {&qserdes_rx_reg_layout->rx_rx_mode_01_high2, 0x5c}, |
| 324 | {&qserdes_rx_reg_layout->rx_rx_mode_01_high3, 0x7b}, |
| 325 | {&qserdes_rx_reg_layout->rx_rx_mode_01_high4, 0xb4}, |
| 326 | {&qserdes_rx_reg_layout->rx_dfe_en_timer, 0x04}, |
| 327 | {&qserdes_rx_reg_layout->rx_dfe_ctle_post_cal_offset, 0x38}, |
| 328 | {&qserdes_rx_reg_layout->rx_aux_data_tcoarse_tfine, 0xa0}, |
| 329 | {&qserdes_rx_reg_layout->rx_dcc_ctrl1, 0x0c}, |
| 330 | {&qserdes_rx_reg_layout->rx_gm_cal, 0x1f}, |
| 331 | {&qserdes_rx_reg_layout->rx_vth_code, 0x10}, |
| 332 | }; |
| 333 | |
| 334 | static const struct qmp_phy_init_tbl qmp_v4_usb3_pcs_tbl[] = { |
| 335 | {&pcs_reg_layout->pcs_lock_detect_config1, 0xd0}, |
| 336 | {&pcs_reg_layout->pcs_lock_detect_config2, 0x07}, |
| 337 | {&pcs_reg_layout->pcs_lock_detect_config3, 0x20}, |
| 338 | {&pcs_reg_layout->pcs_lock_detect_config6, 0x13}, |
| 339 | {&pcs_reg_layout->pcs_refgen_req_config1, 0x21}, |
| 340 | {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xa9}, |
| 341 | {&pcs_reg_layout->pcs_cdr_reset_time, 0x0a}, |
| 342 | {&pcs_reg_layout->pcs_align_detect_config1, 0x88}, |
| 343 | {&pcs_reg_layout->pcs_align_detect_config2, 0x13}, |
| 344 | {&pcs_reg_layout->pcs_pcs_tx_rx_config, 0x0c}, |
| 345 | {&pcs_reg_layout->pcs_eq_config1, 0x4b}, |
| 346 | {&pcs_reg_layout->pcs_eq_config5, 0x10}, |
| 347 | {&pcs_reg_layout->pcs_usb3_lfps_det_high_count_val, 0xf8}, |
| 348 | {&pcs_reg_layout->pcs_usb3_rxeqtraining_dfe_time_s2, 0x07}, |
| 349 | }; |
| 350 | |
| 351 | struct ss_usb_phy_reg qmp_v4_usb_phy = { |
| 352 | .serdes_tbl = qmp_v4_usb3_serdes_tbl, |
| 353 | .serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_serdes_tbl), |
| 354 | .tx_tbl = qmp_v4_usb3_tx_tbl, |
| 355 | .tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_tx_tbl), |
| 356 | .rx_tbl = qmp_v4_usb3_rx_tbl, |
| 357 | .rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_rx_tbl), |
| 358 | .pcs_tbl = qmp_v4_usb3_pcs_tbl, |
| 359 | .pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_tbl), |
| 360 | .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, |
| 361 | }; |
| 362 | |
| 363 | static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], |
| 364 | int num) |
| 365 | { |
| 366 | int i; |
| 367 | const struct qmp_phy_init_tbl *t = tbl; |
| 368 | |
| 369 | if (!t) |
| 370 | return; |
| 371 | |
| 372 | for (i = 0; i < num; i++, t++) |
| 373 | write32(t->address, t->val); |
| 374 | } |
| 375 | |
| 376 | void ss_qmp_phy_init(void) |
| 377 | { |
| 378 | struct ss_usb_phy_reg *ss_phy_reg; |
| 379 | |
| 380 | ss_phy_reg = &qmp_v4_usb_phy; |
| 381 | |
| 382 | /* power up USB3 PHY */ |
| 383 | write32(&ss_phy_reg->qmp_pcs_reg->pcs_power_down_control, 0x01); |
| 384 | |
| 385 | /* Serdes configuration */ |
| 386 | qcom_qmp_phy_configure(ss_phy_reg->serdes_tbl, |
| 387 | ss_phy_reg->serdes_tbl_num); |
| 388 | /* Tx, Rx, and PCS configurations */ |
| 389 | qcom_qmp_phy_configure(ss_phy_reg->tx_tbl, ss_phy_reg->tx_tbl_num); |
| 390 | qcom_qmp_phy_configure(ss_phy_reg->rx_tbl, ss_phy_reg->rx_tbl_num); |
| 391 | qcom_qmp_phy_configure(ss_phy_reg->pcs_tbl, ss_phy_reg->pcs_tbl_num); |
| 392 | |
| 393 | /* perform software reset of PCS/Serdes */ |
| 394 | write32(&ss_phy_reg->qmp_pcs_reg->pcs_sw_reset, 0x00); |
| 395 | /* start PCS/Serdes to operation mode */ |
| 396 | write32(&ss_phy_reg->qmp_pcs_reg->pcs_start_control, 0x03); |
| 397 | |
| 398 | /* |
| 399 | * Wait for PHY initialization to be done |
| 400 | * PCS_STATUS: wait for 1ms for PHY STATUS; |
| 401 | * SW can continuously check for PHYSTATUS = 1.b0. |
| 402 | */ |
| 403 | long lock_us = wait_us(10000, |
| 404 | !(read32(&ss_phy_reg->qmp_pcs_reg->pcs_ready_status) & |
| 405 | USB3_PCS_PHYSTATUS)); |
| 406 | if (!lock_us) |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 407 | printk(BIOS_ERR, "QMP PHY PLL LOCK fails:\n"); |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 408 | else |
| 409 | printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", |
| 410 | lock_us); |
| 411 | } |