Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 2 | |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 3 | #include <timer.h> |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 4 | #include <soc/usb/qmp_usb_phy.h> |
| 5 | #include <soc/addressmap.h> |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 6 | |
| 7 | /* Only for QMP V3 PHY - QSERDES COM registers */ |
| 8 | struct usb3_phy_qserdes_com_reg_layout { |
| 9 | u8 _reserved1[16]; |
| 10 | u32 com_ssc_en_center; |
| 11 | u32 com_ssc_adj_per1; |
| 12 | u32 com_ssc_adj_per2; |
| 13 | u32 com_ssc_per1; |
| 14 | u32 com_ssc_per2; |
| 15 | u32 com_ssc_step_size1; |
| 16 | u32 com_ssc_step_size2; |
| 17 | u8 _reserved2[8]; |
| 18 | u32 com_bias_en_clkbuflr_en; |
| 19 | u32 com_sys_clk_enable1; |
| 20 | u32 com_sys_clk_ctrl; |
| 21 | u32 com_sysclk_buf_enable; |
| 22 | u32 com_pll_en; |
| 23 | u32 com_pll_ivco; |
| 24 | u8 _reserved3[20]; |
| 25 | u32 com_cp_ctrl_mode0; |
| 26 | u8 _reserved4[4]; |
| 27 | u32 com_pll_rctrl_mode0; |
| 28 | u8 _reserved5[4]; |
| 29 | u32 com_pll_cctrl_mode0; |
| 30 | u8 _reserved6[12]; |
| 31 | u32 com_sysclk_en_sel; |
| 32 | u8 _reserved7[8]; |
| 33 | u32 com_resetsm_ctrl2; |
| 34 | u32 com_lock_cmp_en; |
| 35 | u32 com_lock_cmp_cfg; |
| 36 | u32 com_lock_cmp1_mode0; |
| 37 | u32 com_lock_cmp2_mode0; |
| 38 | u32 com_lock_cmp3_mode0; |
| 39 | u8 _reserved8[12]; |
| 40 | u32 com_dec_start_mode0; |
| 41 | u8 _reserved9[4]; |
| 42 | u32 com_div_frac_start1_mode0; |
| 43 | u32 com_div_frac_start2_mode0; |
| 44 | u32 com_div_frac_start3_mode0; |
| 45 | u8 _reserved10[20]; |
| 46 | u32 com_integloop_gain0_mode0; |
| 47 | u32 com_integloop_gain1_mode0; |
| 48 | u8 _reserved11[16]; |
| 49 | u32 com_vco_tune_map; |
| 50 | u32 com_vco_tune1_mode0; |
| 51 | u32 com_vco_tune2_mode0; |
| 52 | u8 _reserved12[60]; |
| 53 | u32 com_clk_select; |
| 54 | u32 com_hsclk_sel; |
| 55 | u8 _reserved13[8]; |
| 56 | u32 com_coreclk_div_mode0; |
| 57 | u8 _reserved14[8]; |
| 58 | u32 com_core_clk_en; |
| 59 | u32 com_c_ready_status; |
| 60 | u32 com_cmn_config; |
| 61 | u32 com_cmn_rate_override; |
| 62 | u32 com_svs_mode_clk_sel; |
| 63 | }; |
| 64 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); |
| 65 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); |
| 66 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); |
| 67 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); |
| 68 | check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); |
| 69 | check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); |
| 70 | check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); |
| 71 | check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); |
| 72 | check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); |
| 73 | check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); |
| 74 | check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); |
| 75 | check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); |
| 76 | check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); |
| 77 | check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); |
| 78 | check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); |
| 79 | check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); |
| 80 | check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); |
| 81 | check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); |
| 82 | |
| 83 | /* Only for QMP V3 PHY - TX registers */ |
| 84 | struct usb3_phy_qserdes_tx_reg_layout { |
| 85 | u8 _reserved1[68]; |
| 86 | u32 tx_res_code_lane_offset_tx; |
| 87 | u32 tx_res_code_lane_offset_rx; |
| 88 | u8 _reserved2[20]; |
| 89 | u32 tx_highz_drvr_en; |
| 90 | u8 _reserved3[40]; |
| 91 | u32 tx_lane_mode_1; |
| 92 | u8 _reserved4[20]; |
| 93 | u32 tx_rcv_detect_lvl_2; |
| 94 | }; |
| 95 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); |
| 96 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); |
| 97 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); |
| 98 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); |
| 99 | check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); |
| 100 | |
| 101 | /* Only for QMP V3 PHY - RX registers */ |
| 102 | struct usb3_phy_qserdes_rx_reg_layout { |
| 103 | u8 _reserved1[8]; |
| 104 | u32 rx_ucdr_fo_gain; |
| 105 | u32 rx_ucdr_so_gain_half; |
| 106 | u8 _reserved2[32]; |
| 107 | u32 rx_ucdr_fastlock_fo_gain; |
| 108 | u32 rx_ucdr_so_saturtn_and_en; |
| 109 | u8 _reserved3[12]; |
| 110 | u32 rx_ucdr_pi_cntrls; |
| 111 | u8 _reserved4[120]; |
| 112 | u32 rx_vga_cal_ctrl2; |
| 113 | u8 _reserved5[16]; |
| 114 | u32 rx_rx_equ_adap_ctrl2; |
| 115 | u32 rx_rx_equ_adap_ctrl3; |
| 116 | u32 rx_rx_equ_adap_ctrl4; |
| 117 | u8 _reserved6[24]; |
| 118 | u32 rx_rx_eq_offset_adap_ctrl1; |
| 119 | u32 rx_rx_offset_adap_ctrl2; |
| 120 | u32 rx_sigdet_enables; |
| 121 | u32 rx_sigdet_ctrl; |
| 122 | u8 _reserved7[4]; |
| 123 | u32 rx_sigdet_deglitch_ctrl; |
| 124 | u32 rx_rx_band; |
| 125 | u8 _reserved8[80]; |
| 126 | u32 rx_rx_mode_00; |
| 127 | }; |
| 128 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); |
| 129 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); |
| 130 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); |
| 131 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); |
| 132 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); |
| 133 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); |
| 134 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); |
| 135 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); |
| 136 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); |
| 137 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); |
| 138 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); |
| 139 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); |
| 140 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); |
| 141 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); |
| 142 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); |
| 143 | check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); |
| 144 | |
| 145 | /* Only for QMP V3 PHY - PCS registers */ |
| 146 | struct usb3_phy_pcs_reg_layout { |
| 147 | u32 pcs_sw_reset; |
| 148 | u32 pcs_power_down_control; |
| 149 | u32 pcs_start_control; |
| 150 | u32 pcs_txmgn_v0; |
| 151 | u32 pcs_txmgn_v1; |
| 152 | u32 pcs_txmgn_v2; |
| 153 | u32 pcs_txmgn_v3; |
| 154 | u32 pcs_txmgn_v4; |
| 155 | u32 pcs_txmgn_ls; |
| 156 | u32 pcs_txdeemph_m6db_v0; |
| 157 | u32 pcs_txdeemph_m3p5db_v0; |
| 158 | u32 pcs_txdeemph_m6db_v1; |
| 159 | u32 pcs_txdeemph_m3p5db_v1; |
| 160 | u32 pcs_txdeemph_m6db_v2; |
| 161 | u32 pcs_txdeemph_m3p5db_v2; |
| 162 | u32 pcs_txdeemph_m6db_v3; |
| 163 | u32 pcs_txdeemph_m3p5db_v3; |
| 164 | u32 pcs_txdeemph_m6db_v4; |
| 165 | u32 pcs_txdeemph_m3p5db_v4; |
| 166 | u32 pcs_txdeemph_m6db_ls; |
| 167 | u32 pcs_txdeemph_m3p5db_ls; |
| 168 | u8 _reserved1[8]; |
| 169 | u32 pcs_rate_slew_cntrl; |
| 170 | u8 _reserved2[4]; |
| 171 | u32 pcs_power_state_config2; |
| 172 | u8 _reserved3[8]; |
| 173 | u32 pcs_rcvr_dtct_dly_p1u2_l; |
| 174 | u32 pcs_rcvr_dtct_dly_p1u2_h; |
| 175 | u32 pcs_rcvr_dtct_dly_u3_l; |
| 176 | u32 pcs_rcvr_dtct_dly_u3_h; |
| 177 | u32 pcs_lock_detect_config1; |
| 178 | u32 pcs_lock_detect_config2; |
| 179 | u32 pcs_lock_detect_config3; |
| 180 | u32 pcs_tsync_rsync_time; |
| 181 | u8 _reserved4[16]; |
| 182 | u32 pcs_pwrup_reset_dly_time_auxclk; |
| 183 | u8 _reserved5[12]; |
| 184 | u32 pcs_lfps_ecstart_eqtlock; |
| 185 | u8 _reserved6[4]; |
| 186 | u32 pcs_rxeqtraining_wait_time; |
| 187 | u32 pcs_rxeqtraining_run_time; |
| 188 | u8 _reserved7[4]; |
| 189 | u32 pcs_fll_ctrl1; |
| 190 | u32 pcs_fll_ctrl2; |
| 191 | u32 pcs_fll_cnt_val_l; |
| 192 | u32 pcs_fll_cnt_val_h_tol; |
| 193 | u32 pcs_fll_man_code; |
| 194 | u32 pcs_autonomous_mode_ctrl; |
| 195 | u8 _reserved8[152]; |
| 196 | u32 pcs_ready_status; |
| 197 | u8 _reserved9[96]; |
| 198 | u32 pcs_rx_sigdet_lvl; |
| 199 | u8 _reserved10[48]; |
| 200 | u32 pcs_refgen_req_config1; |
| 201 | u32 pcs_refgen_req_config2; |
| 202 | }; |
| 203 | check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); |
| 204 | check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); |
| 205 | check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); |
| 206 | check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); |
| 207 | check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); |
| 208 | check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); |
| 209 | check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); |
| 210 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); |
| 211 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); |
| 212 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); |
| 213 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); |
| 214 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); |
| 215 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); |
| 216 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); |
| 217 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); |
| 218 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); |
| 219 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); |
| 220 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); |
| 221 | check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); |
| 222 | check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); |
| 223 | check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); |
| 224 | check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); |
| 225 | check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); |
| 226 | check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); |
| 227 | check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); |
| 228 | check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); |
| 229 | check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); |
| 230 | check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); |
| 231 | check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); |
| 232 | check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); |
| 233 | check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); |
| 234 | check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); |
| 235 | check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); |
| 236 | check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); |
| 237 | |
| 238 | static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = |
| 239 | (void *)QMP_PHY_QSERDES_COM_REG_BASE; |
| 240 | static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = |
| 241 | (void *)QMP_PHY_QSERDES_TX_REG_BASE; |
| 242 | static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = |
| 243 | (void *)QMP_PHY_QSERDES_RX_REG_BASE; |
| 244 | static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = |
| 245 | (void *)QMP_PHY_PCS_REG_BASE; |
| 246 | |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 247 | |
| 248 | static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { |
| 249 | {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, |
| 250 | {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, |
| 251 | {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, |
| 252 | {&qserdes_com_reg_layout->com_clk_select, 0x30}, |
| 253 | {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, |
| 254 | {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, |
| 255 | {&qserdes_com_reg_layout->com_cmn_config, 0x16}, |
| 256 | {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, |
| 257 | {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, |
| 258 | {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, |
| 259 | {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, |
| 260 | {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, |
| 261 | {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, |
| 262 | {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, |
| 263 | {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, |
| 264 | {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, |
| 265 | {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, |
| 266 | {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, |
| 267 | {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, |
| 268 | {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, |
| 269 | {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, |
| 270 | {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, |
| 271 | {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, |
| 272 | {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, |
| 273 | {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, |
| 274 | {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, |
| 275 | {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, |
| 276 | {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, |
| 277 | {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, |
| 278 | {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, |
| 279 | {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, |
| 280 | {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, |
| 281 | {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, |
| 282 | {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, |
| 283 | {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, |
| 284 | {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, |
| 285 | }; |
| 286 | |
| 287 | static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { |
| 288 | {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, |
| 289 | {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, |
| 290 | {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, |
| 291 | {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, |
| 292 | {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, |
| 293 | }; |
| 294 | |
| 295 | static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { |
| 296 | {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, |
| 297 | {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, |
| 298 | {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, |
| 299 | {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, |
| 300 | {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, |
| 301 | {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, |
| 302 | {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, |
| 303 | {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, |
| 304 | {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, |
| 305 | {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, |
| 306 | {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, |
| 307 | {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, |
| 308 | {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, |
| 309 | }; |
| 310 | |
| 311 | static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { |
| 312 | /* FLL settings */ |
| 313 | {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, |
| 314 | {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, |
| 315 | {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, |
| 316 | {&pcs_reg_layout->pcs_fll_man_code, 0x40}, |
| 317 | {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, |
| 318 | |
| 319 | /* Lock Det settings */ |
| 320 | {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, |
| 321 | {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, |
| 322 | {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, |
| 323 | {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, |
| 324 | |
| 325 | {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, |
| 326 | {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, |
| 327 | {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, |
| 328 | {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, |
| 329 | {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, |
| 330 | {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, |
| 331 | {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, |
| 332 | {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, |
| 333 | {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, |
| 334 | {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, |
| 335 | {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, |
| 336 | {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, |
| 337 | {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, |
| 338 | {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, |
| 339 | {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, |
| 340 | {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, |
| 341 | {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, |
| 342 | {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, |
| 343 | {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, |
| 344 | {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, |
| 345 | {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, |
| 346 | {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, |
| 347 | {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, |
| 348 | {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, |
| 349 | {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, |
| 350 | {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, |
| 351 | {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, |
| 352 | {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, |
| 353 | {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, |
| 354 | }; |
| 355 | |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 356 | struct ss_usb_phy_reg qmp_v3_usb_phy = { |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 357 | .serdes_tbl = qmp_v3_usb3_serdes_tbl, |
| 358 | .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), |
| 359 | .tx_tbl = qmp_v3_usb3_tx_tbl, |
| 360 | .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), |
| 361 | .rx_tbl = qmp_v3_usb3_rx_tbl, |
| 362 | .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), |
| 363 | .pcs_tbl = qmp_v3_usb3_pcs_tbl, |
| 364 | .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), |
| 365 | .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 366 | }; |
| 367 | |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 368 | static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], |
| 369 | int num) |
| 370 | { |
| 371 | int i; |
| 372 | const struct qmp_phy_init_tbl *t = tbl; |
| 373 | |
| 374 | if (!t) |
| 375 | return; |
| 376 | |
| 377 | for (i = 0; i < num; i++, t++) |
| 378 | write32(t->address, t->val); |
| 379 | } |
| 380 | |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 381 | void ss_qmp_phy_init(void) |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 382 | { |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 383 | struct ss_usb_phy_reg *ss_phy_reg; |
| 384 | |
| 385 | ss_phy_reg = &qmp_v3_usb_phy; |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 386 | /* power up USB3 PHY */ |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 387 | write32(&ss_phy_reg->qmp_pcs_reg->pcs_power_down_control, 0x01); |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 388 | |
| 389 | /* Serdes configuration */ |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 390 | qcom_qmp_phy_configure(ss_phy_reg->serdes_tbl, |
| 391 | ss_phy_reg->serdes_tbl_num); |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 392 | /* Tx, Rx, and PCS configurations */ |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 393 | qcom_qmp_phy_configure(ss_phy_reg->tx_tbl, ss_phy_reg->tx_tbl_num); |
| 394 | qcom_qmp_phy_configure(ss_phy_reg->rx_tbl, ss_phy_reg->rx_tbl_num); |
| 395 | qcom_qmp_phy_configure(ss_phy_reg->pcs_tbl, ss_phy_reg->pcs_tbl_num); |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 396 | |
| 397 | /* perform software reset of PCS/Serdes */ |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 398 | write32(&ss_phy_reg->qmp_pcs_reg->pcs_sw_reset, 0x00); |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 399 | /* start PCS/Serdes to operation mode */ |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 400 | write32(&ss_phy_reg->qmp_pcs_reg->pcs_start_control, 0x03); |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 401 | |
| 402 | /* |
| 403 | * Wait for PHY initialization to be done |
| 404 | * PCS_STATUS: wait for 1ms for PHY STATUS; |
| 405 | * SW can continuously check for PHYSTATUS = 1.b0. |
| 406 | */ |
Sandeep Maheswaram | 6c2b860 | 2021-07-05 11:11:48 +0530 | [diff] [blame] | 407 | long lock_us = wait_us(10000, |
| 408 | !(read32(&ss_phy_reg->qmp_pcs_reg->pcs_ready_status) & |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 409 | USB3_PCS_PHYSTATUS)); |
| 410 | if (!lock_us) |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 411 | printk(BIOS_ERR, "QMP PHY PLL LOCK fails:\n"); |
T Michael Turney | 050be72 | 2019-10-22 06:25:09 -0700 | [diff] [blame] | 412 | else |
| 413 | printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", |
| 414 | lock_us); |
| 415 | } |