Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 3 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include "me.h" |
| 6 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | /* HFS1[3:0] Current Working State Values */ |
| 8 | static const char *me_cws_values[] = { |
| 9 | [ME_HFS_CWS_RESET] = "Reset", |
| 10 | [ME_HFS_CWS_INIT] = "Initializing", |
| 11 | [ME_HFS_CWS_REC] = "Recovery", |
| 12 | [ME_HFS_CWS_NORMAL] = "Normal", |
| 13 | [ME_HFS_CWS_WAIT] = "Platform Disable Wait", |
| 14 | [ME_HFS_CWS_TRANS] = "OP State Transition", |
| 15 | [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" |
| 16 | }; |
| 17 | |
| 18 | /* HFS1[8:6] Current Operation State Values */ |
| 19 | static const char *me_opstate_values[] = { |
| 20 | [ME_HFS_STATE_PREBOOT] = "Preboot", |
| 21 | [ME_HFS_STATE_M0_UMA] = "M0 with UMA", |
| 22 | [ME_HFS_STATE_M3] = "M3 without UMA", |
| 23 | [ME_HFS_STATE_M0] = "M0 without UMA", |
| 24 | [ME_HFS_STATE_BRINGUP] = "Bring up", |
| 25 | [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" |
| 26 | }; |
| 27 | |
| 28 | /* HFS[19:16] Current Operation Mode Values */ |
| 29 | static const char *me_opmode_values[] = { |
| 30 | [ME_HFS_MODE_NORMAL] = "Normal", |
| 31 | [ME_HFS_MODE_DEBUG] = "Debug", |
| 32 | [ME_HFS_MODE_DIS] = "Soft Temporary Disable", |
| 33 | [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", |
| 34 | [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" |
| 35 | }; |
| 36 | |
| 37 | /* HFS[15:12] Error Code Values */ |
| 38 | static const char *me_error_values[] = { |
| 39 | [ME_HFS_ERROR_NONE] = "No Error", |
| 40 | [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", |
| 41 | [ME_HFS_ERROR_IMAGE] = "Image Failure", |
| 42 | [ME_HFS_ERROR_DEBUG] = "Debug Failure" |
| 43 | }; |
| 44 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 45 | /* HFS2[31:28] ME Progress Code */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 46 | static const char *me_progress_values[] = { |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 47 | [ME_HFS2_PHASE_ROM] = "ROM Phase", |
| 48 | [ME_HFS2_PHASE_BUP] = "BUP Phase", |
| 49 | [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", |
| 50 | [ME_HFS2_PHASE_POLICY] = "Policy Module", |
| 51 | [ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading", |
| 52 | [ME_HFS2_PHASE_UNKNOWN] = "Unknown", |
| 53 | [ME_HFS2_PHASE_HOST_COMM] = "Host Communication" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 54 | }; |
| 55 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 56 | /* HFS2[27:24] Power Management Event */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 57 | static const char *me_pmevent_values[] = { |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 58 | [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", |
| 59 | [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", |
| 60 | [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", |
| 61 | [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", |
| 62 | [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", |
| 63 | [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", |
| 64 | [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", |
| 65 | [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3", |
| 66 | [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0", |
| 67 | [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", |
| 68 | [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", |
| 69 | [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", |
| 70 | [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | /* Progress Code 0 states */ |
| 74 | static const char *me_progress_rom_values[] = { |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 75 | [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", |
| 76 | [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | }; |
| 78 | |
| 79 | /* Progress Code 1 states */ |
| 80 | static const char *me_progress_bup_values[] = { |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 81 | [ME_HFS2_STATE_BUP_INIT] = "Initialization starts", |
| 82 | [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event", |
| 83 | [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process", |
| 84 | [ME_HFS2_STATE_BUP_VSCC_ERR] = "Error reading/matching the VSCC table in the descriptor", |
| 85 | [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED", |
| 86 | [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK", |
| 87 | [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = "Possibly handle BUP manufacturing override strap", |
| 88 | [ME_HFS2_STATE_BUP_M3] = "Bringup in M3", |
| 89 | [ME_HFS2_STATE_BUP_M0] = "Bringup in M0", |
| 90 | [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error", |
| 91 | [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error", |
Aaron Durbin | 569c653 | 2012-12-11 17:17:38 -0600 | [diff] [blame] | 92 | [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = "Host error - CPU reset timeout, DID timeout, memory missing", |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 93 | [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load", |
| 94 | [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC", |
| 95 | [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message", |
| 96 | [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure", |
| 97 | [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error", |
| 98 | [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA", |
| 99 | [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error", |
| 100 | [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS", |
| 101 | [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error", |
| 102 | [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0", |
| 103 | [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error", |
| 104 | [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable", |
| 105 | [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | /* Progress Code 3 states */ |
| 109 | static const char *me_progress_policy_values[] = { |
Angel Pons | e91af4d | 2020-05-07 00:39:50 +0200 | [diff] [blame^] | 110 | [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module", |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 111 | [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry", |
| 112 | [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry", |
| 113 | [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry", |
| 114 | [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry", |
| 115 | [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry", |
| 116 | [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry", |
| 117 | [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake", |
| 118 | [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch", |
| 119 | [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done", |
| 120 | [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] = "VSCC Data not found for flash device", |
| 121 | [ME_HFS2_STATE_POLICY_VSCC_INVALID] = "VSCC Table is not valid", |
| 122 | [ME_HFS2_STATE_POLICY_FPB_ERR] = "Flash Partition Boundary is outside address space", |
| 123 | [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region", |
| 124 | [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 125 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 127 | void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 128 | { |
Kyösti Mälkki | c86fc8e | 2019-11-06 06:32:27 +0200 | [diff] [blame] | 129 | if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) |
| 130 | return; |
| 131 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | /* Check Current States */ |
| 133 | printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", |
| 134 | hfs->fpt_bad ? "BAD" : "OK"); |
| 135 | printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", |
| 136 | hfs->ft_bup_ld_flr ? "YES" : "NO"); |
| 137 | printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", |
| 138 | hfs->fw_init_complete ? "YES" : "NO"); |
| 139 | printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", |
| 140 | hfs->mfg_mode ? "YES" : "NO"); |
| 141 | printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", |
| 142 | hfs->boot_options_present ? "YES" : "NO"); |
| 143 | printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", |
| 144 | hfs->update_in_progress ? "YES" : "NO"); |
| 145 | printk(BIOS_DEBUG, "ME: Current Working State : %s\n", |
| 146 | me_cws_values[hfs->working_state]); |
| 147 | printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", |
| 148 | me_opstate_values[hfs->operation_state]); |
| 149 | printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", |
| 150 | me_opmode_values[hfs->operation_mode]); |
| 151 | printk(BIOS_DEBUG, "ME: Error Code : %s\n", |
| 152 | me_error_values[hfs->error_code]); |
| 153 | printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 154 | me_progress_values[hfs2->progress_code]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 155 | printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 156 | me_pmevent_values[hfs2->current_pmevent]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 157 | |
| 158 | printk(BIOS_DEBUG, "ME: Progress Phase State : "); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 159 | switch (hfs2->progress_code) { |
| 160 | case ME_HFS2_PHASE_ROM: /* ROM Phase */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 161 | printk(BIOS_DEBUG, "%s", |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 162 | me_progress_rom_values[hfs2->current_state]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 163 | break; |
| 164 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 165 | case ME_HFS2_PHASE_BUP: /* Bringup Phase */ |
| 166 | if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) |
| 167 | && me_progress_bup_values[hfs2->current_state]) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 168 | printk(BIOS_DEBUG, "%s", |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 169 | me_progress_bup_values[hfs2->current_state]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 170 | else |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 171 | printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 172 | break; |
| 173 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 174 | case ME_HFS2_PHASE_POLICY: /* Policy Module Phase */ |
| 175 | if (hfs2->current_state < ARRAY_SIZE(me_progress_policy_values) |
| 176 | && me_progress_policy_values[hfs2->current_state]) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 177 | printk(BIOS_DEBUG, "%s", |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 178 | me_progress_policy_values[hfs2->current_state]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 179 | else |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 180 | printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 181 | break; |
| 182 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 183 | case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ |
| 184 | if (!hfs2->current_state) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 185 | printk(BIOS_DEBUG, "Host communication established"); |
| 186 | else |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 187 | printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 188 | break; |
| 189 | |
| 190 | default: |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 191 | printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x", |
| 192 | hfs2->progress_code, hfs2->current_state); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 193 | } |
| 194 | printk(BIOS_DEBUG, "\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 195 | } |