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review.coreboot.org / coreboot / e8696e1b079454d3f5753564037bd886701da8f1 / . / src / mainboard / amd / birman / Kconfig
blob: 32967b19c8098a0c8d0b7e60261b118ca7d2e065 [file] [log] [blame]
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-only
2
Martin Roth20646cd2023-01-04 21:27:06 -0700[diff] [blame]3if BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_PHOENIX
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]4
5config BOARD_SPECIFIC_OPTIONS
6 def_bool y
Martin Roth86284c22022-10-27 18:15:25 -0600[diff] [blame]7 select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]8 select EC_ACPI
Fred Reitberger997ead62023-02-23 14:09:10 -0500[diff] [blame]9 select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
Fred Reitberger67bc6ab2023-04-06 10:01:23 -0400[diff] [blame]10 select DRIVERS_PCIE_RTD3_DEVICE
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]11 select MAINBOARD_HAS_CHROMEOS
12 select PCIEXP_ASPM
13 select PCIEXP_CLK_PM
14 select PCIEXP_COMMON_CLOCK
15 select PCIEXP_L1_SUB_STATE
Fred Reitberger997ead62023-02-23 14:09:10 -0500[diff] [blame]16 select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
17 select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED
Fred Reitbergere8696e12023-06-23 09:59:18 -0400[diff] [blame^]18 select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]19
20config FMDFILE
Fred Reitberger0ef9d892023-02-08 13:02:42 -0500[diff] [blame]21 default "src/mainboard/amd/birman/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_GLINDA
22 default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX
23 default "src/mainboard/amd/birman/board_glinda.fmd" if BOARD_AMD_BIRMAN_GLINDA
24 default "src/mainboard/amd/birman/board_phoenix.fmd"
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]25
26config MAINBOARD_DIR
27 default "amd/birman"
28
29config MAINBOARD_PART_NUMBER
Martin Roth86284c22022-10-27 18:15:25 -0600[diff] [blame]30 default "Birman_Glinda" if BOARD_AMD_BIRMAN_GLINDA
Martin Roth20646cd2023-01-04 21:27:06 -0700[diff] [blame]31 default "Birman_Phoenix"
Martin Roth86284c22022-10-27 18:15:25 -0600[diff] [blame]32
33config DEVICETREE
34 default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA
Martin Roth20646cd2023-01-04 21:27:06 -0700[diff] [blame]35 default "devicetree_phoenix.cb"
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]36
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]37config BIRMAN_HAVE_MCHP_FW
38 bool "Have Microchip EC firmware?"
39 default n
40
41config BIRMAN_MCHP_SIG_FILE
42 string "Microchip EC signature file"
43 depends on BIRMAN_HAVE_MCHP_FW
44 default "3rdparty/blobs/mainboard/amd/birman/EC_birman_sig.bin"
45 help
46 The EC sig blob is the first 4kBytes of the firmware image.
47 The first 4 bytes form a pointer (with CRC) to where the EC firmware
48 is located
49
Martin Roth2fca0262023-05-10 13:32:29 -0600[diff] [blame]50config AMD_SOC_CONSOLE_UART
51 default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
52
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]53config BIRMAN_MCHP_FW_FILE
54 string "Microchip EC firmware file"
55 depends on BIRMAN_HAVE_MCHP_FW
56 default "3rdparty/blobs/mainboard/amd/birman/EC_birman.bin"
57 help
Fred Reitberger75e720b2022-12-12 10:13:41 -0500[diff] [blame]58 The EC firmware blob is at the EC_BODY FMAP region of the firmware image.
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]59
60config VBOOT
61 select VBOOT_NO_BOARD_SUPPORT
62 select VBOOT_SEPARATE_VERSTAGE
63 select VBOOT_STARTS_IN_BOOTBLOCK
64
65config VBOOT_VBNV_OFFSET
66 hex
67 default 0x2A
68
69config RO_REGION_ONLY
70 string
71 depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
72 # Add the EFS and EC to the RO region only
Martin Roth20646cd2023-01-04 21:27:06 -0700[diff] [blame]73 # This is a birman-specific override of soc/amd/(phoenix | glinda)/Kconfig
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]74 default "apu/amdfw apu/ecfw"
75
76config CHROMEOS
77 # Use default libpayload config
78 select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
79 # We don't have recovery buttons, so we can't manually enable devmode.
80 select GBB_FLAG_FORCE_DEV_SWITCH_ON
81
Fred Reitberger3c8a8c22023-03-23 13:29:01 -0400[diff] [blame]82config ENABLE_EVAL_CARD
83 bool "Enable Eval Card"
84 help
85 Enable the Eval Card PCIe slot
86
87config ENABLE_EVAL_19V
88 bool "Enable 19V rail for Eval Card"
89 depends on ENABLE_EVAL_CARD
90 help
91 Enable the 19V rail for Eval Card PCIe slot
92
93choice
94 prompt "DT SLOT/M.2 SSD1 ENABLE"
95 default ENABLE_DT_SLOT
96 help
97 Either DT slot or M.2 SSD1 can be used, as they are sharing PCIe lanes.
98
99config ENABLE_DT_SLOT
100 bool "Enable DT slot"
101
102config ENABLE_M2_SSD1
103 bool "Enable M.2 SSD1"
104
105config DISABLE_DT_M2
106 bool "Disable both DT and M.2 slot"
107
108endchoice
109
110choice
111 prompt "WLAN/WWAN Selection"
112 default WLAN0_WWAN0
113 help
114 WLAN and WWAN lane configuration
115
116config WLAN0_WWAN0
117 bool "Both WLAN and WWAN Enabled (1 lane each)"
118
119config WLAN01
120 bool "Only WLAN Enabled (2 lanes WLAN, 0 lanes WWAN)"
121
122config WWAN01
123 bool "Only WWAN Enabled (2 lanes WWAN, 0 lanes WLAN)"
124
125endchoice
126
Martin Roth3c963d92022-10-06 16:29:07 -0600[diff] [blame]127if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
128config EFS_SPI_READ_MODE
129 default 3 # Quad IO (1-1-4)
130
131config EFS_SPI_SPEED
132 default 0 # 66MHz
133
134config EFS_SPI_MICRON_FLAG
135 default 0
136
137config NORMAL_READ_SPI_SPEED
138 default 1 # 33MHz
139
140config ALT_SPI_SPEED
141 default 1 # 33MHz
142
143config TPM_SPI_SPEED
144 default 1 # 33MHz
145
146endif # !EM100
147
Martin Roth20646cd2023-01-04 21:27:06 -0700[diff] [blame]148endif # BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_PHOENIX