Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
| 13 | * * Neither the name of The Linux Foundation nor the names of its |
| 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #ifndef __DRIVERS_CLOCK_IPQ806X_LCC_REG_H__ |
| 31 | #define __DRIVERS_CLOCK_IPQ806X_LCC_REG_H__ |
| 32 | |
| 33 | #define MSM_GCC_BASE 0x00900000 |
| 34 | #define MSM_LPASS_LCC_BASE 0x28000000 |
| 35 | |
| 36 | /* GCC APCS Configuration/Control */ |
| 37 | |
| 38 | #define GCC_PLL_APCS_REG 0x34C0 |
| 39 | |
| 40 | #define GCC_PLL_APCS_PLL4_MASK 0x10 |
| 41 | #define GCC_PLL_APCS_PLL4_SHIFT 4 |
| 42 | #define GCC_PLL_APCS_PLL4_ENABLE (1 << GCC_PLL_APCS_PLL4_SHIFT) |
| 43 | |
| 44 | /* LCC PLL0 Configuration/Control */ |
| 45 | |
| 46 | #define LCC_PLL0_MODE_REG 0x00 |
| 47 | #define LCC_PLL0_L_REG 0x04 |
| 48 | #define LCC_PLL0_M_REG 0x08 |
| 49 | #define LCC_PLL0_N_REG 0x0C |
| 50 | #define LCC_PLL0_CFG_REG 0x14 |
| 51 | #define LCC_PLL0_STAT_REG 0x18 |
| 52 | |
| 53 | #define LCC_PLL0_MODE_FSM_RESET_MASK 0x200000 |
| 54 | #define LCC_PLL0_MODE_FSM_RESET_SHIFT 21 |
| 55 | #define LCC_PLL0_MODE_FSM_RESET_ASSERT (1 << LCC_PLL0_MODE_FSM_RESET_SHIFT) |
| 56 | |
| 57 | #define LCC_PLL0_MODE_FSM_VOTE_MASK 0x100000 |
| 58 | #define LCC_PLL0_MODE_FSM_VOTE_SHIFT 20 |
| 59 | #define LCC_PLL0_MODE_FSM_VOTE_ENABLE (1 << LCC_PLL0_MODE_FSM_VOTE_SHIFT) |
| 60 | |
| 61 | #define LCC_PLL0_MODE_BIAS_CNT_MASK 0xFC000 |
| 62 | #define LCC_PLL0_MODE_BIAS_CNT_SHIFT 14 |
| 63 | |
| 64 | #define LCC_PLL0_MODE_LOCK_CNT_MASK 0x3F00 |
| 65 | #define LCC_PLL0_MODE_LOCK_CNT_SHIFT 8 |
| 66 | |
| 67 | #define LCC_PLL0_MODE_XO_SEL_MASK 0x30 |
| 68 | #define LCC_PLL0_MODE_XO_SEL_SHIFT 4 |
| 69 | #define LCC_PLL0_MODE_XO_SEL_PXO (0 << LCC_PLL0_MODE_XO_SEL_SHIFT) |
| 70 | #define LCC_PLL0_MODE_XO_SEL_MXO (1 << LCC_PLL0_MODE_XO_SEL_SHIFT) |
| 71 | #define LCC_PLL0_MODE_XO_SEL_CXO (2 << LCC_PLL0_MODE_XO_SEL_SHIFT) |
| 72 | |
| 73 | #define LCC_PLL0_MODE_TEST_MASK 0x8 |
| 74 | #define LCC_PLL0_MODE_TEST_SHIFT 3 |
| 75 | #define LCC_PLL0_MODE_TEST_ENABLE (1 << LCC_PLL0_MODE_TEST_SHIFT) |
| 76 | |
| 77 | #define LCC_PLL0_MODE_RESET_MASK 0x4 |
| 78 | #define LCC_PLL0_MODE_RESET_SHIFT 2 |
| 79 | #define LCC_PLL0_MODE_RESET_DEASSERT (1 << LCC_PLL0_MODE_RESET_SHIFT) |
| 80 | |
| 81 | #define LCC_PLL0_MODE_BYPASS_MASK 0x2 |
| 82 | #define LCC_PLL0_MODE_BYPASS_SHIFT 1 |
| 83 | #define LCC_PLL0_MODE_BYPASS_DISABLE (1 << LCC_PLL0_MODE_BYPASS_SHIFT) |
| 84 | |
| 85 | #define LCC_PLL0_MODE_OUTPUT_MASK 0x1 |
| 86 | #define LCC_PLL0_MODE_OUTPUT_SHIFT 0 |
| 87 | #define LCC_PLL0_MODE_OUTPUT_ENABLE (1 << LCC_PLL0_MODE_OUTPUT_SHIFT) |
| 88 | |
| 89 | #define LCC_PLL0_L_MASK 0x3FF |
| 90 | #define LCC_PLL0_L_SHIFT 0 |
| 91 | |
| 92 | #define LCC_PLL0_M_MASK 0x7FFFF |
| 93 | #define LCC_PLL0_M_SHIFT 0 |
| 94 | |
| 95 | #define LCC_PLL0_N_MASK 0x7FFFF |
| 96 | #define LCC_PLL0_N_SHIFT 0 |
| 97 | |
| 98 | #define LCC_PLL0_CFG_LV_MAIN_MASK 0x800000 |
| 99 | #define LCC_PLL0_CFG_LV_MAIN_SHIFT 23 |
| 100 | #define LCC_PLL0_CFG_LV_MAIN_ENABLE (1 << LCC_PLL0_CFG_LV_MAIN_SHIFT) |
| 101 | |
| 102 | #define LCC_PLL0_CFG_FRAC_MASK 0x400000 |
| 103 | #define LCC_PLL0_CFG_FRAC_SHIFT 22 |
| 104 | #define LCC_PLL0_CFG_FRAC_ENABLE (1 << LCC_PLL0_CFG_FRAC_SHIFT) |
| 105 | |
| 106 | #define LCC_PLL0_CFG_POSTDIV_MASK 0x300000 |
| 107 | #define LCC_PLL0_CFG_POSTDIV_SHIFT 20 |
| 108 | #define LCC_PLL0_CFG_POSTDIV_DIV1 (0 << LCC_PLL0_CFG_POSTDIV_SHIFT) |
| 109 | #define LCC_PLL0_CFG_POSTDIV_DIV2 (1 << LCC_PLL0_CFG_POSTDIV_SHIFT) |
| 110 | #define LCC_PLL0_CFG_POSTDIV_DIV4 (2 << LCC_PLL0_CFG_POSTDIV_SHIFT) |
| 111 | |
| 112 | #define LCC_PLL0_CFG_PREDIV_MASK 0x80000 |
| 113 | #define LCC_PLL0_CFG_PREDIV_SHIFT 19 |
| 114 | #define LCC_PLL0_CFG_PREDIV_DIV1 (0 << LCC_PLL0_CFG_PREDIV_SHIFT) |
| 115 | #define LCC_PLL0_CFG_PREDIV_DIV2 (1 << LCC_PLL0_CFG_PREDIV_SHIFT) |
| 116 | |
| 117 | #define LCC_PLL0_CFG_VCO_SEL_MASK 0x30000 |
| 118 | #define LCC_PLL0_CFG_VCO_SEL_SHIFT 16 |
| 119 | #define LCC_PLL0_CFG_VCO_SEL_LOW (0 << LCC_PLL0_CFG_VCO_SEL_SHIFT) |
| 120 | #define LCC_PLL0_CFG_VCO_SEL_MED (1 << LCC_PLL0_CFG_VCO_SEL_SHIFT) |
| 121 | #define LCC_PLL0_CFG_VCO_SEL_HIGH (2 << LCC_PLL0_CFG_VCO_SEL_SHIFT) |
| 122 | |
| 123 | #define LCC_PLL0_STAT_ACTIVE_MASK 0x10000 |
| 124 | #define LCC_PLL0_STAT_ACTIVE_SHIFT 16 |
| 125 | #define LCC_PLL0_STAT_ACTIVE_SET (1 << LCC_PLL0_STAT_ACTIVE_SHIFT) |
| 126 | |
| 127 | #define LCC_PLL0_STAT_NOCLK_MASK 0x1 |
| 128 | #define LCC_PLL0_STAT_NOCLK_SHIFT 0 |
| 129 | #define LCC_PLL0_STAT_NOCLK_SET (1 << LCC_PLL0_STAT_NOCLK_SHIFT) |
| 130 | |
| 131 | /* LCC AHBIX Configuration/Control */ |
| 132 | |
| 133 | #define LCC_AHBIX_NS_REG 0x38 |
| 134 | #define LCC_AHBIX_MD_REG 0x3C |
| 135 | #define LCC_AHBIX_STAT_REG 0x44 |
| 136 | |
| 137 | #define LCC_AHBIX_NS_N_VAL_MASK 0xFF000000 |
| 138 | #define LCC_AHBIX_NS_N_VAL_SHIFT 24 |
| 139 | |
| 140 | #define LCC_AHBIX_NS_CRC_MASK 0x800 |
| 141 | #define LCC_AHBIX_NS_CRC_SHIFT 11 |
| 142 | #define LCC_AHBIX_NS_CRC_ENABLE (1 << LCC_AHBIX_NS_CRC_SHIFT) |
| 143 | |
| 144 | #define LCC_AHBIX_NS_GFM_SEL_MASK 0x400 |
| 145 | #define LCC_AHBIX_NS_GFM_SEL_SHIFT 10 |
| 146 | #define LCC_AHBIX_NS_GFM_SEL_PXO (0 << LCC_AHBIX_NS_GFM_SEL_SHIFT) |
| 147 | #define LCC_AHBIX_NS_GFM_SEL_MNC (1 << LCC_AHBIX_NS_GFM_SEL_SHIFT) |
| 148 | |
| 149 | #define LCC_AHBIX_NS_MNC_CLK_MASK 0x200 |
| 150 | #define LCC_AHBIX_NS_MNC_CLK_SHIFT 9 |
| 151 | #define LCC_AHBIX_NS_MNC_CLK_ENABLE (1 << LCC_AHBIX_NS_MNC_CLK_SHIFT) |
| 152 | |
| 153 | #define LCC_AHBIX_NS_MNC_MASK 0x100 |
| 154 | #define LCC_AHBIX_NS_MNC_SHIFT 8 |
| 155 | #define LCC_AHBIX_NS_MNC_ENABLE (1 << LCC_AHBIX_NS_MNC_SHIFT) |
| 156 | |
| 157 | #define LCC_AHBIX_NS_MNC_RESET_MASK 0x80 |
| 158 | #define LCC_AHBIX_NS_MNC_RESET_SHIFT 7 |
| 159 | #define LCC_AHBIX_NS_MNC_RESET_ASSERT (1 << LCC_AHBIX_NS_MNC_RESET_SHIFT) |
| 160 | |
| 161 | #define LCC_AHBIX_NS_MNC_MODE_MASK 0x60 |
| 162 | #define LCC_AHBIX_NS_MNC_MODE_SHIFT 5 |
| 163 | #define LCC_AHBIX_NS_MNC_MODE_BYPASS (0 << LCC_AHBIX_NS_MNC_MODE_SHIFT) |
| 164 | #define LCC_AHBIX_NS_MNC_MODE_SWALLOW (1 << LCC_AHBIX_NS_MNC_MODE_SHIFT) |
| 165 | #define LCC_AHBIX_NS_MNC_MODE_DUAL (2 << LCC_AHBIX_NS_MNC_MODE_SHIFT) |
| 166 | #define LCC_AHBIX_NS_MNC_MODE_SINGLE (3 << LCC_AHBIX_NS_MNC_MODE_SHIFT) |
| 167 | |
| 168 | #define LCC_AHBIX_NS_PREDIV_MASK 0x18 |
| 169 | #define LCC_AHBIX_NS_PREDIV_SHIFT 3 |
| 170 | #define LCC_AHBIX_NS_PREDIV_BYPASS (0 << LCC_AHBIX_NS_PREDIV_SHIFT) |
| 171 | #define LCC_AHBIX_NS_PREDIV_DIV2 (1 << LCC_AHBIX_NS_PREDIV_SHIFT) |
| 172 | #define LCC_AHBIX_NS_PREDIV_DIV4 (3 << LCC_AHBIX_NS_PREDIV_SHIFT) |
| 173 | |
| 174 | #define LCC_AHBIX_NS_MN_SRC_MASK 0x7 |
| 175 | #define LCC_AHBIX_NS_MN_SRC_SHIFT 0 |
| 176 | #define LCC_AHBIX_NS_MN_SRC_PXO (0 << LCC_AHBIX_NS_MN_SRC_SHIFT) |
| 177 | #define LCC_AHBIX_NS_MN_SRC_CXO (1 << LCC_AHBIX_NS_MN_SRC_SHIFT) |
| 178 | #define LCC_AHBIX_NS_MN_SRC_LPA (2 << LCC_AHBIX_NS_MN_SRC_SHIFT) |
| 179 | #define LCC_AHBIX_NS_MN_SRC_SEC (3 << LCC_AHBIX_NS_MN_SRC_SHIFT) |
| 180 | #define LCC_AHBIX_NS_MN_SRC_CTEST (6 << LCC_AHBIX_NS_MN_SRC_SHIFT) |
| 181 | #define LCC_AHBIX_NS_MN_SRC_PTEST (7 << LCC_AHBIX_NS_MN_SRC_SHIFT) |
| 182 | |
| 183 | #define LCC_AHBIX_MD_M_VAL_MASK 0xFF00 |
| 184 | #define LCC_AHBIX_MD_M_VAL_SHIFT 8 |
| 185 | |
| 186 | #define LCC_AHBIX_MD_NOT_2D_VAL_MASK 0xFF |
| 187 | #define LCC_AHBIX_MD_NOT_2D_VAL_SHIFT 0 |
| 188 | |
| 189 | #define LCC_AHBIX_STAT_AHB_CLK_MASK 0x400 |
| 190 | #define LCC_AHBIX_STAT_AHB_CLK_SHIFT 10 |
| 191 | #define LCC_AHBIX_STAT_AHB_CLK_ON (1 << LCC_AHBIX_STAT_AHB_CLK_SHIFT) |
| 192 | |
| 193 | #define LCC_AHBIX_STAT_AIF_CLK_MASK 0x200 |
| 194 | #define LCC_AHBIX_STAT_AIF_CLK_SHIFT 9 |
| 195 | #define LCC_AHBIX_STAT_AIF_CLK_ON (1 << LCC_AHBIX_STAT_AIF_CLK_SHIFT) |
| 196 | |
| 197 | #define LCC_AHBIX_STAT_FAB2_CLK_MASK 0x40 |
| 198 | #define LCC_AHBIX_STAT_FAB2_CLK_SHIFT 6 |
| 199 | #define LCC_AHBIX_STAT_FAB2_CLK_ON (1 << LCC_AHBIX_STAT_FAB2_CLK_SHIFT) |
| 200 | |
| 201 | #define LCC_AHBIX_STAT_2FAB_CLK_MASK 0x20 |
| 202 | #define LCC_AHBIX_STAT_2FAB_CLK_SHIFT 5 |
| 203 | #define LCC_AHBIX_STAT_2FAB_CLK_ON (1 << LCC_AHBIX_STAT_2FAB_CLK_SHIFT) |
| 204 | |
| 205 | /* LCC MI2S Configuration/Control */ |
| 206 | |
| 207 | #define LCC_MI2S_NS_REG 0x48 |
| 208 | #define LCC_MI2S_MD_REG 0x4C |
| 209 | #define LCC_MI2S_STAT_REG 0x50 |
| 210 | |
| 211 | #define LCC_MI2S_NS_N_VAL_MASK 0xFF000000 |
| 212 | #define LCC_MI2S_NS_N_VAL_SHIFT 24 |
| 213 | |
| 214 | #define LCC_MI2S_NS_RESET_MASK 0x80000 |
| 215 | #define LCC_MI2S_NS_RESET_SHIFT 19 |
| 216 | #define LCC_MI2S_NS_RESET_ASSERT (1 << LCC_MI2S_NS_RESET_SHIFT) |
| 217 | |
| 218 | #define LCC_MI2S_NS_OSR_INV_MASK 0x40000 |
| 219 | #define LCC_MI2S_NS_OSR_INV_SHIFT 18 |
| 220 | #define LCC_MI2S_NS_OSR_INV_ENABLE (1 << LCC_MI2S_NS_OSR_INV_SHIFT) |
| 221 | |
| 222 | #define LCC_MI2S_NS_OSR_CXC_MASK 0x20000 |
| 223 | #define LCC_MI2S_NS_OSR_CXC_SHIFT 17 |
| 224 | #define LCC_MI2S_NS_OSR_CXC_ENABLE (1 << LCC_MI2S_NS_OSR_CXC_SHIFT) |
| 225 | |
| 226 | #define LCC_MI2S_NS_BIT_INV_MASK 0x10000 |
| 227 | #define LCC_MI2S_NS_BIT_INV_SHIFT 16 |
| 228 | #define LCC_MI2S_NS_BIT_INV_ENABLE (1 << LCC_MI2S_NS_BIT_INV_SHIFT) |
| 229 | |
| 230 | #define LCC_MI2S_NS_BIT_CXC_MASK 0x8000 |
| 231 | #define LCC_MI2S_NS_BIT_CXC_SHIFT 15 |
| 232 | #define LCC_MI2S_NS_BIT_CXC_ENABLE (1 << LCC_MI2S_NS_BIT_CXC_SHIFT) |
| 233 | |
| 234 | #define LCC_MI2S_NS_BIT_SRC_MASK 0x4000 |
| 235 | #define LCC_MI2S_NS_BIT_SRC_SHIFT 14 |
| 236 | #define LCC_MI2S_NS_BIT_SRC_MASTER (0 << LCC_MI2S_NS_BIT_SRC_SHIFT) |
| 237 | #define LCC_MI2S_NS_BIT_SRC_SLAVE (1 << LCC_MI2S_NS_BIT_SRC_SHIFT) |
| 238 | |
| 239 | #define LCC_MI2S_NS_BIT_DIV_MASK 0x3C00 |
| 240 | #define LCC_MI2S_NS_BIT_DIV_SHIFT 10 |
| 241 | #define LCC_MI2S_NS_BIT_DIV_BYPASS (0 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 242 | #define LCC_MI2S_NS_BIT_DIV_DIV2 (1 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 243 | #define LCC_MI2S_NS_BIT_DIV_DIV3 (2 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 244 | #define LCC_MI2S_NS_BIT_DIV_DIV4 (3 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 245 | #define LCC_MI2S_NS_BIT_DIV_DIV5 (4 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 246 | #define LCC_MI2S_NS_BIT_DIV_DIV6 (5 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 247 | #define LCC_MI2S_NS_BIT_DIV_DIV7 (6 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 248 | #define LCC_MI2S_NS_BIT_DIV_DIV8 (7 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 249 | #define LCC_MI2S_NS_BIT_DIV_DIV9 (8 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 250 | #define LCC_MI2S_NS_BIT_DIV_DIV10 (9 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 251 | #define LCC_MI2S_NS_BIT_DIV_DIV11 (10 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 252 | #define LCC_MI2S_NS_BIT_DIV_DIV12 (11 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 253 | #define LCC_MI2S_NS_BIT_DIV_DIV13 (12 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 254 | #define LCC_MI2S_NS_BIT_DIV_DIV14 (13 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 255 | #define LCC_MI2S_NS_BIT_DIV_DIV15 (14 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 256 | #define LCC_MI2S_NS_BIT_DIV_DIV16 (15 << LCC_MI2S_NS_BIT_DIV_SHIFT) |
| 257 | |
| 258 | #define LCC_MI2S_NS_MNC_CLK_MASK 0x200 |
| 259 | #define LCC_MI2S_NS_MNC_CLK_SHIFT 9 |
| 260 | #define LCC_MI2S_NS_MNC_CLK_ENABLE (1 << LCC_MI2S_NS_MNC_CLK_SHIFT) |
| 261 | |
| 262 | #define LCC_MI2S_NS_MNC_MASK 0x100 |
| 263 | #define LCC_MI2S_NS_MNC_SHIFT 8 |
| 264 | #define LCC_MI2S_NS_MNC_ENABLE (1 << LCC_MI2S_NS_MNC_SHIFT) |
| 265 | |
| 266 | #define LCC_MI2S_NS_MNC_RESET_MASK 0x80 |
| 267 | #define LCC_MI2S_NS_MNC_RESET_SHIFT 7 |
| 268 | #define LCC_MI2S_NS_MNC_RESET_ASSERT (1 << LCC_MI2S_NS_MNC_RESET_SHIFT) |
| 269 | |
| 270 | #define LCC_MI2S_NS_MNC_MODE_MASK 0x60 |
| 271 | #define LCC_MI2S_NS_MNC_MODE_SHIFT 5 |
| 272 | #define LCC_MI2S_NS_MNC_MODE_BYPASS (0 << LCC_MI2S_NS_MNC_MODE_SHIFT) |
| 273 | #define LCC_MI2S_NS_MNC_MODE_SWALLOW (1 << LCC_MI2S_NS_MNC_MODE_SHIFT) |
| 274 | #define LCC_MI2S_NS_MNC_MODE_DUAL (2 << LCC_MI2S_NS_MNC_MODE_SHIFT) |
| 275 | #define LCC_MI2S_NS_MNC_MODE_SINGLE (3 << LCC_MI2S_NS_MNC_MODE_SHIFT) |
| 276 | |
| 277 | #define LCC_MI2S_NS_PREDIV_MASK 0x18 |
| 278 | #define LCC_MI2S_NS_PREDIV_SHIFT 3 |
| 279 | #define LCC_MI2S_NS_PREDIV_BYPASS (0 << LCC_MI2S_NS_PREDIV_SHIFT) |
| 280 | #define LCC_MI2S_NS_PREDIV_DIV2 (1 << LCC_MI2S_NS_PREDIV_SHIFT) |
| 281 | #define LCC_MI2S_NS_PREDIV_DIV4 (3 << LCC_MI2S_NS_PREDIV_SHIFT) |
| 282 | |
| 283 | #define LCC_MI2S_NS_MN_SRC_MASK 0x7 |
| 284 | #define LCC_MI2S_NS_MN_SRC_SHIFT 0 |
| 285 | #define LCC_MI2S_NS_MN_SRC_PXO (0 << LCC_MI2S_NS_MN_SRC_SHIFT) |
| 286 | #define LCC_MI2S_NS_MN_SRC_CXO (1 << LCC_MI2S_NS_MN_SRC_SHIFT) |
| 287 | #define LCC_MI2S_NS_MN_SRC_LPA (2 << LCC_MI2S_NS_MN_SRC_SHIFT) |
| 288 | #define LCC_MI2S_NS_MN_SRC_SEC (3 << LCC_MI2S_NS_MN_SRC_SHIFT) |
| 289 | #define LCC_MI2S_NS_MN_SRC_CTEST (6 << LCC_MI2S_NS_MN_SRC_SHIFT) |
| 290 | #define LCC_MI2S_NS_MN_SRC_PTEST (7 << LCC_MI2S_NS_MN_SRC_SHIFT) |
| 291 | |
| 292 | #define LCC_MI2S_MD_M_VAL_MASK 0xFF00 |
| 293 | #define LCC_MI2S_MD_M_VAL_SHIFT 8 |
| 294 | |
| 295 | #define LCC_MI2S_MD_NOT_2D_VAL_MASK 0xFF |
| 296 | #define LCC_MI2S_MD_NOT_2D_VAL_SHIFT 0 |
| 297 | |
| 298 | #define LCC_MI2S_STAT_OSR_CLK_MASK 0x2 |
| 299 | #define LCC_MI2S_STAT_OSR_CLK_SHIFT 1 |
| 300 | #define LCC_MI2S_STAT_OSR_CLK_ON (1 << LCC_MI2S_STAT_OSR_CLK_SHIFT) |
| 301 | |
| 302 | #define LCC_MI2S_STAT_BIT_CLK_MASK 0x1 |
| 303 | #define LCC_MI2S_STAT_BIT_CLK_SHIFT 0 |
| 304 | #define LCC_MI2S_STAT_BIT_CLK_ON (1 << LCC_MI2S_STAT_BIT_CLK_SHIFT) |
| 305 | |
| 306 | /* LCC PLL Configuration/Control */ |
| 307 | |
| 308 | #define LCC_PLL_PCLK_REG 0xC4 |
| 309 | #define LCC_PLL_SCLK_REG 0xC8 |
| 310 | |
| 311 | #define LCC_PLL_PCLK_RESET_MASK 0x2 |
| 312 | #define LCC_PLL_PCLK_RESET_SHIFT 1 |
| 313 | #define LCC_PLL_PCLK_RESET_ASSERT (1 << LCC_PLL_PCLK_RESET_SHIFT) |
| 314 | |
| 315 | #define LCC_PLL_PCLK_SRC_MASK 0x1 |
| 316 | #define LCC_PLL_PCLK_SRC_SHIFT 0 |
| 317 | #define LCC_PLL_PCLK_SRC_PXO (0 << LCC_PLL_PCLK_SRC_SHIFT) |
| 318 | #define LCC_PLL_PCLK_SRC_PRI (1 << LCC_PLL_PCLK_SRC_SHIFT) |
| 319 | |
| 320 | #define LCC_PLL_SCLK_RESET_MASK 0x10 |
| 321 | #define LCC_PLL_SCLK_RESET_SHIFT 4 |
| 322 | #define LCC_PLL_SCLK_RESET_ASSERT (1 << LCC_PLL_SCLK_RESET_SHIFT) |
| 323 | |
| 324 | #define LCC_PLL_SCLK_DIV_MASK 0xC |
| 325 | #define LCC_PLL_SCLK_DIV_SHIFT 2 |
| 326 | #define LCC_PLL_SCLK_DIV_BYPASS (0 << LCC_PLL_SCLK_DIV_SHIFT) |
| 327 | #define LCC_PLL_SCLK_DIV_DIV2 (1 << LCC_PLL_SCLK_DIV_SHIFT) |
| 328 | #define LCC_PLL_SCLK_DIV_DIV3 (2 << LCC_PLL_SCLK_DIV_SHIFT) |
| 329 | #define LCC_PLL_SCLK_DIV_DIV4 (3 << LCC_PLL_SCLK_DIV_SHIFT) |
| 330 | |
| 331 | #define LCC_PLL_SCLK_XO_MASK 0x2 |
| 332 | #define LCC_PLL_SCLK_XO_SHIFT 1 |
| 333 | #define LCC_PLL_SCLK_XO_PXO (0 << LCC_PLL_SCLK_XO_SHIFT) |
| 334 | #define LCC_PLL_SCLK_XO_SEC (1 << LCC_PLL_SCLK_XO_SHIFT) |
| 335 | |
| 336 | #define LCC_PLL_SCLK_MUX_MASK 0x1 |
| 337 | #define LCC_PLL_SCLK_MUX_SHIFT 0 |
| 338 | #define LCC_PLL_SCLK_MUX_PLL1 (0 << LCC_PLL_SCLK_MUX_SHIFT) |
| 339 | #define LCC_PLL_SCLK_MUX_PLL0 (1 << LCC_PLL_SCLK_MUX_SHIFT) |
| 340 | |
| 341 | #endif /* __DRIVERS_CLOCK_IPQ806X_LCC_REG_H__ */ |