| Dan Ehrenberg | cb3b0c5a | 2014-10-23 17:46:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012 The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Taken from U-Boot. |
| 5 | */ |
| 6 | #ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_ |
| 7 | #define __SOC_QUALCOMM_IPQ806X_EBI2_H_ |
| 8 | |
| 9 | #define EBI2CR_BASE (0x1A600000) |
| 10 | |
| 11 | struct ebi2cr_regs { |
| 12 | uint32_t chip_select_cfg0; /* 0x00000000 */ |
| 13 | uint32_t cfg; /* 0x00000004 */ |
| 14 | uint32_t hw_info; /* 0x00000008 */ |
| 15 | uint8_t reserved0[20]; |
| 16 | uint32_t lcd_cfg0; /* 0x00000020 */ |
| 17 | uint32_t lcd_cfg1; /* 0x00000024 */ |
| 18 | uint8_t reserved1[8]; |
| 19 | uint32_t arbiter_cfg; /* 0x00000030 */ |
| 20 | uint8_t reserved2[28]; |
| 21 | uint32_t debug_sel; /* 0x00000050 */ |
| 22 | uint32_t crc_cfg; /* 0x00000054 */ |
| 23 | uint32_t crc_reminder_cfg; /* 0x00000058 */ |
| 24 | uint32_t nand_adm_mux; /* 0x0000005C */ |
| 25 | uint32_t mutex_addr_offset; /* 0x00000060 */ |
| 26 | uint32_t misr_value; /* 0x00000064 */ |
| 27 | uint32_t clkon_cfg; /* 0x00000068 */ |
| 28 | uint32_t core_clkon_cfg; /* 0x0000006C */ |
| 29 | }; |
| 30 | |
| 31 | /* Register: EBI2_CHIP_SELECT_CFG0 */ |
| 32 | #define CS7_CFG_MASK 0x00001000 |
| 33 | #define CS7_CFG_DISABLE 0x00000000 |
| 34 | #define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00001000 |
| 35 | #define CS7_CFG(i) ((i) << 12) |
| 36 | |
| 37 | #define CS6_CFG_MASK 0x00000800 |
| 38 | #define CS6_CFG_DISABLE 0x00000000 |
| 39 | #define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000800 |
| 40 | #define CS6_CFG(i) ((i) << 11) |
| 41 | |
| 42 | #define ETM_CS_CFG_MASK 0x00000400 |
| 43 | #define ETM_CS_CFG_DISABLE 0x00000000 |
| 44 | #define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400 |
| 45 | #define ETM_CS_CFG(i) ((i) << 10) |
| 46 | |
| 47 | #define CS5_CFG_MASK 0x00000300 |
| 48 | #define CS5_CFG_DISABLE 0x00000000 |
| 49 | #define CS5_CFG_LCD_DEVICE_CONNECTED 0x00000100 |
| 50 | #define CS5_CFG_LCD_DEVICE_CHIP_ENABLE 0x00000200 |
| 51 | #define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000300 |
| 52 | #define CS5_CFG(i) ((i) << 8) |
| 53 | |
| 54 | #define CS4_CFG_MASK 0x000000c0 |
| 55 | #define CS4_CFG_DISABLE 0x00000000 |
| 56 | #define CS4_CFG_LCD_DEVICE_CONNECTED 0x00000040 |
| 57 | #define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x000000C0 |
| 58 | #define CS4_CFG(i) ((i) << 6) |
| 59 | |
| 60 | #define CS3_CFG_MASK 0x00000020 |
| 61 | #define CS3_CFG_DISABLE 0x00000000 |
| 62 | #define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000020 |
| 63 | #define CS3_CFG(i) ((i) << 5) |
| 64 | |
| 65 | #define CS2_CFG_MASK 0x00000010 |
| 66 | #define CS2_CFG_DISABLE 0x00000000 |
| 67 | #define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000010 |
| 68 | #define CS2_CFG(i) ((i) << 4) |
| 69 | |
| 70 | #define CS1_CFG_MASK 0x0000000c |
| 71 | #define CS1_CFG_DISABLE 0x00000000 |
| 72 | #define CS1_CFG_SERIAL_FLASH_DEVICE 0x00000004 |
| 73 | #define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000008 |
| 74 | #define CS1_CFG(i) ((i) << 2) |
| 75 | |
| 76 | #define CS0_CFG_MASK 0x00000003 |
| 77 | #define CS0_CFG_DISABLE 0x00000000 |
| 78 | #define CS0_CFG_SERIAL_FLASH_DEVICE 0x00000001 |
| 79 | #define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000002 |
| 80 | #define CS0_CFG(i) ((i) << 0) |
| 81 | |
| 82 | #endif |