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Damien Zammit0cf08052015-05-03 19:49:37 +10001config CPU_INTEL_SOCKET_FCBGA559
2 bool
Arthur Heymans19e72732019-01-11 23:56:51 +01003 help
4 Select this socket on Intel Pineview
Damien Zammit0cf08052015-05-03 19:49:37 +10005
6if CPU_INTEL_SOCKET_FCBGA559
7
8config SOCKET_SPECIFIC_OPTIONS
9 def_bool y
10 select CPU_INTEL_MODEL_106CX
11 select MMX
Arthur Heymans19e72732019-01-11 23:56:51 +010012 select CPU_HAS_L2_ENABLE_MSR
Damien Zammit0cf08052015-05-03 19:49:37 +100013
14config DCACHE_RAM_BASE
15 hex
Kyösti Mälkkic86c6b32016-12-09 17:43:27 +020016 default 0xfefc0000
Damien Zammit0cf08052015-05-03 19:49:37 +100017
18config DCACHE_RAM_SIZE
19 hex
Arthur Heymanse69461d2021-05-05 14:45:28 +020020 default 0x8000
Damien Zammit0cf08052015-05-03 19:49:37 +100021
Arthur Heymans99e578e2019-01-15 20:14:33 +010022config DCACHE_BSP_STACK_SIZE
23 hex
24 default 0x2000
25 help
26 The amount of anticipated stack usage in CAR by bootblock and
27 other stages.
28
Angel Ponsbabffce2020-05-29 01:01:05 +020029config MAX_CPUS
30 int
31 default 4
32
Damien Zammit0cf08052015-05-03 19:49:37 +100033endif