Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2003 Linux Networx |
| 5 | * Copyright (C) 2004 SuSE Linux AG |
| 6 | * Copyright (C) 2004 Tyan Computer |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 7 | * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; version 2 of |
| 12 | * the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 22 | */ |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 23 | |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 24 | #include <console/console.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <device/pci_ops.h> |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 29 | #include <pc80/mc146818rtc.h> |
Steven J. Magnani | ef79223 | 2005-09-21 13:53:44 +0000 | [diff] [blame] | 30 | #include <pc80/isa-dma.h> |
| 31 | #include <arch/io.h> |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame] | 32 | #include <arch/ioapic.h> |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 33 | #include "i82801dx.h" |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 34 | |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 35 | #define NMI_OFF 0 |
| 36 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 37 | typedef struct southbridge_intel_i82801dx_config config_t; |
| 38 | |
| 39 | static void i82801dx_enable_ioapic(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 40 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 41 | u32 reg32; |
Stefan Reinauer | 5c32d24 | 2010-03-17 03:40:23 +0000 | [diff] [blame] | 42 | volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); |
| 43 | volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 44 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 45 | /* Set ACPI base address (I/O space). */ |
| 46 | pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 47 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 48 | /* Enable ACPI I/O and power management. */ |
| 49 | pci_write_config8(dev, ACPI_CNTL, 0x10); |
| 50 | |
| 51 | reg32 = pci_read_config32(dev, GEN_CNTL); |
| 52 | reg32 |= (3 << 7); /* Enable IOAPIC */ |
| 53 | reg32 |= (1 << 13); /* Coprocessor error enable */ |
| 54 | reg32 |= (1 << 1); /* Delayed transaction enable */ |
| 55 | reg32 |= (1 << 2); /* DMA collection buffer enable */ |
| 56 | pci_write_config32(dev, GEN_CNTL, reg32); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 57 | printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 58 | |
| 59 | *ioapic_index = 0; |
| 60 | *ioapic_data = (1 << 25); |
| 61 | |
| 62 | *ioapic_index = 0; |
| 63 | reg32 = *ioapic_data; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 64 | printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 65 | if (reg32 != (1 << 25)) |
| 66 | die("APIC Error\n"); |
| 67 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 68 | *ioapic_index = 3; /* Select Boot Configuration register. */ |
| 69 | *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 70 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 71 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 72 | static void i82801dx_enable_serial_irqs(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 73 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 74 | /* Set packet length and toggle silent mode bit. */ |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 75 | pci_write_config8(dev, SERIRQ_CNTL, |
| 76 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 77 | pci_write_config8(dev, SERIRQ_CNTL, |
| 78 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 79 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 80 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 81 | static void i82801dx_pirq_init(device_t dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 82 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 83 | /* Get the chip configuration */ |
| 84 | config_t *config = dev->chip_info; |
| 85 | |
| 86 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 87 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 88 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 89 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 90 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 91 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 92 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 93 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 94 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 95 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 96 | static void i82801dx_power_options(device_t dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 97 | { |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 98 | u8 reg8; |
| 99 | u16 reg16, pmbase; |
| 100 | u32 reg32; |
| 101 | const char *state; |
| 102 | |
| 103 | int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 104 | int nmi_option; |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 105 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 106 | /* Which state do we want to goto after g3 (power restored)? |
| 107 | * 0 == S0 Full On |
| 108 | * 1 == S5 Soft Off |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 109 | * |
| 110 | * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 111 | */ |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 112 | if (get_option(&pwr_on, "power_on_after_fail") < 0) |
| 113 | pwr_on = MAINBOARD_POWER_ON; |
| 114 | |
| 115 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 116 | reg8 &= 0xfe; |
| 117 | switch (pwr_on) { |
| 118 | case MAINBOARD_POWER_OFF: |
| 119 | reg8 |= 1; |
| 120 | state = "off"; |
| 121 | break; |
| 122 | case MAINBOARD_POWER_ON: |
| 123 | reg8 &= ~1; |
| 124 | state = "on"; |
| 125 | break; |
| 126 | case MAINBOARD_POWER_KEEP: |
| 127 | reg8 &= ~1; |
| 128 | state = "state keep"; |
| 129 | break; |
| 130 | default: |
| 131 | state = "undefined"; |
| 132 | } |
| 133 | |
| 134 | reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ |
| 135 | |
| 136 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
Stefan Reinauer | f0aa09b | 2010-03-23 13:23:40 +0000 | [diff] [blame] | 137 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 138 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 139 | /* Set up NMI on errors. */ |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 140 | reg8 = inb(0x61); |
| 141 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 142 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 143 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 144 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 145 | outb(reg8, 0x61); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 146 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 147 | reg8 = inb(0x70); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 148 | nmi_option = NMI_OFF; |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 149 | get_option(&nmi_option, "nmi"); |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 150 | if (nmi_option) { |
Stefan Reinauer | f0aa09b | 2010-03-23 13:23:40 +0000 | [diff] [blame] | 151 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 152 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 153 | } else { |
Stefan Reinauer | f0aa09b | 2010-03-23 13:23:40 +0000 | [diff] [blame] | 154 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 155 | reg8 |= ( 1 << 7); /* Disable NMI. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 156 | } |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 157 | outb(reg8, 0x70); |
| 158 | |
| 159 | /* Set SMI# rate down and enable CPU_SLP# */ |
| 160 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 161 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 162 | reg16 |= (1 << 5); // CPUSLP_EN Desktop only |
| 163 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 164 | |
| 165 | pmbase = pci_read_config16(dev, 0x40) & 0xfffe; |
| 166 | |
| 167 | /* Set up power management block and determine sleep mode */ |
| 168 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 169 | |
| 170 | reg32 &= ~(7 << 10); // SLP_TYP |
| 171 | reg32 |= (1 << 0); // SCI_EN |
| 172 | outl(reg32, pmbase + 0x04); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 173 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 174 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 175 | static void gpio_init(device_t dev) |
| 176 | { |
| 177 | /* This should be done in romstage.c already */ |
| 178 | pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); |
| 179 | pci_write_config8(dev, GPIO_CNTL, 0x10); |
| 180 | } |
| 181 | |
| 182 | static void i82801dx_rtc_init(struct device *dev) |
| 183 | { |
| 184 | u8 reg8; |
| 185 | u32 reg32; |
| 186 | int rtc_failed; |
| 187 | |
| 188 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 189 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 190 | if (rtc_failed) { |
| 191 | reg8 &= ~(1 << 1); /* Preserve the power fail state. */ |
| 192 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
| 193 | } |
| 194 | reg32 = pci_read_config32(dev, GEN_STS); |
| 195 | rtc_failed |= reg32 & (1 << 2); |
| 196 | rtc_init(rtc_failed); |
| 197 | |
| 198 | /* Enable access to the upper 128 byte bank of CMOS RAM. */ |
| 199 | pci_write_config8(dev, RTC_CONF, 0x04); |
| 200 | } |
| 201 | |
| 202 | static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) |
| 203 | { |
| 204 | u16 reg16; |
| 205 | int i; |
| 206 | |
| 207 | reg16 = pci_read_config16(dev, PCI_DMA_CFG); |
| 208 | reg16 &= 0x300; |
| 209 | for (i = 0; i < 8; i++) { |
| 210 | if (i == 4) |
| 211 | continue; |
| 212 | reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); |
| 213 | } |
| 214 | pci_write_config16(dev, PCI_DMA_CFG, reg16); |
| 215 | } |
| 216 | |
| 217 | static void i82801dx_lpc_decode_en(device_t dev) |
| 218 | { |
| 219 | /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. |
| 220 | * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. |
| 221 | * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. |
| 222 | * We also need to set the value for LPC I/F Enables Register. |
| 223 | */ |
| 224 | pci_write_config8(dev, COM_DEC, 0x10); |
| 225 | pci_write_config16(dev, LPC_EN, 0x300F); |
| 226 | } |
| 227 | |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 228 | /* ICH4 does not mention HPET in the docs, but |
| 229 | * all ICH3 and ICH4 do have HPETs built in. |
| 230 | */ |
| 231 | static void enable_hpet(struct device *dev) |
| 232 | { |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 233 | u32 reg32, hpet, val; |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 234 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 235 | /* Set HPET base address and enable it */ |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 236 | printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 237 | reg32 = pci_read_config32(dev, GEN_CNTL); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 238 | /* |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 239 | * Bit 17 is HPET enable bit. |
| 240 | * Bit 16:15 control the HPET base address. |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 241 | */ |
| 242 | reg32 &= ~(3 << 15); /* Clear it */ |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 243 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 244 | hpet = CONFIG_HPET_ADDRESS >> 12; |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 245 | hpet &= 0x3; |
| 246 | |
| 247 | reg32 |= (hpet << 15); |
| 248 | reg32 |= (1 << 17); /* Enable HPET. */ |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 249 | pci_write_config32(dev, GEN_CNTL, reg32); |
| 250 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 251 | /* Check to see whether it took */ |
| 252 | reg32 = pci_read_config32(dev, GEN_CNTL); |
| 253 | val = reg32 >> 15; |
| 254 | val &= 0x7; |
| 255 | |
| 256 | if ((val & 0x4) && (hpet == (val & 0x3))) { |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 257 | printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS); |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 258 | } else { |
Stefan Reinauer | f0aa09b | 2010-03-23 13:23:40 +0000 | [diff] [blame] | 259 | printk(BIOS_WARNING, "HPET was not enabled correctly\n"); |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 260 | reg32 &= ~(1 << 17); /* Clear Enable */ |
| 261 | pci_write_config32(dev, GEN_CNTL, reg32); |
| 262 | } |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 263 | } |
| 264 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 265 | static void lpc_init(struct device *dev) |
| 266 | { |
| 267 | /* Set the value for PCI command register. */ |
| 268 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 269 | |
| 270 | /* IO APIC initialization. */ |
| 271 | i82801dx_enable_ioapic(dev); |
| 272 | |
| 273 | i82801dx_enable_serial_irqs(dev); |
| 274 | |
| 275 | /* Setup the PIRQ. */ |
| 276 | i82801dx_pirq_init(dev); |
| 277 | |
| 278 | /* Setup power options. */ |
| 279 | i82801dx_power_options(dev); |
| 280 | |
| 281 | /* Set the state of the GPIO lines. */ |
| 282 | gpio_init(dev); |
| 283 | |
| 284 | /* Initialize the real time clock. */ |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 285 | i82801dx_rtc_init(dev); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 286 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 287 | /* Route DMA. */ |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 288 | i82801dx_lpc_route_dma(dev, 0xff); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 289 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 290 | /* Initialize ISA DMA. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 291 | isa_dma_init(); |
| 292 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 293 | /* Setup decode ports and LPC I/F enables. */ |
| 294 | i82801dx_lpc_decode_en(dev); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 295 | |
| 296 | /* Initialize the High Precision Event Timers */ |
| 297 | enable_hpet(dev); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 298 | } |
| 299 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 300 | static void i82801dx_lpc_read_resources(device_t dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 301 | { |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 302 | struct resource *res; |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 303 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 304 | /* Get the normal PCI resources of this device. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 305 | pci_dev_read_resources(dev); |
| 306 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 307 | /* Add an extra subtractive resource for both memory and I/O. */ |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 308 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 309 | res->base = 0; |
| 310 | res->size = 0x1000; |
| 311 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 312 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 313 | |
| 314 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 315 | res->base = 0xff800000; |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 316 | res->size = 0x00800000; /* 8 MB for flash */ |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 317 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 318 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 319 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 320 | res = new_resource(dev, 3); /* IOAPIC */ |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame] | 321 | res->base = IO_APIC_ADDR; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 322 | res->size = 0x00001000; |
| 323 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 324 | } |
| 325 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 326 | static struct device_operations lpc_ops = { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 327 | .read_resources = i82801dx_lpc_read_resources, |
| 328 | .set_resources = pci_dev_set_resources, |
Myles Watson | 7eac445 | 2010-06-17 16:16:56 +0000 | [diff] [blame] | 329 | .enable_resources = pci_dev_enable_resources, |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 330 | .init = lpc_init, |
| 331 | .scan_bus = scan_static_bus, |
| 332 | .enable = i82801dx_enable, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 333 | }; |
| 334 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 335 | /* 82801DB/DBL */ |
| 336 | static const struct pci_driver lpc_driver_db __pci_driver = { |
| 337 | .ops = &lpc_ops, |
| 338 | .vendor = PCI_VENDOR_ID_INTEL, |
| 339 | .device = PCI_DEVICE_ID_INTEL_82801DB_LPC, |
| 340 | }; |
| 341 | |
| 342 | /* 82801DBM */ |
| 343 | static const struct pci_driver lpc_driver_dbm __pci_driver = { |
| 344 | .ops = &lpc_ops, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 345 | .vendor = PCI_VENDOR_ID_INTEL, |
Uwe Hermann | a29ec06 | 2007-11-04 03:21:37 +0000 | [diff] [blame] | 346 | .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 347 | }; |