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review.coreboot.org / coreboot / 8f1c70706056723f2be33ef15b1bc06092f1160f / . / src / soc / amd / genoa / Kconfig
blob: 705805edc8eecc64c0085715f1953e544856591d [file] [log] [blame]
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]1config SOC_AMD_GENOA
2 bool
3
4if SOC_AMD_GENOA
5
6config SOC_SPECIFIC_OPTIONS
7 def_bool y
8 select ARCH_X86
9 select HAVE_EXP_X86_64_SUPPORT
10 select NO_ECAM_MMCONF_SUPPORT
11 select NO_MONOTONIC_TIMER
12 select RESET_VECTOR_IN_RAM
13 select SOC_AMD_COMMON
14 select SOC_AMD_COMMON_BLOCK_ACPIMMIO
15 select SOC_AMD_COMMON_BLOCK_NONCAR
16 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
17 select UNKNOWN_TSC_RATE
18
19config USE_EXP_X86_64_SUPPORT
20 default y
21
vbpandya87d8b8c2023-09-22 20:49:37 +0530[diff] [blame]22config CHIPSET_DEVICETREE
23 string
24 default "soc/amd/genoa/chipset.cb"
25
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]26config EARLY_RESERVED_DRAM_BASE
27 hex
28 default 0x7000000
29 help
30 This variable defines the base address of the DRAM which is reserved
31 for usage by coreboot in early stages (i.e. before ramstage is up).
32 This memory gets reserved in BIOS tables to ensure that the OS does
33 not use it, thus preventing corruption of OS memory in case of S3
34 resume.
35
36config EARLYRAM_BSP_STACK_SIZE
37 hex
38 default 0x1000
39
40config PSP_APOB_DRAM_ADDRESS
41 hex
42 default 0x7001000
43 help
44 Location in DRAM where the PSP will copy the AGESA PSP Output
45 Block.
46
47config PSP_APOB_DRAM_SIZE
48 hex
49 default 0x20000
50
51config PRERAM_CBMEM_CONSOLE_SIZE
52 hex
53 default 0x1600
54 help
55 Increase this value if preram cbmem console is getting truncated
56
57config C_ENV_BOOTBLOCK_SIZE
58 hex
59 default 0x10000
60 help
61 Sets the size of the bootblock stage that should be loaded in DRAM.
62 This variable controls the DRAM allocation size in linker script
63 for bootblock stage.
64
65config ROMSTAGE_ADDR
66 hex
67 default 0x7040000
68 help
69 Sets the address in DRAM where romstage should be loaded.
70
71config ROMSTAGE_SIZE
72 hex
73 default 0x80000
74 help
75 Sets the size of DRAM allocation for romstage in linker script.
76
Arthur Heymans8f1c7072023-07-13 12:52:49 +0200[diff] [blame^]77menu "PSP Configuration Options"
78
79config AMDFW_CONFIG_FILE
80 string
81 default "src/soc/amd/genoa/fw.cfg"
82
83config PSP_DISABLE_POSTCODES
84 bool "Disable PSP post codes"
85 help
86 Disables the output of port80 post codes from PSP.
87
88config PSP_INIT_ESPI
89 bool "Initialize eSPI in PSP Stage 2 Boot Loader"
90 help
91 Select to initialize the eSPI controller in the PSP Stage 2 Boot
92 Loader.
93
94config PSP_UNLOCK_SECURE_DEBUG
95 bool
96 default y
97
98config HAVE_PSP_WHITELIST_FILE
99 bool "Include a debug whitelist file in PSP build"
100 default n
101 help
102 Support secured unlock prior to reset using a whitelisted
103 serial number. This feature requires a signed whitelist image
104 and bootloader from AMD.
105
106 If unsure, answer 'n'
107
108config PSP_WHITELIST_FILE
109 string "Debug whitelist file path"
110 depends on HAVE_PSP_WHITELIST_FILE
111
112config HAVE_SPL_FILE
113 bool
114
115config SPL_TABLE_FILE
116 string "SPL table file"
117 depends on HAVE_SPL_FILE
118 default "3rdparty/amd_blobs_internal/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin"
119
120config PSP_SOFTFUSE_BITS
121 string "PSP Soft Fuse bits to enable"
122 default ""
123 help
124 Space separated list of Soft Fuse bits to enable.
125 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
126 Bit 7: Disable PSP postcodes on Renoir and newer chips only
127 (Set by PSP_DISABLE_PORT80)
128 Bit 15: PSP debug output destination:
129 0=SoC MMIO UART, 1=IO port 0x3F8
130
131 See #57299 (NDA) for additional bit definitions.
132endmenu
133
134
135endif # SOC_AMD_GENOA