Felix Held | 060b8ad | 2021-02-05 22:51:33 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Felix Held | aa77d13 | 2021-02-10 16:13:56 +0100 | [diff] [blame] | 3 | #include <amdblocks/cpu.h> |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 4 | #include <amdblocks/iomap.h> |
Felix Held | f1093af | 2021-07-13 23:00:26 +0200 | [diff] [blame] | 5 | #include <amdblocks/mca.h> |
Felix Held | a5cdf75 | 2021-03-10 15:47:00 +0100 | [diff] [blame] | 6 | #include <amdblocks/reset.h> |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 7 | #include <amdblocks/smm.h> |
Felix Held | 79f705f | 2021-04-22 17:08:50 +0200 | [diff] [blame] | 8 | #include <assert.h> |
Felix Held | 060b8ad | 2021-02-05 22:51:33 +0100 | [diff] [blame] | 9 | #include <console/console.h> |
Raul E Rangel | 35dc4b0 | 2021-02-12 16:04:27 -0700 | [diff] [blame] | 10 | #include <cpu/amd/microcode.h> |
Arthur Heymans | 615818f | 2022-05-31 21:33:43 +0200 | [diff] [blame] | 11 | #include <cpu/amd/mtrr.h> |
Felix Held | 060b8ad | 2021-02-05 22:51:33 +0100 | [diff] [blame] | 12 | #include <cpu/cpu.h> |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 13 | #include <cpu/x86/mp.h> |
| 14 | #include <cpu/x86/mtrr.h> |
| 15 | #include <cpu/x86/smm.h> |
Fred Reitberger | 8e3c6f8 | 2022-03-23 09:59:01 -0400 | [diff] [blame] | 16 | #include <acpi/acpi.h> |
Felix Held | 060b8ad | 2021-02-05 22:51:33 +0100 | [diff] [blame] | 17 | #include <device/device.h> |
| 18 | #include <soc/cpu.h> |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 19 | #include <soc/iomap.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 20 | #include <types.h> |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 21 | |
Felix Held | 79f705f | 2021-04-22 17:08:50 +0200 | [diff] [blame] | 22 | _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of " |
| 23 | "available cores, use the downcore_mode and disable_smt devicetree settings instead."); |
| 24 | |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 25 | /* MP and SMM loading initialization */ |
| 26 | |
| 27 | /* |
| 28 | * Do essential initialization tasks before APs can be fired up - |
| 29 | * |
| 30 | * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This |
| 31 | * creates the MTRR solution that the APs will use. Otherwise APs will try to |
| 32 | * apply the incomplete solution as the BSP is calculating it. |
| 33 | */ |
| 34 | static void pre_mp_init(void) |
| 35 | { |
Arthur Heymans | 615818f | 2022-05-31 21:33:43 +0200 | [diff] [blame] | 36 | const msr_t syscfg = rdmsr(SYSCFG_MSR); |
| 37 | if (syscfg.lo & SYSCFG_MSR_TOM2WB) |
| 38 | x86_setup_mtrrs_with_detect_no_above_4gb(); |
| 39 | else |
| 40 | x86_setup_mtrrs_with_detect(); |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 41 | x86_mtrr_check(); |
| 42 | } |
| 43 | |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 44 | static const struct mp_ops mp_ops = { |
| 45 | .pre_mp_init = pre_mp_init, |
| 46 | .get_cpu_count = get_cpu_count, |
| 47 | .get_smm_info = get_smm_info, |
| 48 | .relocation_handler = smm_relocation_handler, |
Arthur Heymans | a19bc34 | 2022-05-31 21:25:53 +0200 | [diff] [blame] | 49 | .post_mp_init = global_smi_enable, |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 50 | }; |
Felix Held | 060b8ad | 2021-02-05 22:51:33 +0100 | [diff] [blame] | 51 | |
Felix Held | b2d8a5c | 2021-02-10 16:17:13 +0100 | [diff] [blame] | 52 | void mp_init_cpus(struct bus *cpu_bus) |
| 53 | { |
Felix Held | 28a0a14 | 2021-11-02 17:15:58 +0100 | [diff] [blame] | 54 | if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) |
| 55 | die_with_post_code(POST_HW_INIT_FAILURE, |
| 56 | "mp_init_with_smm failed. Halting.\n"); |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 57 | |
| 58 | /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 59 | mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE, |
| 60 | FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); |
Arthur Heymans | a19bc34 | 2022-05-31 21:25:53 +0200 | [diff] [blame] | 61 | |
| 62 | /* SMMINFO only needs to be set up when booting from S5 */ |
| 63 | if (!acpi_is_wakeup_s3()) |
| 64 | apm_control(APM_CNT_SMMINFO); |
Felix Held | b2d8a5c | 2021-02-10 16:17:13 +0100 | [diff] [blame] | 65 | } |
| 66 | |
Felix Held | 060b8ad | 2021-02-05 22:51:33 +0100 | [diff] [blame] | 67 | static void zen_2_3_init(struct device *dev) |
| 68 | { |
Felix Held | a24472a | 2021-07-13 18:21:27 +0200 | [diff] [blame] | 69 | check_mca(); |
Felix Held | aa77d13 | 2021-02-10 16:13:56 +0100 | [diff] [blame] | 70 | set_cstate_io_addr(); |
Raul E Rangel | 35dc4b0 | 2021-02-12 16:04:27 -0700 | [diff] [blame] | 71 | |
| 72 | amd_update_microcode_from_cbfs(); |
Felix Held | 060b8ad | 2021-02-05 22:51:33 +0100 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | static struct device_operations cpu_dev_ops = { |
| 76 | .init = zen_2_3_init, |
| 77 | }; |
| 78 | |
| 79 | static struct cpu_device_id cpu_table[] = { |
| 80 | { X86_VENDOR_AMD, CEZANNE_A0_CPUID}, |
| 81 | { 0, 0 }, |
| 82 | }; |
| 83 | |
| 84 | static const struct cpu_driver zen_2_3 __cpu_driver = { |
| 85 | .ops = &cpu_dev_ops, |
| 86 | .id_table = cpu_table, |
| 87 | }; |