blob: f00266552d336a88d85b0a36dfddbecc6f38a15d [file] [log] [blame]
Felix Held060b8ad2021-02-05 22:51:33 +01001/* SPDX-License-Identifier: GPL-2.0-only */
2
Felix Heldaa77d132021-02-10 16:13:56 +01003#include <amdblocks/cpu.h>
Felix Helda5cdf752021-03-10 15:47:00 +01004#include <amdblocks/reset.h>
Felix Held7aacdd12021-02-10 23:27:47 +01005#include <amdblocks/smm.h>
Felix Held79f705f2021-04-22 17:08:50 +02006#include <assert.h>
Felix Held060b8ad2021-02-05 22:51:33 +01007#include <console/console.h>
Raul E Rangel35dc4b02021-02-12 16:04:27 -07008#include <cpu/amd/microcode.h>
Felix Held060b8ad2021-02-05 22:51:33 +01009#include <cpu/cpu.h>
Felix Heldaa77d132021-02-10 16:13:56 +010010#include <cpu/x86/lapic.h>
Felix Held7aacdd12021-02-10 23:27:47 +010011#include <cpu/x86/mp.h>
12#include <cpu/x86/mtrr.h>
13#include <cpu/x86/smm.h>
Felix Held060b8ad2021-02-05 22:51:33 +010014#include <device/device.h>
15#include <soc/cpu.h>
Felix Held7aacdd12021-02-10 23:27:47 +010016#include <soc/iomap.h>
Felix Held7aacdd12021-02-10 23:27:47 +010017
Felix Held79f705f2021-04-22 17:08:50 +020018_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
19 "available cores, use the downcore_mode and disable_smt devicetree settings instead.");
20
Felix Held7aacdd12021-02-10 23:27:47 +010021/* MP and SMM loading initialization */
22
23/*
24 * Do essential initialization tasks before APs can be fired up -
25 *
26 * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
27 * creates the MTRR solution that the APs will use. Otherwise APs will try to
28 * apply the incomplete solution as the BSP is calculating it.
29 */
30static void pre_mp_init(void)
31{
32 x86_setup_mtrrs_with_detect_no_above_4gb();
33 x86_mtrr_check();
34}
35
36static void post_mp_init(void)
37{
38 global_smi_enable();
39 apm_control(APM_CNT_SMMINFO);
40}
41
42static const struct mp_ops mp_ops = {
43 .pre_mp_init = pre_mp_init,
44 .get_cpu_count = get_cpu_count,
45 .get_smm_info = get_smm_info,
46 .relocation_handler = smm_relocation_handler,
47 .post_mp_init = post_mp_init,
48};
Felix Held060b8ad2021-02-05 22:51:33 +010049
Felix Heldb2d8a5c2021-02-10 16:17:13 +010050void mp_init_cpus(struct bus *cpu_bus)
51{
Felix Held7aacdd12021-02-10 23:27:47 +010052 /* Clear for take-off */
53 if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
54 printk(BIOS_ERR, "MP initialization failure.\n");
55
56 /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
57 mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
58
59 set_warm_reset_flag();
Felix Heldb2d8a5c2021-02-10 16:17:13 +010060}
61
Felix Held060b8ad2021-02-05 22:51:33 +010062static void zen_2_3_init(struct device *dev)
63{
Felix Heldaa77d132021-02-10 16:13:56 +010064 setup_lapic();
65 set_cstate_io_addr();
Raul E Rangel35dc4b02021-02-12 16:04:27 -070066
67 amd_update_microcode_from_cbfs();
Felix Held060b8ad2021-02-05 22:51:33 +010068}
69
70static struct device_operations cpu_dev_ops = {
71 .init = zen_2_3_init,
72};
73
74static struct cpu_device_id cpu_table[] = {
75 { X86_VENDOR_AMD, CEZANNE_A0_CPUID},
76 { 0, 0 },
77};
78
79static const struct cpu_driver zen_2_3 __cpu_driver = {
80 .ops = &cpu_dev_ops,
81 .id_table = cpu_table,
82};