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Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Jonathan Zhang8f895492020-01-16 11:16:45 -08002
3#include <assert.h>
Marc Jones63e2a842020-12-02 11:33:02 -07004#include <intelblocks/acpi.h>
Patrick Rudolph40e07482024-02-23 09:23:41 +01005#include <soc/chip_common.h>
Jonathan Zhang8f895492020-01-16 11:16:45 -08006#include <soc/pci_devs.h>
Marc Jones18960ce2020-11-02 12:41:12 -07007#include <soc/util.h>
Arthur Heymans8a3e2b82022-12-02 12:42:27 +01008#include <stdint.h>
Maximilian Bruneb3e336c2023-09-16 19:49:39 +02009#include <stdlib.h>
Marc Jones9f555742020-09-24 16:35:56 -060010
Marc Jones31ed8852021-01-15 13:29:14 -070011#include "chip.h"
12
13/*
14 * List of supported C-states in this processor.
15 */
16enum {
17 C_STATE_C1, /* 0 */
18 C_STATE_C3, /* 1 */
19 C_STATE_C6, /* 2 */
20 C_STATE_C7, /* 3 */
21 NUM_C_STATES
22};
23
24static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
25 [C_STATE_C1] = {
26 /* C1 */
27 .latency = 1,
28 .power = 0x3e8,
29 .resource = MWAIT_RES(0, 0),
30 },
31 [C_STATE_C3] = {
32 /* C3 */
33 .latency = 15,
34 .power = 0x1f4,
35 .resource = MWAIT_RES(1, 0),
36 },
37 [C_STATE_C6] = {
38 /* C6 */
39 .latency = 41,
40 .power = 0x15e,
41 .resource = MWAIT_RES(2, 0),
42 },
43 [C_STATE_C7] = {
44 /* C7 */
45 .latency = 41,
46 .power = 0x0c8,
47 .resource = MWAIT_RES(3, 0),
48 }
49};
50
51/* Max states supported */
52static int cstate_set_all[] = {
53 C_STATE_C1,
54 C_STATE_C3,
55 C_STATE_C6,
56 C_STATE_C7
57};
58
59static int cstate_set_c1_c6[] = {
60 C_STATE_C1,
61 C_STATE_C6,
62};
63
Angel Ponse9f10ff2021-10-17 13:28:23 +020064const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
Marc Jones9f555742020-09-24 16:35:56 -060065{
Marc Jones31ed8852021-01-15 13:29:14 -070066 static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)];
67 int *cstate_set;
68 int i;
69
70 const config_t *config = config_of_soc();
71
72 const enum acpi_cstate_mode states = config->cstate_states;
73
74 switch (states) {
75 case CSTATES_C1C6:
76 *entries = ARRAY_SIZE(cstate_set_c1_c6);
77 cstate_set = cstate_set_c1_c6;
78 break;
79 case CSTATES_ALL:
80 default:
81 *entries = ARRAY_SIZE(cstate_set_all);
82 cstate_set = cstate_set_all;
83 break;
84 }
85
86 for (i = 0; i < *entries; i++) {
87 map[i] = cstate_map[cstate_set[i]];
88 map[i].ctype = i + 1;
89 }
90 return map;
Marc Jones9f555742020-09-24 16:35:56 -060091}
92
Patrick Rudolph40e07482024-02-23 09:23:41 +010093void iio_domain_set_acpi_name(struct device *dev, const char *prefix)
94{
95 const union xeon_domain_path dn = {
96 .domain_path = dev->path.domain.domain
97 };
98
99 assert(dn.socket < CONFIG_MAX_SOCKET);
100 assert(dn.stack < 16);
101 assert(prefix != NULL && strlen(prefix) == 2);
102
103 if (dn.socket >= CONFIG_MAX_SOCKET || dn.stack >= 16 ||
104 !prefix || strlen(prefix) != 2)
105 return;
106
107 char *name = xmalloc(ACPI_NAME_BUFFER_SIZE);
108 snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%1X%1X", prefix, dn.socket, dn.stack);
109 dev->name = name;
110}
111
112const char *soc_acpi_name(const struct device *dev)
113{
114 if (dev->path.type == DEVICE_PATH_DOMAIN)
115 return dev->name;
116
117 /* FIXME: Add SoC specific device names here */
118
119 return NULL;
120}