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review.coreboot.org / coreboot / e3816794737f2eef53843669973018de972afb98 / . / src / soc / intel / common / acpi / acpi_debug.asl
blob: ecee32c82ee8506a40c1e5801645832287fc3cdf [file] [log] [blame]
Angel Pons0612b272020-04-05 15:46:56 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]2
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]3#if CONFIG(ACPI_CONSOLE)
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]4
5#include <soc/iomap.h>
6
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]7Name (UFLG, CONFIG(CONSOLE_SERIAL))
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]8
9Method (LURT, 1, Serialized)
10{
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]11 If (Arg0 == 0) { /* 0 = 0x3f8 */
12 Local0 = 0x3f8
13 } ElseIf (Arg0 == 1) { /* 1 = 0x2f8 */
14 Local0 = 0x2f8
15 } ElseIf (Arg0 == 2) { /* 2 = 0x3e8 */
16 Local0 = 0x3e8
17 } ElseIf (Arg0 == 3) { /* 3 = 0x2e8 */
18 Local0 = 0x2e8
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]19 }
20 Return (Local0)
21}
22
Varshit B Pandyae3816792022-02-25 16:09:37 +0530[diff] [blame^]23#if CONFIG(DRIVERS_UART_8250MEM_32)
24OperationRegion (UBAR, SystemMemory,
25 CONFIG_CONSOLE_UART_BASE_ADDRESS, 24)
26Field (UBAR, AnyAcc, NoLock, Preserve)
27{
28 TDR, 8, /* Transmit Data Register BAR + 0x000 */
29 , 24,
30 IER, 8, /* Interrupt Enable Register BAR + 0x004 */
31 , 24,
32 IIR, 8, /* Interrupt Identification Register BAR + 0x008 */
33 , 24,
34 LCR, 8, /* Line Control Register BAR + 0x00C */
35 , 24,
36 MCR, 8, /* Modem Control Register BAR + 0x010 */
37 , 24,
38 LSR, 8, /* Line Status Register BAR + 0x014 */
39 , 24
40}
41#else
42OperationRegion (UBAR, SystemIO, LURT (CONFIG_UART_FOR_CONSOLE), 6)
43Field (UBAR, ByteAcc, NoLock, Preserve)
44{
45 TDR, 8, /* Transmit Data Register IO Port + 0x0 */
46 IER, 8, /* Interrupt Enable Register IO Port + 0x1 */
47 IIR, 8, /* Interrupt Identification Register IO Port + 0x2 */
48 LCR, 8, /* Line Control Register IO Port + 0x3 */
49 MCR, 8, /* Modem Control Register IO Port + 0x4 */
50 LSR, 8 /* Line Status Register IO Port + 0x5 */
51}
52#endif
53
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]54Method (APRT, 1, Serialized)
55{
56 Name(OPDT, 0)
57 Name(INDX, 0)
58 Name(LENG, 0)
59 Name(ADBG, Buffer(256) {0})
60
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]61 If (ObjectType(Arg0) == 1) { /* Integer */
Subrata Banikf0c7be42017-06-02 10:18:09 +0530[diff] [blame]62 ToHexString(Arg0, Local0)
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]63 ADBG = Local0
64 } ElseIf (ObjectType(Arg0) == 2) { /* String */
65 ADBG = Arg0
66 } ElseIf (ObjectType(Arg0) == 3) { /* Buffer */
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]67 ToHexString(Arg0, ADBG)
68 } Else {
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]69 ADBG = "This type of object is not supported"
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]70 }
71
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]72 While (DeRefOf(ADBG[INDX]) != 0)
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]73 {
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]74 INDX++
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]75 }
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]76 LENG = INDX /* Length of the String */
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]77
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]78 If (UFLG == 0) {
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]79 /* Enable Baud Rate Divisor Latch, Set Word length to 8 bit*/
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]80 LCR = 0x83
81 IIR = 0x01
82 MCR = 0x03
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]83
84 /* Configure baud rate to 115200 */
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]85 TDR = 0x01
86 IER = 0x00
87 LCR = 0x03 /* Disable Baud Rate Divisor Latch */
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]88
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]89 UFLG++
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]90 }
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]91 INDX = 0x00
92 While (INDX < LENG)
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]93 {
94 /* Wait for the transmitter t to be ready */
95 While (1)
96 {
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]97 OPDT = LSR & 0x20
98 If (OPDT != 0)
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]99 {
100 Break
101 }
102 }
Alexey Buyanov03248032020-06-01 21:41:14 -0700[diff] [blame]103 TDR = DeRefOf (ADBG[INDX])
104 INDX++
Subrata Banikc1645fa2016-08-05 18:25:55 +0530[diff] [blame]105 }
106} /* End of APRT */
107
108#endif