Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 1 | #include <stdint.h> |
| 2 | #include <string.h> |
| 3 | #include <device/pci_def.h> |
| 4 | #include <arch/io.h> |
| 5 | #include <device/pnp_def.h> |
| 6 | #include <cpu/x86/lapic.h> |
| 7 | #include <pc80/mc146818rtc.h> |
| 8 | #include <console/console.h> |
| 9 | #include <lib.h> |
| 10 | #include <spd.h> |
| 11 | #include <cpu/amd/model_fxx_rev.h> |
| 12 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 13 | #include <southbridge/nvidia/ck804/early_smbus.h> |
| 14 | #include <northbridge/amd/amdk8/raminit.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 15 | #include <delay.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 16 | #include <cpu/x86/lapic.h> |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 17 | #include "northbridge/amd/amdk8/reset_test.c" |
| 18 | #include "northbridge/amd/amdk8/debug.c" |
Edward O'Callaghan | 0dd0669 | 2014-04-29 13:59:54 +1000 | [diff] [blame] | 19 | #include <superio/winbond/common/winbond.h> |
Edward O'Callaghan | 4f5a525 | 2014-04-03 14:40:24 +1100 | [diff] [blame] | 20 | #include <superio/winbond/w83627thg/w83627thg.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 21 | #include <cpu/x86/bist.h> |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 22 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 23 | |
Jonathan A. Kollasch | 553fe1c | 2013-10-15 16:45:51 -0500 | [diff] [blame] | 24 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 25 | |
| 26 | static void memreset_setup(void) { } |
| 27 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 28 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
| 29 | |
| 30 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 31 | { |
| 32 | return smbus_read_byte(device, address); |
| 33 | } |
| 34 | |
| 35 | #include "northbridge/amd/amdk8/raminit.c" |
| 36 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 37 | #include "lib/generic_sdram.c" |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 38 | #include "cpu/amd/dualcore/dualcore.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 39 | #include <southbridge/nvidia/ck804/early_setup_ss.h> |
Jonathan A. Kollasch | e299ae6 | 2015-01-31 14:26:14 -0600 | [diff] [blame^] | 40 | #include "southbridge/nvidia/ck804/early_setup_car.c" |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 41 | #include "cpu/amd/model_fxx/init_cpus.c" |
Jonathan A. Kollasch | 553fe1c | 2013-10-15 16:45:51 -0500 | [diff] [blame] | 42 | #if CONFIG_SET_FIDVID |
| 43 | #include "cpu/amd/model_fxx/fidvid.c" |
| 44 | #endif |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 45 | #include "northbridge/amd/amdk8/early_ht.c" |
| 46 | |
| 47 | static void sio_setup(void) |
| 48 | { |
| 49 | uint32_t dword; |
| 50 | uint8_t byte; |
| 51 | |
| 52 | /* subject decoding*/ |
| 53 | byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); |
| 54 | byte |= 0x20; |
| 55 | pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); |
| 56 | |
| 57 | /* LPC Positive Decode 0 */ |
| 58 | dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); |
| 59 | /* Serial 0, Serial 1 */ |
| 60 | dword |= (1<<0) | (1<<1); |
| 61 | pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); |
| 62 | |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 66 | { |
| 67 | static const uint16_t spd_addr [] = { |
Jonathan A. Kollasch | 553fe1c | 2013-10-15 16:45:51 -0500 | [diff] [blame] | 68 | DIMM0, 0, 0, 0, |
| 69 | DIMM1, 0, 0, 0, |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | int needs_reset; |
| 73 | unsigned bsp_apicid = 0, nodes; |
| 74 | struct mem_controller ctrl[8]; |
| 75 | |
| 76 | if (!cpu_init_detectedx && boot_cpu()) { |
| 77 | /* Nothing special needs to be done to find bus 0 */ |
| 78 | /* Allow the HT devices to be found */ |
| 79 | enumerate_ht_chain(); |
| 80 | sio_setup(); |
| 81 | } |
| 82 | |
| 83 | if (bist == 0) |
| 84 | bsp_apicid = init_cpus(cpu_init_detectedx); |
| 85 | |
| 86 | // post_code(0x32); |
| 87 | |
Edward O'Callaghan | 0dd0669 | 2014-04-29 13:59:54 +1000 | [diff] [blame] | 88 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 89 | console_init(); |
| 90 | |
| 91 | /* Halt if there was a built in self test failure */ |
| 92 | report_bist_failure(bist); |
| 93 | |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 94 | #if 0 |
| 95 | dump_pci_device(PCI_DEV(0, 0x18, 0)); |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 96 | #endif |
| 97 | |
| 98 | needs_reset = setup_coherent_ht_domain(); |
| 99 | |
| 100 | wait_all_core0_started(); |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 101 | // It is said that we should start core1 after all core0 launched |
| 102 | start_other_cores(); |
| 103 | wait_all_other_cores_started(bsp_apicid); |
Jonathan A. Kollasch | 553fe1c | 2013-10-15 16:45:51 -0500 | [diff] [blame] | 104 | |
| 105 | #if CONFIG_SET_FIDVID |
| 106 | /* Check to see if processor is capable of changing FIDVID */ |
| 107 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 108 | if ((cpuid_edx(0x80000007) & 0x6) == 0x6) { |
| 109 | msr_t msr; |
| 110 | /* Read FIDVID_STATUS */ |
| 111 | msr = rdmsr(0xc0010042); |
| 112 | printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
| 113 | |
| 114 | enable_fid_change(); |
| 115 | init_fidvid_bsp(bsp_apicid); |
| 116 | |
| 117 | msr = rdmsr(0xc0010042); |
| 118 | printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
| 119 | } |
Jonathan A. Kollasch | e1ffd9e | 2013-10-15 14:26:34 -0500 | [diff] [blame] | 120 | #endif |
| 121 | |
| 122 | needs_reset |= ht_setup_chains_x(); |
| 123 | needs_reset |= ck804_early_setup_x(); |
| 124 | if (needs_reset) { |
| 125 | printk(BIOS_INFO, "ht reset -\n"); |
| 126 | soft_reset(); |
| 127 | } |
| 128 | |
| 129 | allow_all_aps_stop(bsp_apicid); |
| 130 | |
| 131 | nodes = get_nodes(); |
| 132 | //It's the time to set ctrl now; |
| 133 | fill_mem_ctrl(nodes, ctrl, spd_addr); |
| 134 | |
| 135 | enable_smbus(); |
| 136 | #if 0 |
| 137 | dump_spd_registers(&cpu[0]); |
| 138 | dump_smbus_registers(); |
| 139 | #endif |
| 140 | |
| 141 | memreset_setup(); |
| 142 | sdram_initialize(nodes, ctrl); |
| 143 | |
| 144 | #if 0 |
| 145 | print_pci_devices(); |
| 146 | dump_pci_devices(); |
| 147 | #endif |
| 148 | |
| 149 | post_cache_as_ram(); |
| 150 | } |