Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <types.h> |
| 21 | #include <string.h> |
| 22 | #include <cbmem.h> |
| 23 | #include <console/console.h> |
| 24 | #include <arch/acpi.h> |
| 25 | #include <arch/ioapic.h> |
| 26 | #include <arch/acpigen.h> |
| 27 | #include <arch/smp/mpspec.h> |
| 28 | #include <device/device.h> |
| 29 | #include <device/pci.h> |
| 30 | #include <device/pci_ids.h> |
| 31 | #include <cpu/x86/msr.h> |
| 32 | #include <vendorcode/google/chromeos/gnvs.h> |
| 33 | |
| 34 | extern const unsigned char AmlCode[]; |
| 35 | #if CONFIG_HAVE_ACPI_SLIC |
| 36 | unsigned long acpi_create_slic(unsigned long current); |
| 37 | #endif |
| 38 | |
| 39 | #include "southbridge/intel/bd82x6x/nvs.h" |
| 40 | #include "thermal.h" |
| 41 | |
| 42 | static global_nvs_t *gnvs_; |
| 43 | |
| 44 | static void acpi_update_thermal_table(global_nvs_t *gnvs) |
| 45 | { |
| 46 | gnvs->f4of = FAN4_THRESHOLD_OFF; |
| 47 | gnvs->f4on = FAN4_THRESHOLD_ON; |
| 48 | gnvs->f4pw = FAN4_PWM; |
| 49 | |
| 50 | gnvs->f3of = FAN3_THRESHOLD_OFF; |
| 51 | gnvs->f3on = FAN3_THRESHOLD_ON; |
| 52 | gnvs->f3pw = FAN3_PWM; |
| 53 | |
| 54 | gnvs->f2of = FAN2_THRESHOLD_OFF; |
| 55 | gnvs->f2on = FAN2_THRESHOLD_ON; |
| 56 | gnvs->f2pw = FAN2_PWM; |
| 57 | |
| 58 | gnvs->f1of = FAN1_THRESHOLD_OFF; |
| 59 | gnvs->f1on = FAN1_THRESHOLD_ON; |
| 60 | gnvs->f1pw = FAN1_PWM; |
| 61 | |
| 62 | gnvs->f0of = FAN0_THRESHOLD_OFF; |
| 63 | gnvs->f0on = FAN0_THRESHOLD_ON; |
| 64 | gnvs->f0pw = FAN0_PWM; |
| 65 | |
| 66 | gnvs->tcrt = CRITICAL_TEMPERATURE; |
| 67 | gnvs->tpsv = PASSIVE_TEMPERATURE; |
| 68 | gnvs->tmax = MAX_TEMPERATURE; |
| 69 | gnvs->flvl = 5; |
| 70 | } |
| 71 | |
| 72 | static void acpi_create_gnvs(global_nvs_t *gnvs) |
| 73 | { |
| 74 | gnvs_ = gnvs; |
| 75 | memset((void *)gnvs, 0, sizeof(*gnvs)); |
| 76 | gnvs->apic = 1; |
| 77 | gnvs->mpen = 1; /* Enable Multi Processing */ |
| 78 | gnvs->pcnt = dev_count_cpu(); |
| 79 | |
| 80 | /* Enable Front USB ports in S3 by default */ |
| 81 | gnvs->s3u0 = 1; |
| 82 | gnvs->s3u1 = 1; |
| 83 | |
| 84 | /* |
| 85 | * Enable Front USB ports in S5 by default |
| 86 | * to be consistent with back port behavior |
| 87 | */ |
| 88 | gnvs->s5u0 = 1; |
| 89 | gnvs->s5u1 = 1; |
| 90 | |
| 91 | /* CBMEM TOC */ |
| 92 | gnvs->cmem = (u32)get_cbmem_toc(); |
| 93 | |
| 94 | /* IGD Displays */ |
| 95 | gnvs->ndid = 3; |
| 96 | gnvs->did[0] = 0x80000100; |
| 97 | gnvs->did[1] = 0x80000240; |
| 98 | gnvs->did[2] = 0x80000410; |
| 99 | gnvs->did[3] = 0x80000410; |
| 100 | gnvs->did[4] = 0x00000005; |
| 101 | |
| 102 | #if CONFIG_CHROMEOS |
| 103 | // TODO(reinauer) this could move elsewhere? |
| 104 | chromeos_init_vboot(&(gnvs->chromeos)); |
| 105 | #endif |
| 106 | |
| 107 | acpi_update_thermal_table(gnvs); |
| 108 | |
| 109 | // Stumpy has no arms^H^H^H^HEC. |
| 110 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 111 | } |
| 112 | |
| 113 | static void acpi_create_intel_hpet(acpi_hpet_t * hpet) |
| 114 | { |
| 115 | #define HPET_ADDR 0xfed00000ULL |
| 116 | acpi_header_t *header = &(hpet->header); |
| 117 | acpi_addr_t *addr = &(hpet->addr); |
| 118 | |
| 119 | memset((void *) hpet, 0, sizeof(acpi_hpet_t)); |
| 120 | |
| 121 | /* fill out header fields */ |
| 122 | memcpy(header->signature, "HPET", 4); |
| 123 | memcpy(header->oem_id, OEM_ID, 6); |
| 124 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 125 | memcpy(header->asl_compiler_id, ASLC, 4); |
| 126 | |
| 127 | header->length = sizeof(acpi_hpet_t); |
| 128 | header->revision = 1; |
| 129 | |
| 130 | /* fill out HPET address */ |
| 131 | addr->space_id = 0; /* Memory */ |
| 132 | addr->bit_width = 64; |
| 133 | addr->bit_offset = 0; |
| 134 | addr->addrl = HPET_ADDR & 0xffffffff; |
| 135 | addr->addrh = HPET_ADDR >> 32; |
| 136 | |
| 137 | hpet->id = 0x8086a201; /* Intel */ |
| 138 | hpet->number = 0x00; |
| 139 | hpet->min_tick = 0x0080; |
| 140 | |
| 141 | header->checksum = |
| 142 | acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); |
| 143 | } |
| 144 | |
| 145 | unsigned long acpi_fill_madt(unsigned long current) |
| 146 | { |
| 147 | /* Local APICs */ |
| 148 | current = acpi_create_madt_lapics(current); |
| 149 | |
| 150 | /* IOAPIC */ |
| 151 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, |
| 152 | 2, IO_APIC_ADDR, 0); |
| 153 | |
| 154 | /* INT_SRC_OVR */ |
| 155 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 156 | current, 0, 0, 2, 0); |
| 157 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 158 | current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); |
| 159 | |
| 160 | return current; |
| 161 | } |
| 162 | |
| 163 | unsigned long acpi_fill_ssdt_generator(unsigned long current, |
| 164 | const char *oem_table_id) |
| 165 | { |
| 166 | generate_cpu_entries(); |
| 167 | return (unsigned long) (acpigen_get_current()); |
| 168 | } |
| 169 | |
| 170 | unsigned long acpi_fill_slit(unsigned long current) |
| 171 | { |
| 172 | // Not implemented |
| 173 | return current; |
| 174 | } |
| 175 | |
| 176 | unsigned long acpi_fill_srat(unsigned long current) |
| 177 | { |
| 178 | /* No NUMA, no SRAT */ |
| 179 | return current; |
| 180 | } |
| 181 | |
| 182 | void smm_setup_structures(void *gnvs, void *tcg, void *smi1); |
| 183 | |
| 184 | #define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) |
| 185 | unsigned long write_acpi_tables(unsigned long start) |
| 186 | { |
| 187 | unsigned long current; |
| 188 | int i; |
| 189 | acpi_rsdp_t *rsdp; |
| 190 | acpi_rsdt_t *rsdt; |
| 191 | acpi_xsdt_t *xsdt; |
| 192 | acpi_hpet_t *hpet; |
| 193 | acpi_madt_t *madt; |
| 194 | acpi_mcfg_t *mcfg; |
| 195 | acpi_fadt_t *fadt; |
| 196 | acpi_facs_t *facs; |
| 197 | #if CONFIG_HAVE_ACPI_SLIC |
| 198 | acpi_header_t *slic; |
| 199 | #endif |
| 200 | acpi_header_t *ssdt; |
| 201 | acpi_header_t *dsdt; |
| 202 | |
| 203 | current = start; |
| 204 | |
| 205 | /* Align ACPI tables to 16byte */ |
| 206 | ALIGN_CURRENT; |
| 207 | |
| 208 | printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); |
| 209 | |
| 210 | /* We need at least an RSDP and an RSDT Table */ |
| 211 | rsdp = (acpi_rsdp_t *) current; |
| 212 | current += sizeof(acpi_rsdp_t); |
| 213 | ALIGN_CURRENT; |
| 214 | rsdt = (acpi_rsdt_t *) current; |
| 215 | current += sizeof(acpi_rsdt_t); |
| 216 | ALIGN_CURRENT; |
| 217 | xsdt = (acpi_xsdt_t *) current; |
| 218 | current += sizeof(acpi_xsdt_t); |
| 219 | ALIGN_CURRENT; |
| 220 | |
| 221 | /* clear all table memory */ |
| 222 | memset((void *) start, 0, current - start); |
| 223 | |
| 224 | acpi_write_rsdp(rsdp, rsdt, xsdt); |
| 225 | acpi_write_rsdt(rsdt); |
| 226 | acpi_write_xsdt(xsdt); |
| 227 | |
| 228 | printk(BIOS_DEBUG, "ACPI: * FACS\n"); |
| 229 | facs = (acpi_facs_t *) current; |
| 230 | current += sizeof(acpi_facs_t); |
| 231 | ALIGN_CURRENT; |
| 232 | acpi_create_facs(facs); |
| 233 | |
| 234 | printk(BIOS_DEBUG, "ACPI: * DSDT\n"); |
| 235 | dsdt = (acpi_header_t *) current; |
| 236 | memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); |
| 237 | current += dsdt->length; |
| 238 | memcpy(dsdt, &AmlCode, dsdt->length); |
| 239 | |
| 240 | ALIGN_CURRENT; |
| 241 | |
| 242 | printk(BIOS_DEBUG, "ACPI: * FADT\n"); |
| 243 | fadt = (acpi_fadt_t *) current; |
| 244 | current += sizeof(acpi_fadt_t); |
| 245 | ALIGN_CURRENT; |
| 246 | |
| 247 | acpi_create_fadt(fadt, facs, dsdt); |
| 248 | acpi_add_table(rsdp, fadt); |
| 249 | |
| 250 | /* |
| 251 | * We explicitly add these tables later on: |
| 252 | */ |
| 253 | printk(BIOS_DEBUG, "ACPI: * HPET\n"); |
| 254 | |
| 255 | hpet = (acpi_hpet_t *) current; |
| 256 | current += sizeof(acpi_hpet_t); |
| 257 | ALIGN_CURRENT; |
| 258 | acpi_create_intel_hpet(hpet); |
| 259 | acpi_add_table(rsdp, hpet); |
| 260 | |
| 261 | /* If we want to use HPET Timers Linux wants an MADT */ |
| 262 | printk(BIOS_DEBUG, "ACPI: * MADT\n"); |
| 263 | |
| 264 | madt = (acpi_madt_t *) current; |
| 265 | acpi_create_madt(madt); |
| 266 | current += madt->header.length; |
| 267 | ALIGN_CURRENT; |
| 268 | acpi_add_table(rsdp, madt); |
| 269 | |
| 270 | printk(BIOS_DEBUG, "ACPI: * MCFG\n"); |
| 271 | mcfg = (acpi_mcfg_t *) current; |
| 272 | acpi_create_mcfg(mcfg); |
| 273 | current += mcfg->header.length; |
| 274 | ALIGN_CURRENT; |
| 275 | acpi_add_table(rsdp, mcfg); |
| 276 | |
| 277 | /* Pack GNVS into the ACPI table area */ |
| 278 | for (i=0; i < dsdt->length; i++) { |
| 279 | if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { |
| 280 | printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " |
| 281 | "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); |
| 282 | *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes |
| 283 | break; |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | /* And fill it */ |
| 288 | acpi_create_gnvs((global_nvs_t *)current); |
| 289 | |
| 290 | /* And tell SMI about it */ |
| 291 | smm_setup_structures((void *)current, NULL, NULL); |
| 292 | |
| 293 | current += sizeof(global_nvs_t); |
| 294 | ALIGN_CURRENT; |
| 295 | |
| 296 | /* We patched up the DSDT, so we need to recalculate the checksum */ |
| 297 | dsdt->checksum = 0; |
| 298 | dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); |
| 299 | |
| 300 | printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, |
| 301 | dsdt->length); |
| 302 | |
| 303 | #if CONFIG_HAVE_ACPI_SLIC |
| 304 | printk(BIOS_DEBUG, "ACPI: * SLIC\n"); |
| 305 | slic = (acpi_header_t *)current; |
| 306 | current += acpi_create_slic(current); |
| 307 | ALIGN_CURRENT; |
| 308 | acpi_add_table(rsdp, slic); |
| 309 | #endif |
| 310 | |
| 311 | printk(BIOS_DEBUG, "ACPI: * SSDT\n"); |
| 312 | ssdt = (acpi_header_t *)current; |
| 313 | acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); |
| 314 | current += ssdt->length; |
| 315 | acpi_add_table(rsdp, ssdt); |
| 316 | ALIGN_CURRENT; |
| 317 | |
| 318 | printk(BIOS_DEBUG, "current = %lx\n", current); |
| 319 | printk(BIOS_INFO, "ACPI: done.\n"); |
| 320 | return current; |
| 321 | } |
| 322 | |
| 323 | #if CONFIG_CHROMEOS |
| 324 | void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) |
| 325 | { |
| 326 | *vdat_addr = &gnvs_->chromeos.vdat; |
| 327 | *vdat_size = sizeof(gnvs_->chromeos.vdat); |
| 328 | } |
| 329 | #endif |
| 330 | |