Dtrain Hsu | 5d3b1bb | 2022-03-21 14:51:18 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
Dtrain Hsu | e18e1f9 | 2022-05-31 11:51:46 +0800 | [diff] [blame^] | 5 | #include <boardid.h> |
Dtrain Hsu | 5d3b1bb | 2022-03-21 14:51:18 +0800 | [diff] [blame] | 6 | #include <gpio.h> |
| 7 | #include <soc/romstage.h> |
| 8 | |
| 9 | static const struct mb_cfg ddr4_mem_config = { |
| 10 | .type = MEM_TYPE_DDR4, |
| 11 | |
| 12 | .rcomp = { |
| 13 | /* Baseboard uses only 100ohm Rcomp resistors */ |
| 14 | .resistor = 100, |
| 15 | |
| 16 | /* Baseboard Rcomp target values */ |
| 17 | .targets = {50, 20, 25, 25, 25}, |
| 18 | }, |
| 19 | |
| 20 | .ect = 1, /* Early Command Training */ |
| 21 | |
| 22 | .UserBd = BOARD_TYPE_MOBILE, |
| 23 | |
| 24 | .ddr_config = { |
| 25 | .dq_pins_interleaved = false, |
| 26 | }, |
| 27 | }; |
| 28 | |
| 29 | const struct mb_cfg *variant_memory_params(void) |
| 30 | { |
| 31 | return &ddr4_mem_config; |
| 32 | } |
Dtrain Hsu | 82a8d81 | 2022-05-13 19:06:01 +0800 | [diff] [blame] | 33 | |
| 34 | void variant_get_spd_info(struct mem_spd *spd_info) |
| 35 | { |
Dtrain Hsu | e18e1f9 | 2022-05-31 11:51:46 +0800 | [diff] [blame^] | 36 | const uint32_t id = board_id(); |
Dtrain Hsu | 82a8d81 | 2022-05-13 19:06:01 +0800 | [diff] [blame] | 37 | spd_info->topo = MEM_TOPO_DIMM_MODULE; |
Dtrain Hsu | e18e1f9 | 2022-05-31 11:51:46 +0800 | [diff] [blame^] | 38 | |
| 39 | if (id >= 2) { |
| 40 | spd_info->smbus[0].addr_dimm[0] = 0x50; |
| 41 | spd_info->smbus[1].addr_dimm[0] = 0x52; |
| 42 | } else { |
| 43 | spd_info->smbus[0].addr_dimm[0] = 0x52; |
| 44 | spd_info->smbus[1].addr_dimm[0] = 0x50; |
| 45 | } |
Dtrain Hsu | 82a8d81 | 2022-05-13 19:06:01 +0800 | [diff] [blame] | 46 | } |