blob: 01a997e78fc0ecf4dc68725fa1d3ae3a8f306096 [file] [log] [blame]
Dtrain Hsu5d3b1bb2022-03-21 14:51:18 +08001/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3#include <baseboard/gpio.h>
4#include <baseboard/variants.h>
Dtrain Hsue18e1f92022-05-31 11:51:46 +08005#include <boardid.h>
Dtrain Hsu5d3b1bb2022-03-21 14:51:18 +08006#include <gpio.h>
7#include <soc/romstage.h>
8
9static const struct mb_cfg ddr4_mem_config = {
10 .type = MEM_TYPE_DDR4,
11
12 .rcomp = {
13 /* Baseboard uses only 100ohm Rcomp resistors */
14 .resistor = 100,
15
16 /* Baseboard Rcomp target values */
17 .targets = {50, 20, 25, 25, 25},
18 },
19
20 .ect = 1, /* Early Command Training */
21
22 .UserBd = BOARD_TYPE_MOBILE,
23
24 .ddr_config = {
25 .dq_pins_interleaved = false,
26 },
27};
28
29const struct mb_cfg *variant_memory_params(void)
30{
31 return &ddr4_mem_config;
32}
Dtrain Hsu82a8d812022-05-13 19:06:01 +080033
34void variant_get_spd_info(struct mem_spd *spd_info)
35{
Dtrain Hsue18e1f92022-05-31 11:51:46 +080036 const uint32_t id = board_id();
Dtrain Hsu82a8d812022-05-13 19:06:01 +080037 spd_info->topo = MEM_TOPO_DIMM_MODULE;
Dtrain Hsue18e1f92022-05-31 11:51:46 +080038
39 if (id >= 2) {
40 spd_info->smbus[0].addr_dimm[0] = 0x50;
41 spd_info->smbus[1].addr_dimm[0] = 0x52;
42 } else {
43 spd_info->smbus[0].addr_dimm[0] = 0x52;
44 spd_info->smbus[1].addr_dimm[0] = 0x50;
45 }
Dtrain Hsu82a8d812022-05-13 19:06:01 +080046}