zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
Elyes HAOUAS | 65fa598 | 2014-07-22 23:12:38 +0200 | [diff] [blame] | 16 | #ifndef _HUDSON_SMBUS_C_ |
| 17 | #define _HUDSON_SMBUS_C_ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 18 | |
Kyösti Mälkki | e132d57 | 2019-03-02 19:06:17 +0200 | [diff] [blame^] | 19 | #include <arch/io.h> |
Paul Menzel | 883b03f | 2013-05-06 15:18:57 +0200 | [diff] [blame] | 20 | #include <stdint.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 21 | #include "smbus.h" |
| 22 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 23 | static int smbus_wait_until_ready(u32 smbus_io_base) |
| 24 | { |
| 25 | u32 loops; |
| 26 | loops = SMBUS_TIMEOUT; |
| 27 | do { |
| 28 | u8 val; |
| 29 | val = inb(smbus_io_base + SMBHSTSTAT); |
| 30 | val &= 0x1f; |
| 31 | if (val == 0) { /* ready now */ |
| 32 | return 0; |
| 33 | } |
| 34 | outb(val, smbus_io_base + SMBHSTSTAT); |
| 35 | } while (--loops); |
| 36 | return -2; /* time out */ |
| 37 | } |
| 38 | |
| 39 | static int smbus_wait_until_done(u32 smbus_io_base) |
| 40 | { |
| 41 | u32 loops; |
| 42 | loops = SMBUS_TIMEOUT; |
| 43 | do { |
| 44 | u8 val; |
| 45 | |
| 46 | val = inb(smbus_io_base + SMBHSTSTAT); |
| 47 | val &= 0x1f; /* mask off reserved bits */ |
| 48 | if (val & 0x1c) { |
| 49 | return -5; /* error */ |
| 50 | } |
| 51 | if (val == 0x02) { |
| 52 | outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ |
| 53 | return 0; |
| 54 | } |
| 55 | } while (--loops); |
| 56 | return -3; /* timeout */ |
| 57 | } |
| 58 | |
| 59 | int do_smbus_recv_byte(u32 smbus_io_base, u32 device) |
| 60 | { |
| 61 | u8 byte; |
| 62 | |
| 63 | if (smbus_wait_until_ready(smbus_io_base) < 0) { |
| 64 | return -2; /* not ready */ |
| 65 | } |
| 66 | |
Jonathan Neuschäfer | 7090377 | 2017-09-23 21:39:02 +0200 | [diff] [blame] | 67 | /* set the device I'm talking to */ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 68 | outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); |
| 69 | |
| 70 | byte = inb(smbus_io_base + SMBHSTCTRL); |
| 71 | byte &= 0xe3; /* Clear [4:2] */ |
| 72 | byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ |
| 73 | outb(byte, smbus_io_base + SMBHSTCTRL); |
| 74 | |
| 75 | /* poll for transaction completion */ |
| 76 | if (smbus_wait_until_done(smbus_io_base) < 0) { |
| 77 | return -3; /* timeout or error */ |
| 78 | } |
| 79 | |
| 80 | /* read results of transaction */ |
| 81 | byte = inb(smbus_io_base + SMBHSTCMD); |
| 82 | |
| 83 | return byte; |
| 84 | } |
| 85 | |
| 86 | int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) |
| 87 | { |
| 88 | u8 byte; |
| 89 | |
| 90 | if (smbus_wait_until_ready(smbus_io_base) < 0) { |
| 91 | return -2; /* not ready */ |
| 92 | } |
| 93 | |
| 94 | /* set the command... */ |
| 95 | outb(val, smbus_io_base + SMBHSTCMD); |
| 96 | |
Jonathan Neuschäfer | 7090377 | 2017-09-23 21:39:02 +0200 | [diff] [blame] | 97 | /* set the device I'm talking to */ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 98 | outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); |
| 99 | |
| 100 | byte = inb(smbus_io_base + SMBHSTCTRL); |
| 101 | byte &= 0xe3; /* Clear [4:2] */ |
| 102 | byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ |
| 103 | outb(byte, smbus_io_base + SMBHSTCTRL); |
| 104 | |
| 105 | /* poll for transaction completion */ |
| 106 | if (smbus_wait_until_done(smbus_io_base) < 0) { |
| 107 | return -3; /* timeout or error */ |
| 108 | } |
| 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | int do_smbus_read_byte(u32 smbus_io_base, u32 device, |
| 114 | u32 address) |
| 115 | { |
| 116 | u8 byte; |
| 117 | |
| 118 | if (smbus_wait_until_ready(smbus_io_base) < 0) { |
| 119 | return -2; /* not ready */ |
| 120 | } |
| 121 | |
| 122 | /* set the command/address... */ |
| 123 | outb(address & 0xff, smbus_io_base + SMBHSTCMD); |
| 124 | |
Jonathan Neuschäfer | 7090377 | 2017-09-23 21:39:02 +0200 | [diff] [blame] | 125 | /* set the device I'm talking to */ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 126 | outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); |
| 127 | |
| 128 | byte = inb(smbus_io_base + SMBHSTCTRL); |
| 129 | byte &= 0xe3; /* Clear [4:2] */ |
| 130 | byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ |
| 131 | outb(byte, smbus_io_base + SMBHSTCTRL); |
| 132 | |
| 133 | /* poll for transaction completion */ |
| 134 | if (smbus_wait_until_done(smbus_io_base) < 0) { |
| 135 | return -3; /* timeout or error */ |
| 136 | } |
| 137 | |
| 138 | /* read results of transaction */ |
| 139 | byte = inb(smbus_io_base + SMBHSTDAT0); |
| 140 | |
| 141 | return byte; |
| 142 | } |
| 143 | |
| 144 | int do_smbus_write_byte(u32 smbus_io_base, u32 device, |
| 145 | u32 address, u8 val) |
| 146 | { |
| 147 | u8 byte; |
| 148 | |
| 149 | if (smbus_wait_until_ready(smbus_io_base) < 0) { |
| 150 | return -2; /* not ready */ |
| 151 | } |
| 152 | |
| 153 | /* set the command/address... */ |
| 154 | outb(address & 0xff, smbus_io_base + SMBHSTCMD); |
| 155 | |
Jonathan Neuschäfer | 7090377 | 2017-09-23 21:39:02 +0200 | [diff] [blame] | 156 | /* set the device I'm talking to */ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 157 | outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); |
| 158 | |
| 159 | /* output value */ |
| 160 | outb(val, smbus_io_base + SMBHSTDAT0); |
| 161 | |
| 162 | byte = inb(smbus_io_base + SMBHSTCTRL); |
| 163 | byte &= 0xe3; /* Clear [4:2] */ |
| 164 | byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ |
| 165 | outb(byte, smbus_io_base + SMBHSTCTRL); |
| 166 | |
| 167 | /* poll for transaction completion */ |
| 168 | if (smbus_wait_until_done(smbus_io_base) < 0) { |
| 169 | return -3; /* timeout or error */ |
| 170 | } |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | void alink_ab_indx(u32 reg_space, u32 reg_addr, |
| 176 | u32 mask, u32 val) |
| 177 | { |
| 178 | u32 tmp; |
| 179 | |
| 180 | outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); |
| 181 | tmp = inl(AB_DATA); |
| 182 | /* rpr 4.2 |
| 183 | * For certain revisions of the chip, the ABCFG registers, |
| 184 | * with an address of 0x100NN (where 'N' is any hexadecimal |
| 185 | * number), require an extra programming step.*/ |
| 186 | outl(0, AB_INDX); |
| 187 | |
| 188 | tmp &= ~mask; |
| 189 | tmp |= val; |
| 190 | |
| 191 | /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ |
| 192 | outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ |
| 193 | outl(tmp, AB_DATA); |
| 194 | outl(0, AB_INDX); |
| 195 | } |
| 196 | |
| 197 | void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, |
| 198 | u32 mask, u32 val) |
| 199 | { |
| 200 | u32 tmp; |
| 201 | |
| 202 | outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); |
| 203 | tmp = inl(AB_DATA); |
| 204 | /* rpr 4.2 |
| 205 | * For certain revisions of the chip, the ABCFG registers, |
| 206 | * with an address of 0x100NN (where 'N' is any hexadecimal |
| 207 | * number), require an extra programming step.*/ |
| 208 | outl(0, AB_INDX); |
| 209 | |
| 210 | tmp &= ~mask; |
| 211 | tmp |= val; |
| 212 | |
| 213 | //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); |
| 214 | outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ |
| 215 | outl(tmp, AB_DATA); |
| 216 | outl(0, AB_INDX); |
| 217 | } |
| 218 | |
| 219 | /* space = 0: AX_INDXC, AX_DATAC |
| 220 | * space = 1: AX_INDXP, AX_DATAP |
| 221 | */ |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 222 | void alink_ax_indx(u32 space /*c or p? */, u32 axindc, |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 223 | u32 mask, u32 val) |
| 224 | { |
| 225 | u32 tmp; |
| 226 | |
| 227 | /* read axindc to tmp */ |
| 228 | outl(space << 29 | space << 3 | 0x30, AB_INDX); |
| 229 | outl(axindc, AB_DATA); |
| 230 | outl(0, AB_INDX); |
| 231 | outl(space << 29 | space << 3 | 0x34, AB_INDX); |
| 232 | tmp = inl(AB_DATA); |
| 233 | outl(0, AB_INDX); |
| 234 | |
| 235 | tmp &= ~mask; |
| 236 | tmp |= val; |
| 237 | |
| 238 | /* write tmp */ |
| 239 | outl(space << 29 | space << 3 | 0x30, AB_INDX); |
| 240 | outl(axindc, AB_DATA); |
| 241 | outl(0, AB_INDX); |
| 242 | outl(space << 29 | space << 3 | 0x34, AB_INDX); |
| 243 | outl(tmp, AB_DATA); |
| 244 | outl(0, AB_INDX); |
| 245 | } |
| 246 | #endif |