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review.coreboot.org / coreboot / ad7758ca521bab7f1aaa0977516002f905cc0a67 / . / src / include / device / pci_ops.h
blob: f1d50d7060fe187b24d806e54d39f897c2707a13 [file] [log] [blame]
Eric Biederman5899fd82003-04-24 06:25:08 +0000[diff] [blame]1#ifndef PCI_OPS_H
2#define PCI_OPS_H
3
4#include <stdint.h>
Eric Biederman7a5416a2003-06-12 19:23:51 +0000[diff] [blame]5#include <device/device.h>
Kyösti Mälkki3e6913b2019-03-02 16:26:10 +0200[diff] [blame]6#include <device/pci_type.h>
Eric Biederman018d8dd2004-11-04 11:04:33 +0000[diff] [blame]7#include <arch/pci_ops.h>
Eric Biederman5899fd82003-04-24 06:25:08 +0000[diff] [blame]8
Kyösti Mälkki92b52962019-03-01 08:08:28 +0200[diff] [blame]9#ifdef __SIMPLE_DEVICE__
10
11/* Avoid name collisions as different stages have different signature
12 * for these functions. The _s_ stands for simple, fundamental IO or
13 * MMIO variant.
14 */
15#define pci_read_config8 pci_s_read_config8
16#define pci_read_config16 pci_s_read_config16
17#define pci_read_config32 pci_s_read_config32
18#define pci_write_config8 pci_s_write_config8
19#define pci_write_config16 pci_s_write_config16
20#define pci_write_config32 pci_s_write_config32
21#else
Edward O'Callaghan016732f2014-10-29 03:04:40 +1100[diff] [blame]22u8 pci_read_config8(struct device *dev, unsigned int where);
23u16 pci_read_config16(struct device *dev, unsigned int where);
24u32 pci_read_config32(struct device *dev, unsigned int where);
25void pci_write_config8(struct device *dev, unsigned int where, u8 val);
26void pci_write_config16(struct device *dev, unsigned int where, u16 val);
27void pci_write_config32(struct device *dev, unsigned int where, u32 val);
Kyösti Mälkki78d14322019-01-23 15:57:49 +0200[diff] [blame]28const struct pci_bus_operations *pci_bus_default_ops(void);
Stefan Reinauer24d1d4b2013-03-21 11:51:41 -0700[diff] [blame]29#endif
Stefan Reinauer43b29cf2009-03-06 19:11:52 +0000[diff] [blame]30
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]31#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]32static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]33void pci_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask)
34#else
35static __always_inline
36void pci_or_config8(struct device *dev, unsigned int where, u8 ormask)
37#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]38{
39 u8 value = pci_read_config8(dev, where);
40 pci_write_config8(dev, where, value | ormask);
41}
42
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]43#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]44static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]45void pci_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask)
46#else
47static __always_inline
48void pci_or_config16(struct device *dev, unsigned int where, u16 ormask)
49#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]50{
51 u16 value = pci_read_config16(dev, where);
52 pci_write_config16(dev, where, value | ormask);
53}
54
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]55#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]56static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]57void pci_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask)
58#else
59static __always_inline
60void pci_or_config32(struct device *dev, unsigned int where, u32 ormask)
61#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]62{
63 u32 value = pci_read_config32(dev, where);
64 pci_write_config32(dev, where, value | ormask);
65}
66
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]67#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]68static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]69void pci_update_config8(pci_devfn_t dev, int reg, u8 mask, u8 or)
70#else
71static __always_inline
72void pci_update_config8(struct device *dev, int reg, u8 mask, u8 or)
73#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]74{
75 u8 reg8;
76
77 reg8 = pci_read_config8(dev, reg);
78 reg8 &= mask;
79 reg8 |= or;
80 pci_write_config8(dev, reg, reg8);
81}
82
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]83#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]84static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]85void pci_update_config16(pci_devfn_t dev, int reg, u16 mask, u16 or)
86#else
87static __always_inline
88void pci_update_config16(struct device *dev, int reg, u16 mask, u16 or)
89#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]90{
91 u16 reg16;
92
93 reg16 = pci_read_config16(dev, reg);
94 reg16 &= mask;
95 reg16 |= or;
96 pci_write_config16(dev, reg, reg16);
97}
98
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]99#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]100static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]101void pci_update_config32(pci_devfn_t dev, int reg, u32 mask, u32 or)
102#else
103static __always_inline
104void pci_update_config32(struct device *dev, int reg, u32 mask, u32 or)
105#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]106{
107 u32 reg32;
108
109 reg32 = pci_read_config32(dev, reg);
110 reg32 &= mask;
111 reg32 |= or;
112 pci_write_config32(dev, reg, reg32);
113}
114
Eric Biederman5899fd82003-04-24 06:25:08 +0000[diff] [blame]115#endif /* PCI_OPS_H */