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review.coreboot.org / coreboot / dfc2b31517535c8a969fadeec4e18172201cf160 / . / src / soc / intel / apollolake / bootblock / cache_as_ram.S
blob: c81fe0a8e301ef29d4b9826577602b3cf6259750 [file] [log] [blame]
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -0700[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015-2016 Intel Corp.
5 * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
6 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <device/pci_def.h>
15#include <cpu/x86/mtrr.h>
16#include <cpu/x86/cache.h>
17#include <cpu/x86/cr.h>
18#include <cpu/x86/post_code.h>
19
20#define EVICT_CTL_MSR 0x2e0
21
22.global bootblock_pre_c_entry
23bootblock_pre_c_entry:
24 /*
25 * eax: BIST value
26 */
27 movd %eax, %mm2
28
29.global cache_as_ram
30cache_as_ram:
31 post_code(0x21)
32
33 /* Clear/disable fixed MTRRs */
34 mov $fixed_mtrr_list_size, %ebx
35 xor %eax, %eax
36 xor %edx, %edx
37clear_fixed_mtrr:
38 add $-2, %ebx
39 movzwl fixed_mtrr_list(%ebx), %ecx
40 wrmsr
41 jnz clear_fixed_mtrr
42
43 post_code(0x22)
44
45 /* Figure put how many MTRRs we have, and clear them out */
46 mov $MTRR_CAP_MSR, %ecx
47 rdmsr
48 movzb %al, %ebx /* Number of variable MTRRs */
49 mov $MTRR_PHYS_BASE(0), %ecx
50 xor %eax, %eax
51 xor %edx, %edx
52
53clear_var_mtrr:
54 wrmsr
55 inc %ecx
56 wrmsr
57 inc %ecx
58 dec %ebx
59 jnz clear_var_mtrr
60
61 post_code(0x23)
62
63 /* Configure default memory type to uncacheable (UC) */
64 mov $MTRR_DEF_TYPE_MSR, %ecx
65 rdmsr
66 and $MTRR_DEF_TYPE_MASK, %eax
67 wrmsr
68
69 post_code(0x24)
70
71 /* Configure CAR region as write-back (WB) */
72 mov $MTRR_PHYS_BASE(0), %ecx
73 mov $CONFIG_DCACHE_RAM_BASE, %eax
74 or $MTRR_TYPE_WRBACK, %eax
75 xor %edx,%edx
76 wrmsr
77
78 /* Configure the MTRR mask for the size region */
79 mov $MTRR_PHYS_MASK(0), %ecx
80 mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */
81 or $MTRR_PHYS_MASK_VALID, %eax
82 wrmsr
83
84 post_code(0x25)
85
86 /* Enable variable MTRRs */
87 mov $MTRR_DEF_TYPE_MSR, %ecx
88 rdmsr
89 or $MTRR_DEF_TYPE_EN, %eax
90 wrmsr
91
92 /* Enable caching */
93 mov %cr0, %eax
94 and $~(CR0_CD | CR0_NW), %eax
95 invd
96 mov %eax, %cr0
97
98 /* Disable cache eviction (setup stage) */
99 mov $EVICT_CTL_MSR, %ecx
100 rdmsr
101 or $0x1, %eax
102 wrmsr
103
104 post_code(0x26)
105
106 /* Clear the cache memory region. This will also fill up the cache */
107 mov $CONFIG_DCACHE_RAM_BASE, %edi
108 mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
109 xor %eax, %eax
110 rep stos %eax, %es:(%edi)
111
112 post_code(0x27)
113
114 /* Disable cache eviction (run stage) */
115 mov $EVICT_CTL_MSR, %ecx
116 rdmsr
117 or $0x2, %eax
118 wrmsr
119
120 post_code(0x28)
121
122car_init_done:
123
124 /* Setup bootblock stack */
125 mov $_car_stack_end, %esp
126
127before_carstage:
128 post_code(0x2b)
129
130 /* We can call into C functions now */
131 call bootblock_c_entry
132
133 /* Never reached */
134
135.halt_forever:
136 post_code(POST_DEAD_CODE)
137 hlt
138 jmp .halt_forever
139
140fixed_mtrr_list:
141 .word MTRR_FIX_64K_00000
142 .word MTRR_FIX_16K_80000
143 .word MTRR_FIX_16K_A0000
144 .word MTRR_FIX_4K_C0000
145 .word MTRR_FIX_4K_C8000
146 .word MTRR_FIX_4K_D0000
147 .word MTRR_FIX_4K_D8000
148 .word MTRR_FIX_4K_E0000
149 .word MTRR_FIX_4K_E8000
150 .word MTRR_FIX_4K_F0000
151 .word MTRR_FIX_4K_F8000
152fixed_mtrr_list_size = . - fixed_mtrr_list