Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 5 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <cpu/x86/msr.h> |
| 22 | #include <device/pci_def.h> |
Stefan Reinauer | 13e4182 | 2015-04-27 14:02:36 -0700 | [diff] [blame] | 23 | #include <southbridge/amd/common/amd_pci_util.h> |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 24 | #include <southbridge/amd/cimx/cimx_util.h> |
| 25 | #include <arch/acpi.h> |
| 26 | #include <northbridge/amd/agesa/BiosCallOuts.h> |
| 27 | #include <cpu/amd/agesa/s3_resume.h> |
| 28 | #include <cpu/amd/mtrr.h> |
Kyösti Mälkki | cd32da4 | 2015-10-14 22:17:22 +0300 | [diff] [blame] | 29 | #include <smbios.h> |
| 30 | #include <string.h> |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 31 | #include "SBPLATFORM.h" |
| 32 | #include <southbridge/amd/cimx/sb800/pci_devs.h> |
| 33 | #include <northbridge/amd/agesa/family14/pci_devs.h> |
Kyösti Mälkki | 017c215 | 2015-05-11 22:53:19 +0300 | [diff] [blame] | 34 | #include <superio/nuvoton/nct5104d/nct5104d.h> |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 35 | #include "gpio_ftns.h" |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 36 | |
| 37 | void set_pcie_reset(void); |
| 38 | void set_pcie_dereset(void); |
| 39 | |
| 40 | /*********************************************************** |
| 41 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 42 | * This table is responsible for physically routing the PIC and |
| 43 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 44 | * is read and written via registers 0xC00/0xC01 as an |
| 45 | * Index/Data pair. These values are chipset and mainboard |
| 46 | * dependent and should be updated accordingly. |
| 47 | * |
| 48 | * These values are used by the PCI configuration space, |
| 49 | * MP Tables. TODO: Make ACPI use these values too. |
| 50 | * |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 51 | * The PCI INTA/B/C/D pins are connected to |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 52 | * FCH pins INTE/F/G/H on the schematic so these need |
| 53 | * to be routed as well. |
| 54 | */ |
| 55 | static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { |
| 56 | /* INTA# - INTH# */ |
| 57 | [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, |
| 58 | /* Misc-nil,0,1,2, INT from Serial irq */ |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 59 | [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 60 | /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ |
| 61 | [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, |
| 62 | /* IMC INT0 - 5 */ |
| 63 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 64 | /* USB Devs 18/19/20/22 INTA-C */ |
Kyösti Mälkki | 5d899c4 | 2015-01-14 12:58:53 +0200 | [diff] [blame] | 65 | [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 66 | /* IDE, SATA */ |
| 67 | [0x40] = 0x0B,0x0B, |
| 68 | /* GPPInt0 - 3 */ |
| 69 | [0x50] = 0x0A,0x0B,0x0A,0x0B |
| 70 | }; |
| 71 | |
| 72 | static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { |
| 73 | /* INTA# - INTH# */ |
| 74 | [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, |
| 75 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 76 | [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 77 | /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ |
| 78 | [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, |
| 79 | /* IMC INT0 - 5 */ |
| 80 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 81 | /* USB Devs 18/19/22/20 INTA-C */ |
| 82 | [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, |
| 83 | /* IDE, SATA */ |
| 84 | [0x40] = 0x11,0x13, |
| 85 | /* GPPInt0 - 3 */ |
| 86 | [0x50] = 0x10,0x11,0x12,0x13 |
| 87 | }; |
| 88 | |
| 89 | /* |
| 90 | * This table defines the index into the picr/intr_data |
| 91 | * tables for each device. Any enabled device and slot |
| 92 | * that uses hardware interrupts should have an entry |
| 93 | * in this table to define its index into the FCH |
| 94 | * PCI_INTR register 0xC00/0xC01. This index will define |
| 95 | * the interrupt that it should use. Putting PIRQ_A into |
| 96 | * the PIN A index for a device will tell that device to |
| 97 | * use PIC IRQ 10 if it uses PIN A for its hardware INT. |
| 98 | */ |
| 99 | /* |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 100 | * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H |
| 101 | * but because of PCI INT_PIN swizzle isnt implemented to match |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 102 | * the IDSEL (dev 3) of the slot, the table is adjusted for the |
| 103 | * swizzle and INTA is connected to PIRQH so PINA/B/C/D on |
| 104 | * off-chip devices should get mapped to PIRQH/E/F/G. |
| 105 | */ |
| 106 | static const struct pirq_struct mainboard_pirq_data[] = { |
| 107 | /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ |
| 108 | {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ |
| 109 | {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 110 | {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 05.0 */ |
| 111 | {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 06.0 */ |
| 112 | {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* miniPCIe: 07.0 */ |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 113 | {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ |
| 114 | {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ |
| 115 | {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ |
| 116 | {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ |
| 117 | {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ |
| 118 | {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ |
| 119 | {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ |
| 120 | {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ |
| 121 | {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ |
| 122 | {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 123 | {SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* miniPCIe: 15.0 */ |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 124 | {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ |
| 125 | {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ |
| 126 | }; |
| 127 | |
| 128 | /* PIRQ Setup */ |
| 129 | static void pirq_setup(void) |
| 130 | { |
| 131 | pirq_data_ptr = mainboard_pirq_data; |
| 132 | pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); |
| 133 | intr_data_ptr = mainboard_intr_data; |
| 134 | picr_data_ptr = mainboard_picr_data; |
| 135 | } |
| 136 | |
Kyösti Mälkki | 017c215 | 2015-05-11 22:53:19 +0300 | [diff] [blame] | 137 | /* Wrapper to enable GPIO/UART devices under menuconfig. Revisit |
| 138 | * once configuration file format for SPI flash storage is complete. |
| 139 | */ |
| 140 | #define SIO_PORT 0x2e |
| 141 | |
| 142 | static void config_gpio_mux(void) |
| 143 | { |
| 144 | struct device *uart, *gpio; |
| 145 | |
| 146 | uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); |
| 147 | gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); |
| 148 | if (uart) |
| 149 | uart->enabled = CONFIG_PINMUX_UART_C; |
| 150 | if (gpio) |
| 151 | gpio->enabled = CONFIG_PINMUX_GPIO0; |
| 152 | |
| 153 | uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); |
| 154 | gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); |
| 155 | if (uart) |
| 156 | uart->enabled = CONFIG_PINMUX_UART_D; |
| 157 | if (gpio) |
| 158 | gpio->enabled = CONFIG_PINMUX_GPIO1; |
| 159 | } |
| 160 | |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 161 | /** |
| 162 | * TODO |
| 163 | * SB CIMx callback |
| 164 | */ |
| 165 | void set_pcie_reset(void) |
| 166 | { |
| 167 | } |
| 168 | |
| 169 | /** |
| 170 | * TODO |
| 171 | * mainboard specific SB CIMx callback |
| 172 | */ |
| 173 | void set_pcie_dereset(void) |
| 174 | { |
| 175 | } |
| 176 | |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 177 | /********************************************** |
| 178 | * Enable the dedicated functions of the board. |
| 179 | **********************************************/ |
| 180 | static void mainboard_enable(device_t dev) |
| 181 | { |
| 182 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 183 | |
Kyösti Mälkki | 017c215 | 2015-05-11 22:53:19 +0300 | [diff] [blame] | 184 | config_gpio_mux(); |
| 185 | |
Felix Held | b06015b | 2015-11-06 18:31:01 +0100 | [diff] [blame] | 186 | /* Power off unused clock pins of GPP PCIe devices */ |
| 187 | u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); |
| 188 | /* GPP CLK0-2 are connected to the 3 ethernet chips |
| 189 | * GPP CLK3-4 are connected to the miniPCIe slots */ |
Felix Held | df95b51 | 2015-11-06 18:32:43 +0100 | [diff] [blame^] | 190 | write8(misc_mem_clk_cntrl + 0, 0x21); |
| 191 | write8(misc_mem_clk_cntrl + 1, 0x43); |
Felix Held | b06015b | 2015-11-06 18:31:01 +0100 | [diff] [blame] | 192 | /* GPP CLK5 is only connected to test pads -> disable */ |
Felix Held | df95b51 | 2015-11-06 18:32:43 +0100 | [diff] [blame^] | 193 | write8(misc_mem_clk_cntrl + 2, 0x05); |
Felix Held | b06015b | 2015-11-06 18:31:01 +0100 | [diff] [blame] | 194 | /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ |
| 195 | write8(misc_mem_clk_cntrl + 3, 0x00); |
| 196 | write8(misc_mem_clk_cntrl + 4, 0x00); |
| 197 | |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 198 | /* Initialize the PIRQ data structures for consumption */ |
| 199 | pirq_setup(); |
| 200 | } |
| 201 | |
Kyösti Mälkki | cd32da4 | 2015-10-14 22:17:22 +0300 | [diff] [blame] | 202 | /* |
| 203 | * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address |
| 204 | * into the smbios serial number location. |
| 205 | */ |
| 206 | const char *smbios_mainboard_serial_number(void) |
| 207 | { |
| 208 | static char serial[10]; |
| 209 | device_t nic_dev; |
| 210 | uintptr_t bar18; |
| 211 | u32 mac_addr = 0; |
| 212 | int i; |
| 213 | |
| 214 | nic_dev = dev_find_slot(1, PCI_DEVFN(0, 0)); |
| 215 | if ((serial[0] != 0) || !nic_dev) |
| 216 | return serial; |
| 217 | |
| 218 | /* Read in the last 3 bytes of NIC's MAC address. */ |
| 219 | bar18 = pci_read_config32(nic_dev, 0x18); |
| 220 | bar18 &= 0xFFFFFC00; |
| 221 | for (i = 3; i < 6; i++) { |
| 222 | mac_addr <<= 8; |
| 223 | mac_addr |= read8((u8 *)bar18 + i); |
| 224 | } |
| 225 | mac_addr &= 0x00FFFFFF; |
| 226 | mac_addr /= 4; |
| 227 | mac_addr -= 64; |
| 228 | |
| 229 | snprintf(serial, sizeof(serial), "%d", mac_addr); |
| 230 | return serial; |
| 231 | } |
| 232 | |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 233 | static void mainboard_final(void *chip_info) |
| 234 | { |
| 235 | u32 mmio_base; |
| 236 | |
| 237 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n"); |
| 238 | |
| 239 | /* |
| 240 | * LED1/D7/GPIO_189 should be 0 |
| 241 | * LED2/D6/GPIO_190 should be 1 |
| 242 | * LED3/D5/GPIO_191 should be 1 |
| 243 | */ |
| 244 | mmio_base = find_gpio_base(); |
| 245 | configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); |
| 246 | configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); |
| 247 | configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); |
| 248 | } |
| 249 | |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 250 | struct chip_operations mainboard_ops = { |
| 251 | .enable_dev = mainboard_enable, |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 252 | .final = mainboard_final, |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 253 | }; |