Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 4 | #include <soc/pmic_wrap.h> |
Elyes HAOUAS | add76f9 | 2019-03-21 09:55:49 +0100 | [diff] [blame] | 5 | #include <timer.h> |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 6 | |
| 7 | u32 wait_for_state_idle(u32 timeout_us, void *wacs_register, |
| 8 | void *wacs_vldclr_register, u32 *read_reg) |
| 9 | { |
| 10 | u32 reg_rdata; |
| 11 | |
| 12 | struct stopwatch sw; |
| 13 | |
| 14 | stopwatch_init_usecs_expire(&sw, timeout_us); |
| 15 | do { |
| 16 | reg_rdata = read32((wacs_register)); |
| 17 | /* if last read command timeout,clear vldclr bit |
| 18 | read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; |
| 19 | write:FSM_REQ-->idle */ |
| 20 | switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & |
| 21 | RDATA_WACS_FSM_MASK)) { |
| 22 | case WACS_FSM_WFVLDCLR: |
| 23 | write32(wacs_vldclr_register, 1); |
| 24 | pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); |
| 25 | break; |
| 26 | case WACS_FSM_WFDLE: |
| 27 | pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n"); |
| 28 | break; |
| 29 | case WACS_FSM_REQ: |
| 30 | pwrap_err("WACS_FSM = WACS_FSM_REQ\n"); |
| 31 | break; |
| 32 | default: |
| 33 | break; |
| 34 | } |
| 35 | |
| 36 | if (stopwatch_expired(&sw)) |
| 37 | return E_PWR_WAIT_IDLE_TIMEOUT; |
| 38 | |
| 39 | } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != |
| 40 | WACS_FSM_IDLE); /* IDLE State */ |
| 41 | if (read_reg) |
| 42 | *read_reg = reg_rdata; |
| 43 | return 0; |
| 44 | } |
| 45 | |
| 46 | u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us, |
| 47 | void *wacs_register, u32 *read_reg) |
| 48 | { |
| 49 | u32 reg_rdata; |
| 50 | struct stopwatch sw; |
| 51 | |
| 52 | stopwatch_init_usecs_expire(&sw, timeout_us); |
| 53 | do { |
| 54 | reg_rdata = read32((wacs_register)); |
| 55 | |
| 56 | if (stopwatch_expired(&sw)) { |
| 57 | pwrap_err("timeout when waiting for idle\n"); |
| 58 | return E_PWR_WAIT_IDLE_TIMEOUT; |
| 59 | } |
| 60 | } while (fp(reg_rdata)); /* IDLE State */ |
| 61 | if (read_reg) |
| 62 | *read_reg = reg_rdata; |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | s32 pwrap_reset_spislv(void) |
| 67 | { |
| 68 | u32 ret = 0; |
| 69 | |
| 70 | write32(&mtk_pwrap->hiprio_arb_en, 0); |
| 71 | write32(&mtk_pwrap->wrap_en, 0); |
| 72 | write32(&mtk_pwrap->mux_sel, 1); |
| 73 | write32(&mtk_pwrap->man_en, 1); |
| 74 | write32(&mtk_pwrap->dio_en, 0); |
| 75 | |
| 76 | write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8)); |
| 77 | /* Reset counter */ |
| 78 | write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 79 | write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8)); |
| 80 | /* |
| 81 | * In order to pull CSN signal to PMIC, |
| 82 | * PMIC will count it then reset spi slave |
| 83 | */ |
| 84 | write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 85 | write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 86 | write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 87 | write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 88 | |
| 89 | if (wait_for_state_ready(wait_for_sync, TIMEOUT_WAIT_IDLE_US, |
| 90 | &mtk_pwrap->wacs2_rdata, 0)) |
| 91 | ret = E_PWR_TIMEOUT; |
| 92 | |
| 93 | write32(&mtk_pwrap->man_en, 0); |
| 94 | write32(&mtk_pwrap->mux_sel, 0); |
| 95 | |
| 96 | return ret; |
| 97 | } |
| 98 | |
| 99 | s32 pwrap_wacs2(u32 write, u16 addr, u16 wdata, u16 *rdata, u32 init_check) |
| 100 | { |
| 101 | u32 reg_rdata = 0; |
| 102 | u32 wacs_write = 0; |
| 103 | u32 wacs_addr = 0; |
| 104 | u32 wacs_cmd = 0; |
| 105 | u32 wait_result = 0; |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 106 | u32 shift; |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 107 | |
| 108 | if (init_check) { |
| 109 | reg_rdata = read32(&mtk_pwrap->wacs2_rdata); |
| 110 | /* Prevent someone to use pwrap before pwrap init */ |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 111 | if (CONFIG(SOC_MEDIATEK_MT8186)) |
| 112 | shift = RDATA_INIT_DONE_V2_SHIFT; |
| 113 | else |
| 114 | shift = RDATA_INIT_DONE_V1_SHIFT; |
| 115 | |
| 116 | if (((reg_rdata >> shift) & RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 117 | pwrap_err("Pwrap initialization isn't finished\n"); |
| 118 | return E_PWR_NOT_INIT_DONE; |
| 119 | } |
| 120 | } |
| 121 | reg_rdata = 0; |
| 122 | /* Check IDLE in advance */ |
| 123 | wait_result = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US, |
| 124 | &mtk_pwrap->wacs2_rdata, |
| 125 | &mtk_pwrap->wacs2_vldclr, |
| 126 | 0); |
| 127 | if (wait_result != 0) { |
| 128 | pwrap_err("wait_for_fsm_idle fail,wait_result=%d\n", |
| 129 | wait_result); |
| 130 | return E_PWR_WAIT_IDLE_TIMEOUT; |
| 131 | } |
| 132 | wacs_write = write << 31; |
| 133 | wacs_addr = (addr >> 1) << 16; |
| 134 | wacs_cmd = wacs_write | wacs_addr | wdata; |
| 135 | |
| 136 | write32(&mtk_pwrap->wacs2_cmd, wacs_cmd); |
| 137 | if (write == 0) { |
Elyes Haouas | 0f1fb8a | 2022-09-13 09:57:30 +0200 | [diff] [blame] | 138 | if (!rdata) { |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 139 | pwrap_err("rdata is a NULL pointer\n"); |
| 140 | return E_PWR_INVALID_ARG; |
| 141 | } |
| 142 | wait_result = wait_for_state_ready(wait_for_fsm_vldclr, |
| 143 | TIMEOUT_READ_US, |
| 144 | &mtk_pwrap->wacs2_rdata, |
| 145 | ®_rdata); |
| 146 | if (wait_result != 0) { |
| 147 | pwrap_err("wait_for_fsm_vldclr fail,wait_result=%d\n", |
| 148 | wait_result); |
| 149 | return E_PWR_WAIT_IDLE_TIMEOUT_READ; |
| 150 | } |
| 151 | *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) |
| 152 | & RDATA_WACS_RDATA_MASK); |
| 153 | write32(&mtk_pwrap->wacs2_vldclr, 1); |
| 154 | } |
| 155 | |
| 156 | return 0; |
| 157 | } |