Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 2 | |
| 3 | #include <arch/mmu.h> |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 4 | #include <symbols.h> |
| 5 | #include <soc/emi.h> |
| 6 | #include <soc/mmu_operations.h> |
| 7 | |
| 8 | __weak void mtk_soc_after_dram(void) { /* do nothing */ } |
| 9 | |
| 10 | void mtk_mmu_init(void) |
| 11 | { |
Yidi Lin | c68176c | 2024-01-16 15:08:41 +0800 | [diff] [blame] | 12 | static bool mmu_inited; |
| 13 | |
| 14 | if (mmu_inited) |
| 15 | return; |
| 16 | |
| 17 | mmu_inited = true; |
| 18 | |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 19 | mmu_init(); |
| 20 | |
Tristan Shieh | 1efe257 | 2018-08-09 15:14:15 +0800 | [diff] [blame] | 21 | /* |
Huayang Duan | 4bcb63b | 2020-07-23 13:44:17 +0800 | [diff] [blame] | 22 | * Set 0x0 to 8GB address as device memory. We want to config IO_PHYS |
Tristan Shieh | 1efe257 | 2018-08-09 15:14:15 +0800 | [diff] [blame] | 23 | * address to DEV_MEM, and map a proper range of dram for the memory |
| 24 | * test during calibration. |
| 25 | */ |
Huayang Duan | 4bcb63b | 2020-07-23 13:44:17 +0800 | [diff] [blame] | 26 | mmu_config_range((void *)0, (uintptr_t)8U * GiB, DEV_MEM); |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 27 | |
| 28 | /* SRAM is cached */ |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 29 | mmu_config_range(_sram, REGION_SIZE(sram), SECURE_CACHED_MEM); |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 30 | |
| 31 | /* L2C SRAM is cached */ |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 32 | mmu_config_range(_sram_l2c, REGION_SIZE(sram_l2c), SECURE_CACHED_MEM); |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 33 | |
| 34 | /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 35 | mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent), |
Tristan Shieh | 1efe257 | 2018-08-09 15:14:15 +0800 | [diff] [blame] | 36 | SECURE_UNCACHED_MEM); |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 37 | |
| 38 | mmu_enable(); |
| 39 | } |
| 40 | |
| 41 | void mtk_mmu_after_dram(void) |
| 42 | { |
| 43 | /* Map DRAM as cached now that it's up and running */ |
Tristan Shieh | 1efe257 | 2018-08-09 15:14:15 +0800 | [diff] [blame] | 44 | mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM); |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 45 | |
| 46 | mtk_soc_after_dram(); |
| 47 | } |
| 48 | |
| 49 | void mtk_mmu_disable_l2c_sram(void) |
| 50 | { |
| 51 | /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ |
| 52 | /* TODO: Implement true unmapping, and also use it for the zero-page! */ |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 53 | mmu_config_range(_sram_l2c, REGION_SIZE(sram_l2c), DEV_MEM); |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 54 | |
| 55 | /* Careful: changing cache geometry while it's active is a bad idea! */ |
| 56 | mmu_disable(); |
| 57 | |
| 58 | mtk_soc_disable_l2c_sram(); |
| 59 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 60 | /* Re-enable MMU with now enlarged L2 cache. Page tables still valid. */ |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 61 | mmu_enable(); |
| 62 | } |