Ryan Chuang | a9be096 | 2021-06-18 19:48:17 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <delay.h> |
| 5 | #include <device/mmio.h> |
| 6 | #include <soc/dpm.h> |
| 7 | #include <soc/dramc_soc.h> |
| 8 | #include <soc/spm.h> |
| 9 | #include <soc/symbols.h> |
| 10 | |
| 11 | static struct dpm_regs *const mtk_dpm2 = (void *)DPM_CFG_BASE2; |
| 12 | |
| 13 | static int wake_dpm_sram_up(void) |
| 14 | { |
| 15 | int loop = 100; |
| 16 | |
| 17 | /* TODO: convert to new APIs (SET32_BITFIELDS/READ32_BITFIELD) */ |
| 18 | setbits32(&mtk_spm->dramc_mcu_sram_con, DRAMC_MCU_SRAM_SLEEP_B_LSB); |
| 19 | setbits32(&mtk_spm->dramc_mcu2_sram_con, DRAMC_MCU2_SRAM_SLEEP_B_LSB); |
| 20 | |
| 21 | while (loop > 0 && |
| 22 | ((read32(&mtk_spm->dramc_mcu_sram_con) & |
| 23 | DRAMC_MCU_SRAM_SLEEP_B_LSB) == 0 || |
| 24 | (read32(&mtk_spm->dramc_mcu2_sram_con) & |
| 25 | DRAMC_MCU2_SRAM_SLEEP_B_LSB) == 0)) { |
| 26 | mdelay(1); |
| 27 | --loop; |
| 28 | } |
| 29 | |
| 30 | if (loop == 0) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 31 | printk(BIOS_ERR, "failed to wake DPM up.\n"); |
Ryan Chuang | a9be096 | 2021-06-18 19:48:17 +0800 | [diff] [blame] | 32 | return -1; |
| 33 | } |
| 34 | |
| 35 | setbits32(&mtk_spm->dramc_mcu_sram_con, DRAMC_MCU_SRAM_ISOINT_B_LSB); |
| 36 | setbits32(&mtk_spm->dramc_mcu2_sram_con, DRAMC_MCU2_SRAM_ISOINT_B_LSB); |
| 37 | |
| 38 | return 0; |
| 39 | } |
| 40 | |
| 41 | static void dpm_mtcoms_sleep_on(void) |
| 42 | { |
| 43 | /* DPM MTCMOS sleep on */ |
| 44 | write32(&mtk_spm->dpm0_pwr_con, 0x0000204d); |
| 45 | write32(&mtk_spm->dpm1_pwr_con, 0x0000204d); |
| 46 | mdelay(1); |
| 47 | write32(&mtk_spm->dpm0_pwr_con, 0x0000224d); |
| 48 | write32(&mtk_spm->dpm1_pwr_con, 0x0000224d); |
| 49 | mdelay(1); |
| 50 | clrbits32(&mtk_dpm->sw_rstn, DPM_SW_RSTN_RESET); |
| 51 | clrbits32(&mtk_dpm2->sw_rstn, DPM_SW_RSTN_RESET); |
| 52 | } |
| 53 | |
| 54 | static struct mtk_mcu dpm_mcu_4ch[] = { |
| 55 | { |
| 56 | .firmware_name = CONFIG_DPM_DM_FIRMWARE, |
| 57 | .run_address = (void *)DPM_DM_SRAM_BASE2, |
| 58 | }, |
| 59 | { |
| 60 | .firmware_name = CONFIG_DPM_PM_FIRMWARE, |
| 61 | .run_address = (void *)DPM_PM_SRAM_BASE2, |
| 62 | .priv = mtk_dpm2, |
| 63 | .reset = dpm_reset, |
| 64 | }, |
| 65 | }; |
| 66 | |
| 67 | int dpm_4ch_init(void) |
| 68 | { |
| 69 | dpm_mtcoms_sleep_on(); |
| 70 | if (wake_dpm_sram_up()) |
| 71 | return -1; |
| 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | int dpm_4ch_para_setting(void) |
| 76 | { |
| 77 | int i; |
| 78 | struct mtk_mcu *dpm; |
| 79 | |
| 80 | for (i = 0; i < ARRAY_SIZE(dpm_mcu_4ch); i++) { |
| 81 | dpm = &dpm_mcu_4ch[i]; |
| 82 | dpm->load_buffer = _dram_dma; |
| 83 | dpm->buffer_size = REGION_SIZE(dram_dma); |
| 84 | if (mtk_init_mcu(dpm)) |
| 85 | return -1; |
| 86 | } |
| 87 | |
| 88 | return 0; |
| 89 | } |