Blame - src/soc/mediatek/common/Kconfig - coreboot

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Xi Chen	e8c681c	2021-03-03 17:58:07 +0800	[diff] [blame]	1	config SOC_MEDIATEK_COMMON
				2	bool
Jianjun Wang	270b0b6	2021-07-14 15:38:19 +0800	[diff] [blame]	3	select NO_ECAM_MMCONF_SUPPORT if PCI
Xi Chen	e8c681c	2021-03-03 17:58:07 +0800	[diff] [blame]	4	help
				5	common code blocks for Mediatek SOCs
				6
				7	if SOC_MEDIATEK_COMMON
				8
				9	config MEDIATEK_DRAM_DVFS
				10	bool
				11	default n
				12	help
				13	This option enables DRAM calibration with multiple frequencies (low,
				14	medium and high frequency groups, with total 7 frequencies) for DVFS
				15	feature. All supported data rates are: 800, 1200, 1600, 1866, 2400,
				16	3200, 4266.
				17
				18	config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT
				19	bool
				20	default y
Rex-BC Chen	909f2d0	2021-08-10 16:17:09 +0800	[diff] [blame]	21	depends on MEDIATEK_DRAM_DVFS
Xi Chen	e8c681c	2021-03-03 17:58:07 +0800	[diff] [blame]	22	help
				23	This options limit DRAM frequency calibration count from total 7 to 3,
				24	other frequency will directly use the low frequency shu result.
				25
Yu-Ping Wu	c071652	2023-02-21 17:24:54 +0800	[diff] [blame]	26	config MEDIATEK_DRAM_BLOB_FAST_INIT
Xi Chen	5c7a923	2022-01-04 19:00:44 +0800	[diff] [blame]	27	bool "Enable running fast calibration by blob"
				28	default n
				29	help
				30	This option allows performing fast calibration through different
				31	open-source policy.
				32
Xi Chen	a637873	2023-02-21 14:31:58 +0800	[diff] [blame]	33	config MEDIATEK_DRAM_SCRAMBLE
Xi Chen	3ea0202	2023-06-14 10:38:19 +0800	[diff] [blame]	34	bool "Enable DRAM scramble feature"
Yidi Lin	37e83250	2023-06-01 12:15:17 +0800	[diff] [blame]	35	default n
Xi Chen	a637873	2023-02-21 14:31:58 +0800	[diff] [blame]	36	help
				37	This option enables DRAM data scramble, which can prevent DRAM data from
				38	being hacked.
				39
Xi Chen	e8c681c	2021-03-03 17:58:07 +0800	[diff] [blame]	40	config MEMORY_TEST
				41	bool
				42	default y
				43	help
				44	This option enables memory basic compare test to verify the DRAM read
				45	or write is as expected.
				46
Ryan Chuang	d41a5ae	2021-06-18 19:47:39 +0800	[diff] [blame]	47	config DPM_FOUR_CHANNEL
				48	bool
				49	default n
				50	help
				51	This option enables four channel configuration for DPM.
				52
Rex-BC Chen	716320b	2021-08-10 12:28:09 +0800	[diff] [blame]	53	config MTK_DFD
Rex-BC Chen	561a2af	2021-11-25 12:16:51 +0800	[diff] [blame]	54	bool "Enable MediaTek DFD (Design For Debug) settings"
Rex-BC Chen	716320b	2021-08-10 12:28:09 +0800	[diff] [blame]	55	help
Rex-BC Chen	561a2af	2021-11-25 12:16:51 +0800	[diff] [blame]	56	DFD (Design for Debug) is a debugging tool, which scans flip-flops
				57	and dumps to internal RAM on the WDT reset. We reserve 1MB on DRAM
				58	to store logs of DFD.
Rex-BC Chen	716320b	2021-08-10 12:28:09 +0800	[diff] [blame]	59
Rex-BC Chen	c69ea24	2022-03-25 15:53:22 +0800	[diff] [blame]	60	config USE_CBMEM_DRAM_INFO
				61	bool "Support filling dram information to cbmem"
				62	help
				63	The DRAM initialization will keep and return DRAM information (size,
				64	geometry and other DDR info) so we can fill that into the CBMEM.
				65
Rex-BC Chen	7a0ca5b	2022-06-13 19:01:51 +0800	[diff] [blame]	66	config FLASH_DUAL_IO_READ
				67	bool
				68	default n
				69	help
				70	When this option is enabled, the flash controller provides the ability
				71	to dual IO read mode.
				72
Rex-BC Chen	6d449e0	2022-10-19 18:51:39 +0800	[diff] [blame]	73	config PWRAP_WITH_PMIF_SPMI
				74	bool
				75	default n
				76	help
				77	When this option is enabled, the PMIC interface only supports PWRAP
				78	and PMIF_SPMI.
				79
Rex-BC Chen	1543252	2022-10-19 19:00:22 +0800	[diff] [blame]	80	config PMIF_SPMI_IOCFG_DEFAULT_SETTING
				81	bool
				82	default n
				83	help
				84	For SoCs where IO pins default to PMIF_SPMI mode, enable this option
				85	to skip software PMIF_SPMI IO pins configuration.
				86
Yidi Lin	63d26b8	2022-12-20 16:42:53 +0800	[diff] [blame]	87	config DEVAPC_DEBUG
				88	bool
				89	default n
				90	help
				91	When this option is enabled, the DEVAPC driver prints the settings after
				92	initialization.
				93
Yidi Lin	c68176c	2024-01-16 15:08:41 +0800	[diff] [blame]	94	config EARLY_MMU_INIT
				95	bool
				96	default n
				97	help
				98	When this option is enabled, `mtk_mmu_init()` will be done in
				99	`bootblock_soc_early_init()` to reduce the boot time.
				100
Xi Chen	e8c681c	2021-03-03 17:58:07 +0800	[diff] [blame]	101	endif