Angel Pons | 6c42d14 | 2021-06-14 13:53:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | |
| 3 | #ifndef PEI_DATA_H |
| 4 | #define PEI_DATA_H |
| 5 | |
| 6 | #include <types.h> |
| 7 | |
| 8 | #define PEI_VERSION 22 |
| 9 | |
| 10 | #define ABI_X86 __attribute__((regparm(0))) |
| 11 | |
Elyes Haouas | 9d450b2 | 2023-09-10 10:30:29 +0200 | [diff] [blame] | 12 | typedef void ABI_X86(*tx_byte_func)(unsigned char byte); |
Angel Pons | 6c42d14 | 2021-06-14 13:53:44 +0200 | [diff] [blame] | 13 | |
| 14 | enum board_type { |
| 15 | BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */ |
| 16 | BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */ |
| 17 | BOARD_TYPE_USER1, /* SV mobile */ |
| 18 | BOARD_TYPE_USER2, /* SV desktop */ |
| 19 | BOARD_TYPE_USER3, /* SV server */ |
| 20 | BOARD_TYPE_ULT, /* ULT */ |
| 21 | BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */ |
| 22 | BOARD_TYPE_UNKNOWN, |
| 23 | }; |
| 24 | |
| 25 | #define PEI_MAX_USB2_PORTS 14 |
| 26 | #define PEI_MAX_USB3_PORTS 6 |
| 27 | #define PEI_USB_OC_PIN_SKIP 8 |
| 28 | |
| 29 | enum pei_usb2_port_location { |
| 30 | PEI_USB_PORT_BACK_PANEL = 0, |
| 31 | PEI_USB_PORT_FRONT_PANEL, |
| 32 | PEI_USB_PORT_DOCK, |
| 33 | PEI_USB_PORT_MINI_PCIE, |
| 34 | PEI_USB_PORT_FLEX, |
| 35 | PEI_USB_PORT_INTERNAL, |
| 36 | PEI_USB_PORT_SKIP, |
| 37 | PEI_USB_PORT_NGFF_DEVICE_DOWN, |
| 38 | }; |
| 39 | |
| 40 | struct pei_usb2_port_setting { |
| 41 | /* |
| 42 | * Usb Port Length: |
| 43 | * [16:4] = length in inches in octal format |
| 44 | * [3:0] = decimal point |
| 45 | */ |
| 46 | uint16_t length; |
| 47 | uint8_t enable; |
| 48 | uint8_t oc_pin; |
| 49 | uint8_t location; |
| 50 | } __packed; |
| 51 | |
| 52 | struct pei_usb3_port_setting { |
| 53 | uint8_t enable; |
| 54 | uint8_t oc_pin; |
| 55 | /* |
| 56 | * Set to 0 if trace length is > 5 inches |
| 57 | * Set to 1 if trace length is <= 5 inches |
| 58 | */ |
| 59 | uint8_t fixed_eq; |
| 60 | } __packed; |
| 61 | |
| 62 | #define PEI_DIMM_INFO_SERIAL_SIZE 5 |
| 63 | #define PEI_DIMM_INFO_PART_NUMBER_SIZE 19 |
| 64 | #define PEI_DIMM_INFO_TOTAL 8 /* Maximum num of dimm is 8 */ |
| 65 | |
| 66 | /** |
| 67 | * This table is filled by the MRC blob and used to populate the mem_info |
| 68 | * struct, which is placed in CBMEM and then used to generate SMBIOS type |
| 69 | * 17 table(s) |
| 70 | * |
| 71 | * Values are specified according to the JEDEC SPD Standard. |
| 72 | */ |
| 73 | struct pei_dimm_info { |
| 74 | /* |
| 75 | * Size of the module in MiB. |
| 76 | */ |
| 77 | uint32_t dimm_size; |
| 78 | /* |
| 79 | * SMBIOS (not SPD) device type. |
| 80 | * |
| 81 | * See the smbios.h smbios_memory_device_type enum. |
| 82 | */ |
| 83 | uint16_t ddr_type; |
| 84 | uint16_t ddr_frequency; |
| 85 | uint8_t rank_per_dimm; |
| 86 | uint8_t channel_num; |
| 87 | uint8_t dimm_num; |
| 88 | uint8_t bank_locator; |
| 89 | /* |
| 90 | * The last byte is '\0' for the end of string. |
| 91 | * |
| 92 | * Even though the SPD spec defines this field as a byte array the value |
| 93 | * is passed directly to SMBIOS as a string, and thus must be printable |
| 94 | * ASCII. |
| 95 | */ |
| 96 | uint8_t serial[PEI_DIMM_INFO_SERIAL_SIZE]; |
| 97 | /* |
| 98 | * The last byte is '\0' for the end of string |
| 99 | * |
| 100 | * Must contain only printable ASCII. |
| 101 | */ |
| 102 | uint8_t module_part_number[PEI_DIMM_INFO_PART_NUMBER_SIZE]; |
| 103 | /* |
| 104 | * SPD Manufacturer ID |
| 105 | */ |
| 106 | uint16_t mod_id; |
| 107 | /* |
| 108 | * SPD Module Type. |
| 109 | * |
| 110 | * See spd.h for valid values. |
| 111 | * |
| 112 | * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM |
| 113 | */ |
| 114 | uint8_t mod_type; |
| 115 | /* |
| 116 | * SPD bus width. |
| 117 | * |
| 118 | * Bits 0 - 2 encode the primary bus width: |
| 119 | * 0b000 = 8 bit width |
| 120 | * 0b001 = 16 bit width |
| 121 | * 0b010 = 32 bit width |
| 122 | * 0b011 = 64 bit width |
| 123 | * |
| 124 | * Bits 3 - 4 encode the extension bits (ECC): |
| 125 | * 0b00 = 0 extension bits |
| 126 | * 0b01 = 8 bit of ECC |
| 127 | * |
| 128 | * e.g., |
| 129 | * 64 bit bus with 8 bits of ECC (72 bits total): 0b1011 |
| 130 | * 64 bit bus with 0 bits of ECC (64 bits total): 0b0011 |
| 131 | * |
| 132 | * See the smbios.h smbios_memory_bus_width enum. |
| 133 | */ |
| 134 | uint8_t bus_width; |
| 135 | } __packed; |
| 136 | |
| 137 | struct pei_memory_info { |
| 138 | uint8_t dimm_cnt; |
| 139 | struct pei_dimm_info dimm[PEI_DIMM_INFO_TOTAL]; |
| 140 | } __packed; |
| 141 | |
| 142 | struct pei_data { |
| 143 | uint32_t pei_version; |
| 144 | |
| 145 | enum board_type board_type; |
| 146 | int boot_mode; |
| 147 | int ec_present; |
| 148 | int usbdebug; |
| 149 | |
| 150 | /* Base addresses */ |
| 151 | uint32_t pciexbar; |
| 152 | uint16_t smbusbar; |
| 153 | uint32_t xhcibar; |
| 154 | uint32_t ehcibar; |
| 155 | uint32_t gttbar; |
| 156 | uint32_t rcba; |
| 157 | uint32_t pmbase; |
| 158 | uint32_t gpiobase; |
| 159 | uint32_t temp_mmio_base; |
| 160 | uint32_t tseg_size; |
| 161 | |
| 162 | /* |
| 163 | * 0 = leave channel enabled |
| 164 | * 1 = disable dimm 0 on channel |
| 165 | * 2 = disable dimm 1 on channel |
| 166 | * 3 = disable dimm 0+1 on channel |
| 167 | */ |
| 168 | int dimm_channel0_disabled; |
| 169 | int dimm_channel1_disabled; |
| 170 | /* Set to 0 for memory down */ |
| 171 | uint8_t spd_addresses[4]; |
| 172 | /* Enable 2x Refresh Mode */ |
| 173 | int ddr_refresh_2x; |
| 174 | /* DQ pins are interleaved on board */ |
| 175 | int dq_pins_interleaved; |
| 176 | /* Limit DDR3 frequency */ |
| 177 | int max_ddr3_freq; |
| 178 | /* Disable self refresh */ |
| 179 | int disable_self_refresh; |
| 180 | /* Disable cmd power/CKEPD */ |
| 181 | int disable_cmd_pwr; |
| 182 | |
| 183 | /* USB port configuration */ |
| 184 | struct pei_usb2_port_setting usb2_ports[MAX_USB2_PORTS]; |
| 185 | struct pei_usb3_port_setting usb3_ports[MAX_USB3_PORTS]; |
| 186 | |
| 187 | /* |
| 188 | * USB3 board specific PHY tuning |
| 189 | */ |
| 190 | |
| 191 | /* Valid range: 0x69 - 0x80 */ |
| 192 | uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS]; |
| 193 | /* Valid range: 0x80 - 0x9c */ |
| 194 | uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS]; |
| 195 | /* Valid range: 0x39 - 0x80 */ |
| 196 | uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS]; |
| 197 | /* Valid range: 0x3d - 0x4a */ |
| 198 | uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS]; |
| 199 | |
| 200 | /* Console output function */ |
| 201 | tx_byte_func tx_byte; |
| 202 | |
| 203 | /* |
| 204 | * DIMM SPD data for memory down configurations |
| 205 | * [CHANNEL][SLOT][SPD] |
| 206 | */ |
| 207 | uint8_t spd_data[2][2][512]; |
| 208 | |
| 209 | /* |
| 210 | * LPDDR3 DQ byte map |
| 211 | * [CHANNEL][ITERATION][2] |
| 212 | * |
| 213 | * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side) |
| 214 | * DQByteMap[0] - ClkDQByteMap: |
| 215 | * - If clock is per rank, program to [0xFF, 0xFF] |
| 216 | * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] |
| 217 | * - If clock is shared by 2 ranks but does not go to all bytes, |
| 218 | * Entry[i] defines which DQ bytes Group i services |
| 219 | * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB |
| 220 | * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB |
| 221 | * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB |
| 222 | * For DDR, DQByteMap[3:1] = [0xFF, 0] |
| 223 | * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] |
| 224 | * since we have 1 CTL / rank |
| 225 | * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] |
| 226 | * since we have 1 CA Vref |
| 227 | */ |
| 228 | uint8_t dq_map[2][6][2]; |
| 229 | |
| 230 | /* |
| 231 | * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins |
| 232 | * [CHANNEL][MAX_BYTES] |
| 233 | */ |
| 234 | uint8_t dqs_map[2][8]; |
| 235 | |
| 236 | /* Data read from flash and passed into MRC */ |
| 237 | const void *saved_data; |
| 238 | int saved_data_size; |
| 239 | |
| 240 | /* Disable use of saved data (can be set by mainboard) */ |
| 241 | int disable_saved_data; |
| 242 | |
| 243 | /* Data from MRC that should be saved to flash */ |
| 244 | void *data_to_save; |
| 245 | int data_to_save_size; |
| 246 | struct pei_memory_info meminfo; |
| 247 | } __packed; |
| 248 | |
| 249 | #endif |