Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <arch/acpi.h> |
| 16 | #include <arch/acpigen.h> |
| 17 | #include <device/mmio.h> |
| 18 | #include <arch/smp/mpspec.h> |
| 19 | #include <cbmem.h> |
| 20 | #include <console/console.h> |
| 21 | #include <device/pci_ops.h> |
| 22 | #include <ec/google/chromeec/ec.h> |
| 23 | #include <intelblocks/cpulib.h> |
| 24 | #include <intelblocks/pmclib.h> |
| 25 | #include <intelblocks/acpi.h> |
| 26 | #include <soc/cpu.h> |
| 27 | #include <soc/iomap.h> |
| 28 | #include <soc/nvs.h> |
| 29 | #include <soc/pci_devs.h> |
| 30 | #include <soc/pm.h> |
| 31 | #include <soc/soc_chip.h> |
| 32 | #include <soc/systemagent.h> |
| 33 | #include <string.h> |
| 34 | #include <wrdd.h> |
| 35 | |
| 36 | /* |
| 37 | * List of supported C-states in this processor. |
| 38 | */ |
| 39 | enum { |
| 40 | C_STATE_C0, /* 0 */ |
| 41 | C_STATE_C1, /* 1 */ |
| 42 | C_STATE_C1E, /* 2 */ |
| 43 | C_STATE_C6_SHORT_LAT, /* 3 */ |
| 44 | C_STATE_C6_LONG_LAT, /* 4 */ |
| 45 | C_STATE_C7_SHORT_LAT, /* 5 */ |
| 46 | C_STATE_C7_LONG_LAT, /* 6 */ |
| 47 | C_STATE_C7S_SHORT_LAT, /* 7 */ |
| 48 | C_STATE_C7S_LONG_LAT, /* 8 */ |
| 49 | C_STATE_C8, /* 9 */ |
| 50 | C_STATE_C9, /* 10 */ |
| 51 | C_STATE_C10, /* 11 */ |
| 52 | NUM_C_STATES |
| 53 | }; |
| 54 | |
| 55 | #define MWAIT_RES(state, sub_state) \ |
| 56 | { \ |
| 57 | .addrl = (((state) << 4) | (sub_state)), \ |
| 58 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 59 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 60 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 61 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 62 | } |
| 63 | |
| 64 | static const acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 65 | [C_STATE_C0] = {}, |
| 66 | [C_STATE_C1] = { |
| 67 | .latency = 0, |
| 68 | .power = C1_POWER, |
| 69 | .resource = MWAIT_RES(0, 0), |
| 70 | }, |
| 71 | [C_STATE_C1E] = { |
| 72 | .latency = 0, |
| 73 | .power = C1_POWER, |
| 74 | .resource = MWAIT_RES(0, 1), |
| 75 | }, |
| 76 | [C_STATE_C6_SHORT_LAT] = { |
| 77 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 78 | .power = C6_POWER, |
| 79 | .resource = MWAIT_RES(2, 0), |
| 80 | }, |
| 81 | [C_STATE_C6_LONG_LAT] = { |
| 82 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 83 | .power = C6_POWER, |
| 84 | .resource = MWAIT_RES(2, 1), |
| 85 | }, |
| 86 | [C_STATE_C7_SHORT_LAT] = { |
| 87 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 88 | .power = C7_POWER, |
| 89 | .resource = MWAIT_RES(3, 0), |
| 90 | }, |
| 91 | [C_STATE_C7_LONG_LAT] = { |
| 92 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 93 | .power = C7_POWER, |
| 94 | .resource = MWAIT_RES(3, 1), |
| 95 | }, |
| 96 | [C_STATE_C7S_SHORT_LAT] = { |
| 97 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 98 | .power = C7_POWER, |
| 99 | .resource = MWAIT_RES(3, 2), |
| 100 | }, |
| 101 | [C_STATE_C7S_LONG_LAT] = { |
| 102 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 103 | .power = C7_POWER, |
| 104 | .resource = MWAIT_RES(3, 3), |
| 105 | }, |
| 106 | [C_STATE_C8] = { |
| 107 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 108 | .power = C8_POWER, |
| 109 | .resource = MWAIT_RES(4, 0), |
| 110 | }, |
| 111 | [C_STATE_C9] = { |
| 112 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 113 | .power = C9_POWER, |
| 114 | .resource = MWAIT_RES(5, 0), |
| 115 | }, |
| 116 | [C_STATE_C10] = { |
| 117 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 118 | .power = C10_POWER, |
| 119 | .resource = MWAIT_RES(6, 0), |
| 120 | }, |
| 121 | }; |
| 122 | |
| 123 | static int cstate_set_non_s0ix[] = { |
| 124 | C_STATE_C1E, |
| 125 | C_STATE_C6_LONG_LAT, |
| 126 | C_STATE_C7S_LONG_LAT |
| 127 | }; |
| 128 | |
| 129 | static int cstate_set_s0ix[] = { |
| 130 | C_STATE_C1E, |
| 131 | C_STATE_C7S_LONG_LAT, |
| 132 | C_STATE_C10 |
| 133 | }; |
| 134 | |
| 135 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
| 136 | { |
| 137 | static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), |
| 138 | ARRAY_SIZE(cstate_set_non_s0ix))]; |
| 139 | int *set; |
| 140 | int i; |
| 141 | |
| 142 | config_t *config = config_of_soc(); |
| 143 | |
| 144 | int is_s0ix_enable = config->s0ix_enable; |
| 145 | |
| 146 | if (is_s0ix_enable) { |
| 147 | *entries = ARRAY_SIZE(cstate_set_s0ix); |
| 148 | set = cstate_set_s0ix; |
| 149 | } else { |
| 150 | *entries = ARRAY_SIZE(cstate_set_non_s0ix); |
| 151 | set = cstate_set_non_s0ix; |
| 152 | } |
| 153 | |
| 154 | for (i = 0; i < *entries; i++) { |
| 155 | memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); |
| 156 | map[i].ctype = i + 1; |
| 157 | } |
| 158 | return map; |
| 159 | } |
| 160 | |
| 161 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 162 | { |
| 163 | config_t *config = config_of_soc(); |
| 164 | |
| 165 | if (config->eist_enable) |
| 166 | /* Generate P-state tables */ |
| 167 | generate_p_state_entries(core_id, cores_per_package); |
| 168 | } |
| 169 | |
| 170 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 171 | { |
| 172 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 173 | |
| 174 | config_t *config = config_of_soc(); |
| 175 | |
| 176 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 177 | fadt->pm_tmr_len = 4; |
| 178 | fadt->x_pm_tmr_blk.space_id = 1; |
| 179 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 180 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 181 | fadt->x_pm_tmr_blk.access_size = 0; |
| 182 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 183 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 184 | |
| 185 | if (config->s0ix_enable) |
| 186 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
| 187 | } |
| 188 | |
| 189 | uint32_t soc_read_sci_irq_select(void) |
| 190 | { |
| 191 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 192 | return read32((void *)pmc_bar + IRQ_REG); |
| 193 | } |
| 194 | |
| 195 | static unsigned long soc_fill_dmar(unsigned long current) |
| 196 | { |
| 197 | const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 198 | uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 199 | bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
| 200 | |
| 201 | if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { |
| 202 | unsigned long tmp = current; |
| 203 | |
| 204 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
| 205 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 206 | |
| 207 | acpi_dmar_drhd_fixup(tmp, current); |
| 208 | } |
| 209 | |
| 210 | const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); |
| 211 | uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; |
| 212 | bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; |
| 213 | |
| 214 | if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { |
| 215 | unsigned long tmp = current; |
| 216 | |
| 217 | current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); |
| 218 | current += acpi_create_dmar_ds_pci(current, 0, 5, 0); |
| 219 | |
| 220 | acpi_dmar_drhd_fixup(tmp, current); |
| 221 | } |
| 222 | |
| 223 | uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; |
| 224 | bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; |
| 225 | |
| 226 | if (vtvc0bar && vtvc0en) { |
| 227 | const unsigned long tmp = current; |
| 228 | |
| 229 | current += acpi_create_dmar_drhd(current, |
| 230 | DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); |
| 231 | current += acpi_create_dmar_ds_ioapic(current, |
| 232 | 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, |
| 233 | V_P2SB_CFG_IBDF_FUNC); |
| 234 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 235 | 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, |
| 236 | V_P2SB_CFG_HBDF_FUNC); |
| 237 | |
| 238 | acpi_dmar_drhd_fixup(tmp, current); |
| 239 | } |
| 240 | |
| 241 | /* TCSS Thunderbolt root ports */ |
| 242 | for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { |
| 243 | uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK; |
| 244 | bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED; |
| 245 | if (tbtbar && tbten) { |
| 246 | unsigned long tmp = current; |
| 247 | |
| 248 | current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); |
| 249 | current += acpi_create_dmar_ds_pci(current, 0, 7, i); |
| 250 | |
| 251 | acpi_dmar_drhd_fixup(tmp, current); |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | /* Add RMRR entry */ |
| 256 | const unsigned long tmp = current; |
| 257 | current += acpi_create_dmar_rmrr(current, 0, |
| 258 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 259 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 260 | acpi_dmar_rmrr_fixup(tmp, current); |
| 261 | |
| 262 | return current; |
| 263 | } |
| 264 | |
| 265 | unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, |
| 266 | struct acpi_rsdp *rsdp) |
| 267 | { |
| 268 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 269 | |
| 270 | /* |
| 271 | * Create DMAR table only if we have VT-d capability and FSP does not override its |
| 272 | * feature. |
| 273 | */ |
| 274 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 275 | !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) |
| 276 | return current; |
| 277 | |
| 278 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 279 | acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); |
| 280 | current += dmar->header.length; |
| 281 | current = acpi_align_current(current); |
| 282 | acpi_add_table(rsdp, dmar); |
| 283 | |
| 284 | return current; |
| 285 | } |
| 286 | |
| 287 | void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| 288 | { |
| 289 | config_t *config = config_of_soc(); |
| 290 | |
| 291 | /* Set unknown wake source */ |
| 292 | gnvs->pm1i = -1; |
| 293 | |
| 294 | /* CPU core count */ |
| 295 | gnvs->pcnt = dev_count_cpu(); |
| 296 | |
| 297 | if (CONFIG(CONSOLE_CBMEM)) |
| 298 | /* Update the mem console pointer. */ |
| 299 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 300 | |
| 301 | if (CONFIG(CHROMEOS)) { |
| 302 | /* Initialize Verified Boot data */ |
| 303 | chromeos_init_chromeos_acpi(&(gnvs->chromeos)); |
| 304 | if (CONFIG(EC_GOOGLE_CHROMEEC)) { |
| 305 | gnvs->chromeos.vbt2 = google_ec_running_ro() ? |
| 306 | ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; |
| 307 | } else |
| 308 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 309 | } |
| 310 | |
| 311 | /* Enable DPTF based on mainboard configuration */ |
| 312 | gnvs->dpte = config->dptf_enable; |
| 313 | |
| 314 | /* Fill in the Wifi Region id */ |
| 315 | gnvs->cid1 = wifi_regulatory_domain(); |
| 316 | |
| 317 | /* Set USB2/USB3 wake enable bitmaps. */ |
| 318 | gnvs->u2we = config->usb2_wake_enable_bitmap; |
| 319 | gnvs->u3we = config->usb3_wake_enable_bitmap; |
| 320 | |
| 321 | /* Fill in Above 4GB MMIO resource */ |
| 322 | sa_fill_gnvs(gnvs); |
| 323 | } |
| 324 | |
| 325 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 326 | const struct chipset_power_state *ps) |
| 327 | { |
| 328 | /* |
| 329 | * WAK_STS bit is set when the system is in one of the sleep states |
| 330 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 331 | * this bit, the PMC will transition the system to the ON state and |
| 332 | * can only be set by hardware and can only be cleared by writing a one |
| 333 | * to this bit position. |
| 334 | */ |
| 335 | |
| 336 | generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; |
| 337 | return generic_pm1_en; |
| 338 | } |
| 339 | |
| 340 | int soc_madt_sci_irq_polarity(int sci) |
| 341 | { |
| 342 | return MP_IRQ_POLARITY_HIGH; |
| 343 | } |