Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 3 | * |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 16 | #define SYSTEM_TYPE 0 /* SERVER */ |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 17 | |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 18 | /* used by incoherent_ht */ |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 19 | #define FAM10_SCAN_PCI_BUS 0 |
| 20 | #define FAM10_ALLOCATE_IO_RANGE 0 |
| 21 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 22 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 23 | #include <string.h> |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 24 | #include <device/pci_def.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <device/pnp_def.h> |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 28 | #include <cpu/x86/lapic.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 29 | #include <console/console.h> |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 30 | #include <timestamp.h> |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 31 | #include <cpu/amd/model_10xxx_rev.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 32 | #include <lib.h> |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 33 | #include <spd.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 34 | #include <cpu/x86/lapic.h> |
Aaron Durbin | dc9f5cd | 2015-09-08 13:34:43 -0500 | [diff] [blame] | 35 | #include <commonlib/loglevel.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 36 | #include <cpu/x86/bist.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 37 | #include <cpu/amd/car.h> |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 38 | #include <superio/winbond/common/winbond.h> |
| 39 | #include <superio/winbond/w83627hf/w83627hf.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 40 | #include <northbridge/amd/amdfam10/raminit.h> |
| 41 | #include <northbridge/amd/amdht/ht_wrapper.h> |
| 42 | #include <cpu/amd/family_10h-family_15h/init_cpus.h> |
| 43 | #include <arch/early_variables.h> |
| 44 | #include <cbmem.h> |
| 45 | #include "southbridge/amd/amd8111/early_smbus.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 46 | #include "southbridge/amd/amd8111/early_ctrl.c" |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 47 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 48 | #include "resourcemap.c" |
| 49 | #include "cpu/amd/quadcore/quadcore.c" |
| 50 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 51 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 52 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 53 | void activate_spd_rom(const struct mem_controller *ctrl); |
Elyes HAOUAS | dd35e2c | 2018-09-20 17:33:50 +0200 | [diff] [blame^] | 54 | int spd_read_byte(unsigned int device, unsigned int address); |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 55 | extern struct sys_info sysinfo_car; |
| 56 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 57 | static void memreset_setup(void) |
| 58 | { |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 59 | /* GPIO on amd8111 to enable MEMRST ???? */ |
| 60 | outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 61 | outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 62 | } |
| 63 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 64 | void activate_spd_rom(const struct mem_controller *ctrl) |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 65 | { |
| 66 | #define SMBUS_HUB 0x18 |
| 67 | int ret,i; |
| 68 | u8 device = ctrl->spd_switch_addr; |
| 69 | |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 70 | printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 71 | |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 72 | /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ |
| 73 | i = 2; |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 74 | do { |
| 75 | ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7))); |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 76 | } while ((ret != 0) && (i-->0)); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 77 | smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| 78 | } |
| 79 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 80 | int spd_read_byte(u32 device, u32 address) |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 81 | { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 82 | return smbus_read_byte(device, address); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 85 | static const u8 spd_addr[] = { |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 86 | /* first node */ |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 87 | RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 88 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 89 | /* second node */ |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 90 | RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, |
| 91 | #endif |
| 92 | #if CONFIG_MAX_PHYSICAL_CPUS > 2 |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 93 | /* third node */ |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 94 | RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 95 | /* forth node */ |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 96 | RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, |
| 97 | #endif |
| 98 | #if CONFIG_MAX_PHYSICAL_CPUS > 4 |
| 99 | RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 100 | RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 101 | #endif |
| 102 | #if CONFIG_MAX_PHYSICAL_CPUS > 6 |
| 103 | RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 104 | RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 105 | #endif |
| 106 | #if CONFIG_MAX_PHYSICAL_CPUS > 8 |
| 107 | RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 108 | RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 109 | RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 110 | RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 111 | #endif |
| 112 | #if CONFIG_MAX_PHYSICAL_CPUS > 12 |
| 113 | RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 114 | RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 115 | RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 116 | RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 117 | #endif |
| 118 | #if CONFIG_MAX_PHYSICAL_CPUS > 16 |
| 119 | RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 120 | RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 121 | RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 122 | RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 123 | #endif |
| 124 | #if CONFIG_MAX_PHYSICAL_CPUS > 20 |
| 125 | RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 126 | RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 127 | RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 128 | RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 129 | #endif |
| 130 | #if CONFIG_MAX_PHYSICAL_CPUS > 24 |
| 131 | RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 132 | RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 133 | RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 134 | RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 135 | RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 136 | RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 137 | RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 138 | RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 139 | #endif |
| 140 | #if CONFIG_MAX_PHYSICAL_CPUS > 32 |
| 141 | RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 142 | RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 143 | RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 144 | RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 145 | RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 146 | RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 147 | RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 148 | RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 149 | RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 150 | RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 151 | RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 152 | RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 153 | RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 154 | RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 155 | RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 156 | RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 157 | #endif |
| 158 | #if CONFIG_MAX_PHYSICAL_CPUS > 48 |
| 159 | RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 160 | RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 161 | RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 162 | RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 163 | RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 164 | RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 165 | RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 166 | RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 167 | RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 168 | RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 169 | RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 170 | RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 171 | RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 172 | RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 173 | RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 174 | RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 175 | #endif |
| 176 | }; |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 177 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 178 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 179 | { |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 180 | struct sys_info *sysinfo = &sysinfo_car; |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 181 | u32 bsp_apicid = 0, val; |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 182 | msr_t msr; |
| 183 | |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 184 | timestamp_init(timestamp_get()); |
| 185 | timestamp_add_now(TS_START_ROMSTAGE); |
| 186 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 187 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 188 | /* Nothing special needs to be done to find bus 0 */ |
| 189 | /* Allow the HT devices to be found */ |
| 190 | /* mov bsp to bus 0xff when > 8 nodes */ |
| 191 | set_bsp_node_CHtExtNodeCfgEn(); |
| 192 | enumerate_ht_chain(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 193 | } |
| 194 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 195 | post_code(0x30); |
| 196 | |
| 197 | if (bist == 0) { |
Marc Jones | f0174b5 | 2008-04-22 23:27:53 +0000 | [diff] [blame] | 198 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 199 | /* All cores run this but the BSP(node0,core0) is the only core that returns. */ |
| 200 | } |
| 201 | |
| 202 | post_code(0x32); |
| 203 | |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 204 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 205 | console_init(); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 206 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 207 | /* Halt if there was a built in self test failure */ |
| 208 | report_bist_failure(bist); |
| 209 | |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 210 | /* Load MPB */ |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 211 | val = cpuid_eax(1); |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 212 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 213 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 214 | printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); |
| 215 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 216 | |
| 217 | /* Setup sysinfo defaults */ |
| 218 | set_sysinfo_in_ram(0); |
| 219 | |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 220 | update_microcode(val); |
Kyösti Mälkki | f0a13ce | 2013-12-08 07:20:48 +0200 | [diff] [blame] | 221 | |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 222 | post_code(0x33); |
| 223 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 224 | cpuSetAMDMSR(0); |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 225 | post_code(0x34); |
| 226 | |
| 227 | amd_ht_init(sysinfo); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 228 | post_code(0x35); |
| 229 | |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 230 | /* Setup nodes PCI space and start core 0 AP init. */ |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 231 | finalize_node_setup(sysinfo); |
| 232 | |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 233 | /* Setup any mainboard PCI settings etc. */ |
| 234 | setup_mb_resource_map(); |
| 235 | post_code(0x36); |
| 236 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 237 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 238 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 239 | It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 240 | I think it could be done by putting the spinlock flag in the cache |
| 241 | of the BSP located right after sysinfo. |
| 242 | */ |
| 243 | wait_all_core0_started(); |
| 244 | |
Martin Roth | f95911a | 2017-06-24 21:45:13 -0600 | [diff] [blame] | 245 | #if IS_ENABLED(CONFIG_LOGICAL_CPUS) |
Marc Jones | f0174b5 | 2008-04-22 23:27:53 +0000 | [diff] [blame] | 246 | /* Core0 on each node is configured. Now setup any additional cores. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 247 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 248 | start_other_cores(bsp_apicid); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 249 | post_code(0x37); |
| 250 | wait_all_other_cores_started(bsp_apicid); |
| 251 | #endif |
| 252 | |
| 253 | post_code(0x38); |
| 254 | |
Martin Roth | f95911a | 2017-06-24 21:45:13 -0600 | [diff] [blame] | 255 | #if IS_ENABLED(CONFIG_SET_FIDVID) |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 256 | msr = rdmsr(0xc0010071); |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 257 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 258 | |
| 259 | /* FIXME: The sb fid change may survive the warm reset and only |
| 260 | need to be done once.*/ |
| 261 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 262 | |
| 263 | post_code(0x39); |
| 264 | |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 265 | if (!warm_reset_detect(0)) { /* BSP is node 0 */ |
Marc Jones | f0174b5 | 2008-04-22 23:27:53 +0000 | [diff] [blame] | 266 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 267 | } else { |
Elyes HAOUAS | caccd97 | 2016-10-10 21:25:17 +0200 | [diff] [blame] | 268 | init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | post_code(0x3A); |
| 272 | |
Marc Jones | f0174b5 | 2008-04-22 23:27:53 +0000 | [diff] [blame] | 273 | /* show final fid and vid */ |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 274 | msr = rdmsr(0xc0010071); |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 275 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 276 | #endif |
| 277 | |
Marc Jones | f0174b5 | 2008-04-22 23:27:53 +0000 | [diff] [blame] | 278 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 279 | if (!warm_reset_detect(0)) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 280 | printk(BIOS_INFO, "...WARM RESET...\n\n\n"); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 281 | soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); |
| 282 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 283 | } |
| 284 | |
| 285 | post_code(0x3B); |
| 286 | |
Marc Jones | f0174b5 | 2008-04-22 23:27:53 +0000 | [diff] [blame] | 287 | /* FIXME: Move this to chipset init. |
| 288 | enable cf9 for hard reset */ |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 289 | printk(BIOS_DEBUG, "enable_cf9_x()\n"); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 290 | enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn); |
| 291 | post_code(0x3C); |
| 292 | |
Marc Jones | f0174b5 | 2008-04-22 23:27:53 +0000 | [diff] [blame] | 293 | /* It's the time to set ctrl in sysinfo now; */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 294 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 295 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 296 | post_code(0x3D); |
| 297 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 298 | printk(BIOS_DEBUG, "enable_smbus()\n"); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 299 | enable_smbus(); |
| 300 | post_code(0x3E); |
| 301 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 302 | memreset_setup(); |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 303 | post_code(0x40); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 304 | |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 305 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 306 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 307 | raminit_amdmct(sysinfo); |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 308 | timestamp_add_now(TS_AFTER_INITRAM); |
| 309 | |
Timothy Pearson | 86f4ca5 | 2015-03-13 13:27:58 -0500 | [diff] [blame] | 310 | cbmem_initialize_empty(); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 311 | post_code(0x41); |
| 312 | |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 313 | amdmct_cbmem_store_info(sysinfo); |
| 314 | |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 315 | post_code(0x42); |
Marc Jones | 2ce8bfd | 2007-12-19 01:49:44 +0000 | [diff] [blame] | 316 | } |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 317 | |
| 318 | /** |
| 319 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 320 | * Description: |
| 321 | * This routine is called every time a non-coherent chain is processed. |
| 322 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 323 | * swap list. The first part of the list controls the BUID assignment and the |
| 324 | * second part of the list provides the device to device linking. Device orientation |
| 325 | * can be detected automatically, or explicitly. See documentation for more details. |
| 326 | * |
| 327 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 328 | * based on each device's unit count. |
| 329 | * |
| 330 | * Parameters: |
Martin Roth | c3fde7e | 2014-12-29 22:13:37 -0700 | [diff] [blame] | 331 | * @param[in] node = The node on which this chain is located |
| 332 | * @param[in] link = The link on the host for this chain |
| 333 | * @param[out] List = supply a pointer to a list |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 334 | */ |
| 335 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 336 | { |
| 337 | static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; |
| 338 | /* If the BUID was adjusted in early_ht we need to do the manual override */ |
| 339 | if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { |
| 340 | printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); |
| 341 | if ((node == 0) && (link == 0)) { /* BSP SB link */ |
| 342 | *List = swaplist; |
| 343 | return 1; |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | return 0; |
| 348 | } |