Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/smp/mpspec.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <arch/ioapic.h> |
| 22 | #include <string.h> |
| 23 | #include <stdint.h> |
| 24 | #include <cpu/amd/amdfam15.h> |
| 25 | #include <arch/cpu.h> |
| 26 | #include <cpu/x86/lapic.h> |
| 27 | #include <southbridge/amd/common/amd_pci_util.h> |
| 28 | |
| 29 | #if 0 |
| 30 | u8 picr_data[FCH_INT_TABLE_SIZE] = { |
| 31 | 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/ |
| 32 | 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */ |
| 33 | 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */ |
| 34 | 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */ |
| 35 | 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */ |
| 36 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */ |
| 37 | 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */ |
| 38 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */ |
| 39 | 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */ |
| 40 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */ |
| 41 | // 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */ |
| 42 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */ |
| 43 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */ |
| 44 | 0x00,0x00,0x1F /* 60 - 62 */ |
| 45 | }; |
| 46 | u8 intr_data[FCH_INT_TABLE_SIZE] = { |
| 47 | 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/ |
| 48 | 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */ |
| 49 | 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */ |
| 50 | 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */ |
| 51 | 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */ |
| 52 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */ |
| 53 | 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */ |
| 54 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */ |
| 55 | 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */ |
| 56 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */ |
| 57 | // 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */ |
| 58 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */ |
| 59 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */ |
| 60 | 0x00,0x00,0x1F /* 60 - 62 */ |
| 61 | }; |
| 62 | |
| 63 | #endif |
| 64 | |
| 65 | |
| 66 | static void *smp_write_config_table(void *v) |
| 67 | { |
| 68 | struct mp_config_table *mc; |
| 69 | int bus_isa; |
| 70 | |
| 71 | /* Intialize the MP_Table */ |
| 72 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 73 | |
| 74 | mptable_init(mc, LOCAL_APIC_ADDR); |
| 75 | |
| 76 | /* |
| 77 | * Type 0: Processor Entries: |
| 78 | * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, |
| 79 | * CPU Signature (Stepping, Model, Family), |
| 80 | * Feature Flags |
| 81 | */ |
| 82 | smp_write_processors(mc); |
| 83 | |
| 84 | /* |
| 85 | * Type 1: Bus Entries: |
| 86 | * Bus ID, Bus Type |
| 87 | */ |
| 88 | mptable_write_buses(mc, NULL, &bus_isa); |
| 89 | |
| 90 | /* |
| 91 | * Type 2: I/O APICs: |
| 92 | * APIC ID, Version, APIC Flags:EN, Address |
| 93 | */ |
| 94 | u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); |
| 95 | u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); |
| 96 | |
| 97 | smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); |
| 98 | |
| 99 | /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 100 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 101 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
| 102 | |
| 103 | /* |
| 104 | * Type 3: I/O Interrupt Table Entries: |
| 105 | * Int Type, Int Polarity, Int Level, Source Bus ID, |
| 106 | * Source Bus IRQ, Dest APIC ID, Dest PIN# |
| 107 | */ |
| 108 | |
| 109 | mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); |
| 110 | |
| 111 | /* PCI interrupts are level triggered, and are |
| 112 | * associated with a specific bus/device/function tuple. |
| 113 | */ |
| 114 | #define PCI_INT(bus, dev, int_sign, pin) \ |
| 115 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) |
| 116 | |
| 117 | |
| 118 | /* SMBUS / ACPI */ |
| 119 | PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); |
| 120 | |
| 121 | /* SD card */ |
| 122 | PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]); |
| 123 | |
| 124 | /* USB */ |
| 125 | PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); |
| 126 | PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); |
| 127 | PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); |
| 128 | PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); |
| 129 | PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); |
| 130 | PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); |
| 131 | PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); |
| 132 | |
| 133 | /* SATA */ |
| 134 | PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); |
| 135 | |
| 136 | /* on board NIC & Slot PCIE */ |
| 137 | PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); |
| 138 | PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); |
| 139 | |
| 140 | |
| 141 | /* GPP0 */ |
| 142 | PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3 |
| 143 | /* GPP1 */ |
| 144 | PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2 |
| 145 | /* GPP2 */ |
| 146 | PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1 |
| 147 | /* GPP3 */ |
| 148 | PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI |
| 149 | /* GPP4 */ |
| 150 | PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI |
| 151 | |
| 152 | IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); |
| 153 | IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); |
| 154 | |
| 155 | /* There is no extension information... */ |
| 156 | |
| 157 | /* Compute the checksums */ |
| 158 | return mptable_finalize(mc); |
| 159 | } |
| 160 | |
| 161 | unsigned long write_smp_table(unsigned long addr) |
| 162 | { |
| 163 | void *v; |
| 164 | v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ |
| 165 | return (unsigned long)smp_write_config_table(v); |
| 166 | } |