Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mp.h |
| 6 | * |
| 7 | * Platform Specific common header file |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem) |
| 12 | * @e \$Revision: 37402 $ @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $ |
| 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _MP_H_ |
| 48 | #define _MP_H_ |
| 49 | |
| 50 | /*---------------------------------------------------------------------------- |
| 51 | * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) |
| 52 | * |
| 53 | *---------------------------------------------------------------------------- |
| 54 | */ |
| 55 | |
| 56 | /*----------------------------------------------------------------------------- |
| 57 | * DEFINITIONS AND MACROS |
| 58 | * |
| 59 | *----------------------------------------------------------------------------- |
| 60 | */ |
| 61 | |
| 62 | /*---------------------------------------------------------------------------- |
| 63 | * TYPEDEFS, STRUCTURES, ENUMS |
| 64 | * |
| 65 | *---------------------------------------------------------------------------- |
| 66 | */ |
| 67 | /// Type of an entry for Dram Term table |
| 68 | typedef struct { |
| 69 | UINT32 Speed; ///< BitMap for the supported speed |
| 70 | UINT8 Dimms; ///< BitMap for supported number of dimm |
| 71 | UINT8 QR_Dimms; ///< BitMap for supported number of QR dimm |
| 72 | UINT8 DramTerm; ///< DramTerm value |
| 73 | UINT8 QR_DramTerm; ///< DramTerm value for QR |
| 74 | UINT8 DynamicDramTerm; ///< Dynamic DramTerm |
| 75 | } DRAM_TERM_ENTRY; |
| 76 | |
| 77 | /// Type of an entry for POR speed limit table |
| 78 | typedef struct { |
| 79 | UINT16 DIMMRankType; ///< Bitmap of Ranks |
| 80 | UINT8 Dimms; ///< Number of dimm |
| 81 | UINT16 SpeedLimit_1_5V; ///< POR speed limit for 1.5V |
| 82 | UINT16 SpeedLimit_1_35V; ///< POR speed limit for 1.35V |
| 83 | UINT16 SpeedLimit_1_25V; ///< POR speed limit for 1.25V |
| 84 | } POR_SPEED_LIMIT; |
| 85 | |
| 86 | /// UDIMM&RDIMM Max. Frequency |
| 87 | typedef union { |
| 88 | struct { ///< PSCFG_MAXFREQ_ENTRY |
| 89 | UINT16 DimmPerCh:3; ///< Dimm slot per chanel |
| 90 | UINT16 Dimms:3; ///< Number of Dimms on a channel |
| 91 | UINT16 SR:3; ///< Number of single-rank Dimm |
| 92 | UINT16 DR:3; ///< Number of dual-rank Dimm |
| 93 | UINT16 QR:4; ///< Number of quad-rank Dimm |
| 94 | UINT16 Speed1_5V; ///< Speed limit with voltage 1.5V |
| 95 | UINT16 Speed1_35V; ///< Speed limit with voltage 1.35V |
| 96 | UINT16 Speed1_25V; ///< Speed limit with voltage 1.25V |
| 97 | } _MAXFREQ_ENTRY; |
| 98 | struct { |
| 99 | UINT16 CDN; ///< Condition |
| 100 | UINT16 Speed[3]; ///< Speed limit |
| 101 | } MAXFREQ_ENTRY; |
| 102 | } PSCFG_MAXFREQ_ENTRY; |
| 103 | |
| 104 | /// LRDIMM Max. Frequency |
| 105 | typedef union { |
| 106 | struct { ///< PSCFG_LR_MAXFREQ_ENTRY |
| 107 | UINT16 DimmPerCh:3; ///< Dimm slot per chanel |
| 108 | UINT16 Dimms:3; ///< Number of Dimms on a channel |
| 109 | UINT16 LR:10; ///< Number of LR-DIMM |
| 110 | UINT16 Speed1_5V; ///< Speed limit with voltage 1.5V |
| 111 | UINT16 Speed1_35V; ///< Speed limit with voltage 1.35V |
| 112 | UINT16 Speed1_25V; ///< Speed limit with voltage 1.25V |
| 113 | } _LR_MAXFREQ_ENTRY; |
| 114 | struct { |
| 115 | UINT16 CDN; |
| 116 | UINT16 Speed[3]; |
| 117 | } LR_MAXFREQ_ENTRY; |
| 118 | } PSCFG_LR_MAXFREQ_ENTRY; |
| 119 | |
| 120 | /// UDIMM&RDIMM RttNom and RttWr |
| 121 | typedef struct { |
| 122 | UINT64 DimmPerCh:8; ///< Dimm slot per chanel |
| 123 | UINT64 DDRrate:32; ///< Bitmap of DDR rate |
| 124 | UINT64 VDDIO:4; ///< Bitmap of VDDIO |
| 125 | UINT64 Dimm0:4; ///< Bitmap of rank type of Dimm0 |
| 126 | UINT64 Dimm1:4; ///< Bitmap of rank type of Dimm1 |
| 127 | UINT64 Dimm2:4; ///< Bitmap of rank type of Dimm2 |
| 128 | UINT64 Dimm:3; ///< Bitmap of rank type of Dimm |
| 129 | UINT64 Rank:5; ///< Bitmap of rank |
| 130 | UINT8 RttNom:3; ///< Dram term |
| 131 | UINT8 RttWr:5; ///< Dynamic dram term |
| 132 | } PSCFG_RTT_ENTRY; |
| 133 | |
| 134 | /// LRDIMM RttNom and RttWr |
| 135 | typedef struct { |
| 136 | UINT64 DimmPerCh:8; ///< Dimm slot per chanel |
| 137 | UINT64 DDRrate:32; ///< Bitmap of DDR rate |
| 138 | UINT64 VDDIO:4; ///< Bitmap of VDDIO |
| 139 | UINT64 Dimm0:4; ///< Dimm0 population |
| 140 | UINT64 Dimm1:4; ///< Dimm1 population |
| 141 | UINT64 Dimm2:12; ///< Dimm2 population |
| 142 | UINT8 RttNom:3; ///< Dram term |
| 143 | UINT8 RttWr:5; ///< Dynamic dram term |
| 144 | } PSCFG_LR_RTT_ENTRY; |
| 145 | |
| 146 | /// UDIMM&RDIMM&LRDIMM ODT pattern OF 1 DPC |
| 147 | typedef struct { |
| 148 | UINT16 Dimm0; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM |
| 149 | UINT32 RdODTCSHigh; ///< RdODTCSHigh |
| 150 | UINT32 RdODTCSLow; ///< RdODTCSLow |
| 151 | UINT32 WrODTCSHigh; ///< WrODTCSHigh |
| 152 | UINT32 WrODTCSLow; ///< WrODTCSLow |
| 153 | } PSCFG_1D_ODTPAT_ENTRY; |
| 154 | |
| 155 | /// UDIMM&RDIMM&LRDIMM ODT pattern OF 2 DPC |
| 156 | typedef struct { |
| 157 | UINT16 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM |
| 158 | UINT16 Dimm1:12; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM |
| 159 | UINT32 RdODTCSHigh; ///< RdODTCSHigh |
| 160 | UINT32 RdODTCSLow; ///< RdODTCSLow |
| 161 | UINT32 WrODTCSHigh; ///< WrODTCSHigh |
| 162 | UINT32 WrODTCSLow; ///< WrODTCSLow |
| 163 | } PSCFG_2D_ODTPAT_ENTRY; |
| 164 | |
| 165 | /// UDIMM&RDIMM&LRDIMM ODT pattern OF 3 DPC |
| 166 | typedef struct { |
| 167 | UINT16 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM |
| 168 | UINT16 Dimm1:4; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM |
| 169 | UINT16 Dimm2:8; ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM |
| 170 | UINT32 RdODTCSHigh; ///< RdODTCSHigh |
| 171 | UINT32 RdODTCSLow; ///< RdODTCSLow |
| 172 | UINT32 WrODTCSHigh; ///< WrODTCSHigh |
| 173 | UINT32 WrODTCSLow; ///< WrODTCSLow |
| 174 | } PSCFG_3D_ODTPAT_ENTRY; |
| 175 | |
| 176 | /// UDIMM&RDIMM&LRDIMM SlowMode, AddrTmgCtl and ODC |
| 177 | typedef struct { |
| 178 | UINT64 DimmPerCh:8; ///< Dimm slot per channel |
| 179 | UINT64 DDRrate:32; ///< Bitmap of DDR rate |
| 180 | UINT64 VDDIO:4; ///< Bitmap of VDDIO |
| 181 | UINT64 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM |
| 182 | UINT64 Dimm1:4; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM |
| 183 | UINT64 Dimm2:11; ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM |
| 184 | UINT64 SlowMode:1; ///< SlowMode |
| 185 | UINT32 AddTmgCtl; ///< AddTmgCtl |
| 186 | UINT32 ODC; ///< ODC |
| 187 | } PSCFG_SAO_ENTRY; |
| 188 | |
| 189 | /// UDIMM&RDIMM MR0[WR] |
| 190 | typedef struct { |
| 191 | UINT8 Timing; ///< Fn2_22C_dct[1:0][Twr] |
| 192 | UINT8 Value; ///< MR0[WR] : bit0 - bit2 available |
| 193 | } PSCFG_MR0WR_ENTRY; |
| 194 | |
| 195 | /// UDIMM&RDIMM MR0[CL] |
| 196 | typedef struct { |
| 197 | UINT8 Timing; ///< Fn2_200_dct[1:0][Tcl] |
| 198 | UINT8 Value:3; ///< MR0[CL] : bit0 - bit2 CL[3:1] |
| 199 | UINT8 Value1:5; ///< MR0[CL] : bit3 CL[0] |
| 200 | } PSCFG_MR0CL_ENTRY; |
| 201 | |
| 202 | /// UDIMM&RDIMM MR2[IBT] |
| 203 | typedef struct { |
| 204 | UINT64 DimmPerCh:4; ///< Dimm slot per channel |
| 205 | UINT64 DDRrate:32; ///< Bitmap of DDR rate |
| 206 | UINT64 VDDIO:4; ///< Bitmap of VDDIO |
| 207 | UINT64 Dimm0:4; ///< Bitmap of dimm0 rank type |
| 208 | UINT64 Dimm1:4; ///< Bitmap of dimm1 rank type |
| 209 | UINT64 Dimm2:4; ///< Bitmap of dimm2 rank type |
| 210 | UINT64 Dimm:4; ///< Bitmap of rank type of Dimm |
| 211 | UINT64 NumOfReg:4; ///< Number of registers |
| 212 | UINT64 IBT:4; ///< MR2[IBT] value |
| 213 | } PSCFG_MR2IBT_ENTRY; |
| 214 | |
| 215 | /// UDIMM&RDIMM&LRDIMM Operating Speed |
| 216 | typedef struct { |
| 217 | UINT32 DDRrate; ///< Bitmap of DDR rate |
| 218 | UINT8 OPSPD; ///< RC10[OperatingSpeed] |
| 219 | } PSCFG_OPSPD_ENTRY; |
| 220 | |
| 221 | /// LRDIMM IBT |
| 222 | typedef struct { |
| 223 | UINT64 DimmPerCh:4; ///< Dimm slot per channel |
| 224 | UINT64 DDRrate:32; ///< Bitmap of DDR rate |
| 225 | UINT64 VDDIO:4; ///< Bitmap of VDDIO |
| 226 | UINT64 Dimm0:4; ///< Dimm0 population |
| 227 | UINT64 Dimm1:4; ///< Dimm1 population |
| 228 | UINT64 Dimm2:4; ///< Dimm2 population |
| 229 | UINT64 F0RC8:3; ///< F0RC8 |
| 230 | UINT64 F1RC0:3; ///< F1RC0 |
| 231 | UINT64 F1RC1:3; ///< F1RC1 |
| 232 | UINT64 F1RC2:3; ///< F1RC2 |
| 233 | } PSCFG_L_IBT_ENTRY; |
| 234 | |
| 235 | /// LRDIMM F0RC13[NumPhysicalRanks] |
| 236 | typedef struct { |
| 237 | UINT8 NumRanks:3; ///< NumRanks |
| 238 | UINT8 NumPhyRanks:5; ///< NumPhyRanks |
| 239 | } PSCFG_L_NPR_ENTRY; |
| 240 | |
| 241 | /// LRDIMM F0RC13[NumLogicalRanks] |
| 242 | typedef struct { |
| 243 | UINT16 NumPhyRanks:3; ///< NumPhyRanks |
| 244 | UINT16 DramCap:4; ///< DramCap |
| 245 | UINT16 NumDimmSlot:9; ///< NumDimmSlot |
| 246 | UINT8 NumLogRanks; ///< NumLogRanks |
| 247 | } PSCFG_L_NLR_ENTRY; |
| 248 | |
| 249 | /// Platform specific configuration types |
| 250 | typedef enum { |
| 251 | PSCFG_MAXFREQ, ///< PSCFG_MAXFREQ |
| 252 | PSCFG_LR_MAXFREQ, ///< PSCFG_LR_MAXFREQ |
| 253 | PSCFG_RTT, ///< PSCFG_RTT |
| 254 | PSCFG_LR_RTT, ///< PSCFG_LR_RTT |
| 255 | PSCFG_ODT_PAT_1D, ///< PSCFG_ODT_PAT_1D |
| 256 | PSCFG_ODT_PAT_2D, ///< PSCFG_ODT_PAT_2D |
| 257 | PSCFG_ODT_PAT_3D, ///< PSCFG_ODT_PAT_3D |
| 258 | PSCFG_LR_ODT_PAT_1D, ///< PSCFG_LR_ODT_PAT_1D |
| 259 | PSCFG_LR_ODT_PAT_2D, ///< PSCFG_LR_ODT_PAT_2D |
| 260 | PSCFG_LR_ODT_PAT_3D, ///< PSCFG_LR_ODT_PAT_3D |
| 261 | PSCFG_SAO, ///< PSCFG_SAO |
| 262 | PSCFG_LR_SAO, ///< PSCFG_LR_SAO |
| 263 | PSCFG_MR0WR, ///< PSCFG_MR0WR |
| 264 | PSCFG_MR0CL, ///< PSCFG_MR0CL |
| 265 | PSCFG_RC2IBT, ///< PSCFG_RC2IBT |
| 266 | PSCFG_RC10OPSPD, ///< PSCFG_RC10OPSPD |
| 267 | PSCFG_LR_IBT, ///< PSCFG_LR_IBT |
| 268 | PSCFG_LR_NPR, ///< PSCFG_LR_NPR |
| 269 | PSCFG_LR_NLR, ///< PSCFG_LR_NLR |
| 270 | |
| 271 | // The type of general table entries could be added between |
| 272 | // PSCFG_GEN_START and PSCFG_GEN_END so that the PSCGen routine |
| 273 | // is able to look for the entries per the PSCType. |
| 274 | PSCFG_GEN_START, ///< PSCFG_GEN_START |
| 275 | PSCFG_CLKDIS, ///< PSCFG_CLKDIS |
| 276 | PSCFG_CKETRI, ///< PSCFG_CKETRI |
| 277 | PSCFG_ODTTRI, ///< PSCFG_ODTTRI |
| 278 | PSCFG_CSTRI, ///< PSCFG_CSTRI |
| 279 | PSCFG_GEN_END ///< PSCFG_GEN_END |
| 280 | } PSCFG_TYPE; |
| 281 | |
| 282 | /// Dimm types |
| 283 | typedef enum { |
| 284 | UDIMM_TYPE = 0x01, ///< UDIMM_TYPE |
| 285 | RDIMM_TYPE = 0x02, ///< RDIMM_TYPE |
| 286 | SODIMM_TYPE = 0x04, ///< SODIMM_TYPE |
| 287 | LRDIMM_TYPE = 0x08, ///< LRDIMM_TYPE |
| 288 | DT_DONT_CARE = 0xFF ///< DT_DONT_CARE |
| 289 | } DIMM_TYPE; |
| 290 | |
| 291 | /// Number of Dimm |
| 292 | typedef enum { |
| 293 | _1DIMM = 0x01, ///< _1DIMM |
| 294 | _2DIMM = 0x02, ///< _2DIMM |
| 295 | _3DIMM = 0x04, ///< _3DIMM |
| 296 | _4DIMM = 0x08, ///< _4DIMM |
| 297 | NOD_DONT_CARE = 0xFF ///< NOD_DONT_CARE |
| 298 | } NOD_SUPPORTED; |
| 299 | |
| 300 | /// Table header related definitions |
| 301 | typedef struct { |
| 302 | PSCFG_TYPE PSCType; ///< PSC Type |
| 303 | DIMM_TYPE DimmType; ///< Dimm Type |
| 304 | NOD_SUPPORTED NumOfDimm; ///< Numbef of dimm |
| 305 | CPU_LOGICAL_ID LogicalCpuid; ///< Logical Cpuid |
| 306 | UINT8 PackageType; ///< Package Type |
| 307 | TECHNOLOGY_TYPE TechType; ///< Technology type |
| 308 | } PSC_TBL_HEADER; |
| 309 | |
| 310 | /// Table entry |
| 311 | typedef struct { |
| 312 | PSC_TBL_HEADER Header; ///< PSC_TBL_HEADER |
| 313 | UINT8 TableSize; ///< Table size |
| 314 | VOID *TBLPtr; ///< Pointer of the table |
| 315 | } PSC_TBL_ENTRY; |
| 316 | |
| 317 | #define NOD_DONT_CARE 0xFF |
| 318 | #define PT_DONT_CARE 0xFF |
| 319 | #define NP 1 |
| 320 | #define V1_5 1 |
| 321 | #define V1_35 2 |
| 322 | #define V1_25 4 |
| 323 | #define VOLT_ALL (V1_5 | V1_35 | V1_25) |
| 324 | #define DIMM_SR 2 |
| 325 | #define DIMM_DR 4 |
| 326 | #define DIMM_QR 8 |
| 327 | #define DIMM_LR 2 |
| 328 | #define R0 1 |
| 329 | #define R1 2 |
| 330 | #define R2 4 |
| 331 | #define R3 8 |
| 332 | /*---------------------------------------------------------------------------- |
| 333 | * FUNCTIONS PROTOTYPE |
| 334 | * |
| 335 | *---------------------------------------------------------------------------- |
| 336 | */ |
| 337 | |
| 338 | AGESA_STATUS |
| 339 | MemPConstructPsUDef ( |
| 340 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 341 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 342 | IN OUT MEM_PS_BLOCK *PsPtr |
| 343 | ); |
| 344 | |
| 345 | BOOLEAN |
| 346 | MemPGetDramTerm ( |
| 347 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 348 | IN UINT8 ArraySize, |
| 349 | IN CONST DRAM_TERM_ENTRY *DramTermPtr |
| 350 | ); |
| 351 | |
| 352 | AGESA_STATUS |
| 353 | MemPConstructPsSHy3 ( |
| 354 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 355 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 356 | IN OUT MEM_PS_BLOCK *PsPtr |
| 357 | ); |
| 358 | |
| 359 | AGESA_STATUS |
| 360 | MemPConstructPsUHy3 ( |
| 361 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 362 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 363 | IN OUT MEM_PS_BLOCK *PsPtr |
| 364 | ); |
| 365 | |
| 366 | AGESA_STATUS |
| 367 | MemPConstructPsRHy3 ( |
| 368 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 369 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 370 | IN OUT MEM_PS_BLOCK *PsPtr |
| 371 | ); |
| 372 | |
| 373 | AGESA_STATUS |
| 374 | MemPConstructPsUC32_3 ( |
| 375 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 376 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 377 | IN OUT MEM_PS_BLOCK *PsPtr |
| 378 | ); |
| 379 | |
| 380 | AGESA_STATUS |
| 381 | MemPConstructPsRC32_3 ( |
| 382 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 383 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 384 | IN OUT MEM_PS_BLOCK *PsPtr |
| 385 | ); |
| 386 | |
| 387 | |
| 388 | AGESA_STATUS |
| 389 | MemPConstructPsSDr3 ( |
| 390 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 391 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 392 | IN OUT MEM_PS_BLOCK *PsPtr |
| 393 | ); |
| 394 | |
| 395 | AGESA_STATUS |
| 396 | MemPConstructPsUDr3 ( |
| 397 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 398 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 399 | IN OUT MEM_PS_BLOCK *PsPtr |
| 400 | ); |
| 401 | |
| 402 | AGESA_STATUS |
| 403 | MemPConstructPsRDr3 ( |
| 404 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 405 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 406 | IN OUT MEM_PS_BLOCK *PsPtr |
| 407 | ); |
| 408 | |
| 409 | AGESA_STATUS |
| 410 | MemPConstructPsUDA3 ( |
| 411 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 412 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 413 | IN OUT MEM_PS_BLOCK *PsPtr |
| 414 | ); |
| 415 | |
| 416 | AGESA_STATUS |
| 417 | MemPConstructPsSNi3 ( |
| 418 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 419 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 420 | IN OUT MEM_PS_BLOCK *PsPtr |
| 421 | ); |
| 422 | |
| 423 | AGESA_STATUS |
| 424 | MemPConstructPsUNi3 ( |
| 425 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 426 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 427 | IN OUT MEM_PS_BLOCK *PsPtr |
| 428 | ); |
| 429 | |
| 430 | AGESA_STATUS |
| 431 | MemPConstructPsSRb3 ( |
| 432 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 433 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 434 | IN OUT MEM_PS_BLOCK *PsPtr |
| 435 | ); |
| 436 | |
| 437 | AGESA_STATUS |
| 438 | MemPConstructPsURb3 ( |
| 439 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 440 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 441 | IN OUT MEM_PS_BLOCK *PsPtr |
| 442 | ); |
| 443 | |
| 444 | AGESA_STATUS |
| 445 | MemPConstructPsSPh3 ( |
| 446 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 447 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 448 | IN OUT MEM_PS_BLOCK *PsPtr |
| 449 | ); |
| 450 | |
| 451 | AGESA_STATUS |
| 452 | MemPConstructPsUPh3 ( |
| 453 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 454 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 455 | IN OUT MEM_PS_BLOCK *PsPtr |
| 456 | ); |
| 457 | |
| 458 | AGESA_STATUS |
| 459 | MemPConstructPsSDA3 ( |
| 460 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 461 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 462 | IN OUT MEM_PS_BLOCK *PsPtr |
| 463 | ); |
| 464 | |
| 465 | AGESA_STATUS |
| 466 | MemPConstructPsSDA2 ( |
| 467 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 468 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 469 | IN OUT MEM_PS_BLOCK *PsPtr |
| 470 | ); |
| 471 | |
| 472 | AGESA_STATUS |
| 473 | MemPConstructPsSLN3 ( |
| 474 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 475 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 476 | IN OUT MEM_PS_BLOCK *PsPtr |
| 477 | ); |
| 478 | |
| 479 | AGESA_STATUS |
| 480 | MemPConstructPsULN3 ( |
| 481 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 482 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 483 | IN OUT MEM_PS_BLOCK *PsPtr |
| 484 | ); |
| 485 | |
| 486 | AGESA_STATUS |
| 487 | MemPConstructPsRLN3 ( |
| 488 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 489 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 490 | IN OUT MEM_PS_BLOCK *PsPtr |
| 491 | ); |
| 492 | |
| 493 | AGESA_STATUS |
| 494 | MemPConstructPsSON3 ( |
| 495 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 496 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 497 | IN OUT MEM_PS_BLOCK *PsPtr |
| 498 | ); |
| 499 | |
| 500 | AGESA_STATUS |
| 501 | MemPConstructPsUON3 ( |
| 502 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 503 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 504 | IN OUT MEM_PS_BLOCK *PsPtr |
| 505 | ); |
| 506 | |
| 507 | UINT16 |
| 508 | MemPGetPorFreqLimit ( |
| 509 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 510 | IN UINT8 FreqLimitSize, |
| 511 | IN CONST POR_SPEED_LIMIT *FreqLimitPtr |
| 512 | ); |
| 513 | |
| 514 | VOID |
| 515 | MemPGetPORFreqLimitDef ( |
| 516 | IN OUT MEM_NB_BLOCK *NBPtr |
| 517 | ); |
| 518 | |
| 519 | BOOLEAN |
| 520 | MemPPSCFlow ( |
| 521 | IN OUT MEM_NB_BLOCK *NBPtr |
| 522 | ); |
| 523 | |
| 524 | VOID |
| 525 | MemPConstructRankTypeMap ( |
| 526 | IN UINT16 Dimm0, |
| 527 | IN UINT16 Dimm1, |
| 528 | IN UINT16 Dimm2, |
| 529 | IN OUT UINT16 *RankTypeInTable |
| 530 | ); |
| 531 | |
| 532 | BOOLEAN |
| 533 | MemPIsIdSupported ( |
| 534 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 535 | IN CPU_LOGICAL_ID LogicalId, |
| 536 | IN UINT8 PackageType |
| 537 | ); |
| 538 | |
| 539 | UINT16 |
| 540 | MemPGetPsRankType ( |
| 541 | IN CH_DEF_STRUCT *CurrentChannel |
| 542 | ); |
| 543 | |
| 544 | BOOLEAN |
| 545 | MemPRecPSCFlow ( |
| 546 | IN OUT MEM_NB_BLOCK *NBPtr |
| 547 | ); |
| 548 | |
| 549 | VOID |
| 550 | MemPRecConstructRankTypeMap ( |
| 551 | IN UINT16 Dimm0, |
| 552 | IN UINT16 Dimm1, |
| 553 | IN UINT16 Dimm2, |
| 554 | IN OUT UINT16 *RankTypeInTable |
| 555 | ); |
| 556 | |
| 557 | BOOLEAN |
| 558 | MemPRecIsIdSupported ( |
| 559 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 560 | IN CPU_LOGICAL_ID LogicalId, |
| 561 | IN UINT8 PackageType |
| 562 | ); |
| 563 | |
| 564 | UINT16 |
| 565 | MemPRecGetPsRankType ( |
| 566 | IN CH_DEF_STRUCT *CurrentChannel |
| 567 | ); |
| 568 | |
| 569 | #endif /* _MP_H_ */ |