Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mn.h |
| 6 | * |
| 7 | * Common Northbridge |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12 | * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _MN_H_ |
| 48 | #define _MN_H_ |
| 49 | |
| 50 | /*---------------------------------------------------------------------------- |
| 51 | * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) |
| 52 | * |
| 53 | *---------------------------------------------------------------------------- |
| 54 | */ |
| 55 | |
| 56 | /*----------------------------------------------------------------------------- |
| 57 | * DEFINITIONS AND MACROS |
| 58 | * |
| 59 | *----------------------------------------------------------------------------- |
| 60 | */ |
| 61 | #define _4GB_RJ16 ((UINT32)4 << (30 - 16)) |
| 62 | #define DCT_ACCESS_WRITE (UINT32) 0x40000000 |
| 63 | #define MTRR_VALID 11 |
| 64 | #define THERMAL_OPT 31 |
| 65 | |
| 66 | #define NB_ACCESS 0 |
| 67 | #define DCT_PHY_ACCESS 1 |
| 68 | #define DCT_EXTRA 2 |
| 69 | |
| 70 | #define DCT_PHY_DIRECT 0xF1 |
| 71 | |
| 72 | #define VT_MSK_VALUE 0 |
| 73 | #define VT_ARRAY 1 |
| 74 | /*--------------------------------------------- |
| 75 | * TSEFO - Type Start End Function Offset |
| 76 | * |
| 77 | * 31:30 Type of access (2-bits) |
| 78 | * 29:29 Special (1-bit) |
| 79 | * 28:28 Phy Direct (1-bit) |
| 80 | * 27:27 Whole Register Access (1-bit) |
| 81 | * 26:26 Linked (1-bit) |
| 82 | * 25:21 Start bit (5-bits) |
| 83 | * 20:16 End bit (5-bits) |
| 84 | * 15:00 Function_Offset/Index (16-bits) |
| 85 | *--------------------------------------------- |
| 86 | */ |
| 87 | typedef UINT32 TSEFO; |
| 88 | |
| 89 | /** |
| 90 | MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex): |
| 91 | |
| 92 | @param[in] TableName |
| 93 | @param[in] BitFieldIndex |
| 94 | @param[in] a Type of access. |
| 95 | @param[in] b Index of register (can be in Function_Offset format). |
| 96 | @param[in] c Highest bit of the bit field. |
| 97 | @param[in] d Lowest bit of the bit field. |
| 98 | |
| 99 | @return TSEFO Access params encrypted in TSEFO format. |
| 100 | --*/ |
| 101 | #define MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex) \ |
| 102 | TableName[BitFieldIndex] = ( \ |
| 103 | (a == DCT_PHY_DIRECT) ? ( \ |
| 104 | (((UINT32) DCT_PHY_ACCESS) << 30) | (((UINT32) 1) << 28) | (((UINT32) b) & 0xFFFF) | (\ |
| 105 | ((c == 15) && (d == 0)) ? ( \ |
| 106 | (((UINT32) 1) << 27) | (((UINT32) b) & 0xF0000) \ |
| 107 | ) : ( \ |
| 108 | (c >= d) ? ( \ |
| 109 | (((UINT32) c) << 21) | (((UINT32) d) << 16) \ |
| 110 | ) : ( \ |
| 111 | (((UINT32) d) << 21) | (((UINT32) c) << 16) \ |
| 112 | ) \ |
| 113 | ) \ |
| 114 | ) \ |
| 115 | ) : ( \ |
| 116 | (((UINT32) a) << 30) | (((UINT32) b) & 0xFFFFFFF) | ( \ |
| 117 | (((UINT32) b) >> 16) ? ( \ |
| 118 | (((UINT32) 1) << 29) \ |
| 119 | ) : ( \ |
| 120 | (c >= d) ? ( \ |
| 121 | (((UINT32) c) << 21) | (((UINT32) d) << 16) \ |
| 122 | ) : ( \ |
| 123 | (((UINT32) d) << 21) | (((UINT32) c) << 16) \ |
| 124 | ) \ |
| 125 | ) \ |
| 126 | ) \ |
| 127 | ) \ |
| 128 | ) |
| 129 | |
| 130 | /** |
| 131 | LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex): |
| 132 | This is one way link: any write to LowerBitFieldIndex would write to HigherBitFieldIndex, |
| 133 | but NOT the other way around. |
| 134 | Requirement: LowerBitFieldIndex must be declared *right* before HigherBitFieldIndex. |
| 135 | |
| 136 | @param[in] TableName |
| 137 | @param[in] LowerBitFieldIndex |
| 138 | @param[in] HigherBitFieldIndex |
| 139 | |
| 140 | @return TSEFO Access params encrypted in TSEFO format. |
| 141 | --*/ |
| 142 | #define LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex) { \ |
| 143 | ASSERT (LowerBitFieldIndex == (HigherBitFieldIndex - 1)) ; \ |
| 144 | TableName[LowerBitFieldIndex] = TableName[LowerBitFieldIndex] | (((UINT32) 1) << 26); \ |
| 145 | } |
| 146 | |
| 147 | #define TSEFO_TYPE(x) ((UINT8) (((UINT32) (x) >> 30) & 0x03)) |
| 148 | #define TSEFO_START(x) ((UINT8) (((UINT32) (x) >> 21) & 0x1F)) |
| 149 | #define TSEFO_END(x) ((UINT8) (((UINT32) (x) >> 16) & 0x1F)) |
| 150 | #define TSEFO_OFFSET(x) ((UINT32) (x) & 0xFFFF) |
| 151 | #define TSEFO_LINKED(x) ((UINT8) (((UINT32) (x) >> 26) & 0x01)) |
| 152 | #define TSEFO_DIRECT_EN(x) ((UINT8) (((UINT32) (x) >> 28) & 0x01)) |
| 153 | #define TSEFO_WHOLE_REG_ACCESS(x) ((UINT8) (((UINT32) (x) >> 27) & 0x01)) |
| 154 | #define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y)) |
| 155 | #define _NOT_USED_ 0 |
| 156 | |
| 157 | /* */ |
| 158 | #define B0_DLY 0 |
| 159 | #define B1_DLY 1 |
| 160 | #define B2_DLY 2 |
| 161 | #define B3_DLY 3 |
| 162 | #define B4_DLY 4 |
| 163 | #define B5_DLY 5 |
| 164 | #define B6_DLY 6 |
| 165 | #define B7_DLY 7 |
| 166 | #define ECC_DLY 8 |
| 167 | |
| 168 | #define DDR2_TRAIN_FLOW 0 |
| 169 | #define DDR3_TRAIN_FLOW 1 |
| 170 | |
| 171 | // |
| 172 | // Minimum Data Eye width in consecutive 32nds of a UI of |
| 173 | // valid data |
| 174 | // |
| 175 | #define MIN_RD_DATAEYE_WIDTH_NB 4 |
| 176 | #define MIN_WR_DATAEYE_WIDTH_NB 4 |
| 177 | |
| 178 | // |
| 179 | // RELIABLE READ/WRITE MODE DEFINITIONS |
| 180 | // |
| 181 | #define PRECHARGE_ALL_BANKS 0xFF ///< Use to specify PrechargeAll Command to Precharge Cmd Function |
| 182 | #define CMD_TGT_A 0x00 ///< Issue Commands to Command Target A |
| 183 | #define CMD_TGT_AB 0x01 ///< Issue Commands to Command Targets A and B |
| 184 | #define CMD_TYPE_READ 0x00 ///< Read Command |
| 185 | #define CMD_TYPE_WRITE 0x01 ///< Write Command |
| 186 | #define CMD_TYPE_WR_RD 0x02 ///< Alternating Write and Read Commands |
| 187 | #define CPG_BANK_ADDRESS_A 0x0 ///< Dimm Bank address used in Reliable RD/RW mode training |
| 188 | #define CPG_BANK_ADDRESS_B 0x1 ///< Dimm Bank address used in Reliable RD/RW mode training |
| 189 | #define CPG_ROW_ADDRESS_A 0x0 ///< Dimm Row address used in Reliable RD/RW mode training |
| 190 | #define CPG_ROW_ADDRESS_B 0x0 ///< Dimm Row address used in Reliable RD/RW mode training |
| 191 | #define CPG_COL_ADDRESS_A 0x0 ///< Dimm Column address used in Reliable RD/RW mode training |
| 192 | #define CPG_COL_ADDRESS_B 0x0 ///< Dimm Column address used in Reliable RD/RW mode training |
| 193 | #define CPG_COMPARE_MASK_LOW 0x00000000 ///< Dram DQMask[31:0] used to mask comparison on reads. 1=ignore |
| 194 | #define CPG_COMPARE_MASK_HI 0x00000000 ///< Dram DQMask[63:32] used to mask comparison on reads. 1=ignore |
| 195 | #define CPG_COMPARE_MASK_ECC 0x00 ///< Dram EccMask used to mask comparison on reads. 1=ignore |
| 196 | #define PRBS_SEED_32 0x062221 ///< Data PRBS Seed |
| 197 | #define PRBS_SEED_64 0x066665 ///< Data PRBS Seed |
| 198 | #define PRBS_SEED_128 0x026666 ///< Data PRBS Seed |
| 199 | #define PRBS_SEED_256 0x044443 ///< Data PRBS Seed |
| 200 | |
| 201 | |
| 202 | /*---------------------------------------------------------------------------- |
| 203 | * TYPEDEFS, STRUCTURES, ENUMS |
| 204 | * |
| 205 | *---------------------------------------------------------------------------- |
| 206 | */ |
| 207 | |
| 208 | /// Structure for Reliable Read/Write Mode Data |
| 209 | /// These are values that may need to be referenced by the low level functions |
| 210 | /// during training and are initialized at the begining of a particular type of training. |
| 211 | typedef struct _RRW_SETTINGS { |
| 212 | UINT8 CmdTgt; ///< Value to program into CmdTgt |
| 213 | UINT8 TgtBankAddressA; ///< Target A Bank address |
| 214 | UINT32 TgtRowAddressA; ///< Target A Row address |
| 215 | UINT32 TgtColAddressA; ///< Target A Column address |
| 216 | UINT8 TgtBankAddressB; ///< Target B Bank address |
| 217 | UINT32 TgtRowAddressB; ///< Target B Row address |
| 218 | UINT32 TgtColAddressB; ///< Target B Column address |
| 219 | UINT32 CompareMaskLow; ///< Compare Mask Bits 31:0 |
| 220 | UINT32 CompareMaskHigh; ///< Compare Mask Bits 63:32 |
| 221 | UINT8 CompareMaskEcc; ///< Compare Mask Ecc |
| 222 | UINT32 DataPrbsSeed; ///< PRBS Seed value |
| 223 | } RRW_SETTINGS; |
| 224 | |
| 225 | /// DQS training related delays |
| 226 | typedef enum { |
| 227 | AccessRcvEnDly, ///< Receiver enable delay |
| 228 | AccessWrDatDly, ///< Write data delay |
| 229 | AccessRdDqsDly, ///< Read DQS delay |
| 230 | AccessWrDqsDly, ///< Write DQS delay |
| 231 | AccessPhRecDly ///< Phase recovery delay |
| 232 | } TRN_DLY_TYPE; |
| 233 | |
| 234 | /// Training patterns for position training |
| 235 | typedef enum { |
| 236 | POS_PATTERN_72B, ///< 72 bit pattern |
| 237 | POS_PATTERN_256B, ///< 256 bit pattern |
| 238 | } POS_TRN_PATTERN_TYPE; |
| 239 | |
| 240 | /// ODT mode |
| 241 | typedef enum { |
| 242 | MISSION_MODE, ///< ODT during mission mode |
| 243 | WRITE_LEVELING_MODE ///< ODT during write leveling |
| 244 | } ODT_MODE; |
| 245 | |
| 246 | /* |
| 247 | * DRBN - Dimm-Rank-Byte-Nibble |
| 248 | * 31:12 Reserved |
| 249 | * 11:09 Dimm (3-bits) |
| 250 | * 08 Rank (1-bit) |
| 251 | * 07:05 Reserved |
| 252 | * 04:01 Byte (4-bits) |
| 253 | * 00 Nibble (1-bit) |
| 254 | */ |
| 255 | typedef UINT32 DRBN; |
| 256 | #define MAKE_DRBN(dimm, rank, byte, nibble) ((((UINT32) (dimm)) << 9) | (((UINT32) (rank)) << 8) | \ |
| 257 | (((UINT32) (byte)) << 1) | ((UINT32) (nibble)) ) |
| 258 | #define DIMM_BYTE_ACCESS(dimm, byte) ((((UINT32) (dimm)) << 9) | (((UINT32) (byte)) << 1)) |
| 259 | #define CS_NBBL_ACCESS(cs, nibble) ((((UINT32) (cs)) << 8) | ((UINT32) (nibble))) |
| 260 | #define DRBN_DIMM(x) ((UINT8) (((UINT32) (x) >> 9) & 0x07)) |
| 261 | #define DRBN_RANK(x) ((UINT8) (((UINT32) (x) >> 8) & 0x01)) |
| 262 | #define DRBN_BYTE(x) ((UINT8) (((UINT32) (x) >> 1) & 0x0F)) |
| 263 | #define DRBN_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x01)) |
| 264 | |
| 265 | /* Dimm Type mask */ |
| 266 | #define DT_X4 0x01 |
| 267 | #define DT_X8 0x02 |
| 268 | #define DT_X16 0x04 |
| 269 | #define DT_SR 0x10 |
| 270 | #define DT_DR 0x20 |
| 271 | #define DT_QR 0x40 |
| 272 | |
| 273 | #define DT_ANY_X4 0x71 |
| 274 | #define DT_ANY_X8 0x72 |
| 275 | #define DT_ANY_X16 0x74 |
| 276 | #define DT_ANY_SR 0x17 |
| 277 | #define DT_ANY_DR 0x27 |
| 278 | #define DT_ANY_QR 0x47 |
| 279 | #define DT_ANY_SR_DR (DT_ANY_SR | DT_ANY_DR) |
| 280 | #define DT_ANY (DT_ANY_SR | DT_ANY_DR | DT_ANY_QR) |
| 281 | |
| 282 | /// Delay Scaling Info Struct - Describes number of delay increments per UI of a delay type |
| 283 | /// |
| 284 | typedef struct _TRN_DLY_PARMS { |
| 285 | UINT8 Min; ///< Minimum Value |
| 286 | UINT8 Max; ///< Maximum Value |
| 287 | UINT8 Mask; ///< Mask to be applied (i.e. 0xFF if adjustable by one, 0xFE if adjustable by 2, etc.) |
| 288 | } TRN_DLY_PARMS; |
| 289 | |
| 290 | /// Structure for certain data saving needed for DCT. |
| 291 | typedef struct { |
| 292 | UINT8 RcvEnDlyCounts[8]; ///< DQS Receiver Enable Delay counts |
| 293 | UINT32 PhRecReg[3]; ///< 3 Phase recovery control registers |
| 294 | } MEM_DCT_CACHE; |
| 295 | |
| 296 | /// Structure for table driven support. |
| 297 | typedef struct _MEM_TBL_ALIAS { |
| 298 | UINT8 time; ///< Modification time. |
| 299 | UINT8 node:4; ///< Node on which to make modification. |
| 300 | UINT8 dct:4; ///< DCT on which to make modification. |
| 301 | UINT8 dimm:4; ///< Dimm on which to make modification. |
| 302 | UINT8 attr:3; ///< Attribute of modification. |
| 303 | UINT8 vtype:1; ///< Flag indicating value type. |
| 304 | UINT32 bfindex; ///< Bit field index that need to be modified. |
| 305 | union { ///< Union is defined to easy select between single and multiple bytelane cases. |
| 306 | struct { ///< Sub-struct used for one bytelane value. |
| 307 | UINT16 bytelane:16; ///< Bytelane on which to make modification. |
| 308 | UINT32 value; ///< Modified value. |
| 309 | UINT8 reserved[3]; ///< Reserved for this purpose |
| 310 | } s; ///< single value to one or multiple bytelanes |
| 311 | UINT8 bytelanevalue[9]; ///< Array to specify individual bytelane values |
| 312 | } data; |
| 313 | } MEM_TABLE_ALIAS; |
| 314 | |
| 315 | /// Structure for Platform Specific Block. |
| 316 | typedef struct _MEM_PS_BLOCK { |
| 317 | UINT8 DramTerm; ///< Dram Term |
| 318 | UINT8 QR_DramTerm; ///< Dram Term for QR |
| 319 | UINT8 DynamicDramTerm; ///< Dynamic Dram Term |
| 320 | UINT8 NumOfReg[MAX_DIMMS_PER_CHANNEL]; ///< Number of registers on each RDIMM (From SPD) |
| 321 | UINT8 MR0WR; ///< MR0WR |
| 322 | UINT8 MR0CL31; ///< MR0[CL][3:1] |
| 323 | UINT8 MR0CL0; ///< MR0CL[0] |
| 324 | UINT8 RttNom[8]; ///< RttNom value for maximum 8 chipsels per channel |
| 325 | UINT8 RttWr[8]; ///< RttWr value for maximum 8 chipsels per channel |
| 326 | UINT8 F0RC8; ///< F0RC8 |
| 327 | UINT8 F1RC0; ///< F1RC0 |
| 328 | UINT8 F1RC1; ///< F1RC1 |
| 329 | UINT8 F1RC2; ///< F1RC2 |
| 330 | UINT8 RC10OpSpd; ///< RC10[OperatingSpeed] |
| 331 | UINT8 LrdimmRowAddrBits[MAX_DIMMS_PER_CHANNEL]; ///< Effective Row address bits used by LRDIMMS |
| 332 | /* PUBLIC functions */ |
| 333 | BOOLEAN (*MemPDoPs) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets Form factor info. |
| 334 | VOID (*MemPGetPORFreqLimit) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets the speed limit of a dimm population. |
| 335 | } MEM_PS_BLOCK; |
| 336 | |
| 337 | /// Structure parameters needed in frequency change of client NB. |
| 338 | typedef struct _MEM_FREQ_CHANGE_PARAM { |
| 339 | UINT16 PllLockTimeDefault; ///< Default PllLockTime |
| 340 | UINT8 RdPtrInit667orHigher; ///< RdPtrInit for frequency 667MHz and higher |
| 341 | UINT8 RdPtrInitLower667; ///< RdPtrInit for frequency lower than 667MHz |
| 342 | UINT8 NclkPeriodMul2x; ///< Multiplier for NclkPeriod in parial sum calculation x 2 |
| 343 | UINT8 MemClkPeriodMul2x; ///< Multiplier for MemClkPeriod in parial sum calculation x 2 |
| 344 | UINT8 SyncTimeMul4x; ///< Multiplier for SyncTime |
| 345 | UINT16 TDataProp800orHigher; ///< TDataProp for frequency 800MHz or higher |
| 346 | UINT16 TDataPropLower800; ///< TDataProp for frequency lower than 800MHz |
| 347 | } MEM_FREQ_CHANGE_PARAM; |
| 348 | |
| 349 | /// List for NB items that are supported |
| 350 | typedef enum { |
| 351 | SetSpareEn, ///< Sets spare enable |
| 352 | CheckSpareEn, ///< Spare enabled |
| 353 | SetDllShutDown, ///< Sets DllShutDown |
| 354 | CheckEccDLLPwrDnConfig, ///< Checks to determine if EccDLLPwrDnConf needs to be adjusted |
| 355 | DimmBasedOnSpeed, ///< Checks to determine if Dimm number needs to be adjusted based on speed |
| 356 | CheckMaxDramRate, ///< Checks to determine the maximum rate |
| 357 | Check1GAlign, ///< Checks to determine if 1 GB alignment is supported |
| 358 | DramModeBeforeDimmPres, ///< Check to determine if DRAM mode needs to be set before dimm presence |
| 359 | DramModeAfterDimmPres, ///< Check to determine if DRAM mode needs to be set after dimm presence |
| 360 | CheckClearOnDimmMirror, ///< Check to determine if we need to clear on DIMM mirror |
| 361 | CheckDisDllShutdownSR, ///< Check to determine if DisDllShutdown needs to be set |
| 362 | CheckMemClkCSPresent, ///< Check to determine if chipselect needs to be set based on disabled memclocks |
| 363 | CheckChangeAvgValue, ///< Check to determine if we need to change average value |
| 364 | CheckMaxRdDqsDlyPtr, ///< Check to determine change Max Rd Dqs Delay |
| 365 | CheckPhyFenceTraining, ///< Check to determine if we need to Phy Fence training |
| 366 | CheckGetMCTSysAddr, ///< Check to determine if we need to GetMCTSysAddr |
| 367 | CheckSendAllMRCmds, ///< Check to determine if we need to SendAllMRCmds |
| 368 | CheckFindPSOverideWithSocket, ///< Check to determine if we need to Find PSOveride With Socket |
| 369 | CheckFindPSDct, ///< Check to determine if we need to Find PSOveride With DCT |
| 370 | CheckODTControls, ///< Check to determine if we need to set ODT controls |
| 371 | CheckDummyCLRead, ///< Check to determine if an extra dummy read is required |
| 372 | CheckDllStdBy, ///< Check to determine if setting DLL stand by is required |
| 373 | CheckSlewWithMarginImprv, ///< Check to determine if setting of Slew With MarginImprv is required |
| 374 | CheckSlewWithoutMarginImprv, ///< Check to determine if setting of Slew Without MarginImprv is required |
| 375 | CheckDllSpeedUp, ///< Check to determine if setting of Dll SpeedUp is required |
| 376 | CheckDllRegDis, ///< Check to determine if setting of DLL Regulator Disable is required |
| 377 | FenceTrnBeforeDramInit, ///< Check to determine if fence training has been done before Dram init |
| 378 | WLSeedAdjust, ///< Check to determine if WL seed needs to be adjusted |
| 379 | UnifiedNbFence, ///< Check to determine if Phy fence is of Unified NB |
| 380 | AdjustTwr, ///< Check to determine if Twr needs to be adjusted |
| 381 | ChannelPDMode, ///< Check to determine if channel power down mode is the only that is supported |
| 382 | ForceEnMemHoleRemapping, ///< Check to determine if we need to force enabling memory hole remapping |
| 383 | AdjustTrdrdSD, ///< Check to determine if we need to adjust TrdrdSD |
| 384 | ReverseMaxRdLatTrain, ///< Check to determine if reverse (pass to fail) algorithm is supported for MaxRdLat training |
| 385 | SkipErrTrain, ///< Check to determine if skip error training is supported |
| 386 | DramSrHys, ///< Check to determine if DRAM SR hysteresis is supported |
| 387 | PchgPDMode, ///< Check to determine if Precharge powerdown mode is supported |
| 388 | EccByteTraining, ///< Check to determine if DRAM ECC Byte training |
| 389 | CheckDrvImpCtrl, ///< Check to determine if we need to set DrvImpCtrl |
| 390 | CheckDramTerm, ///< Check to determine if we need to set DramTerm |
| 391 | CheckDramTermDyn, ///< Check to determine if we need to set DramTermDyn |
| 392 | CheckQoff, ///< Check to determine if we need to set Qoff |
| 393 | CheckSetSameDctODTsEn, ///< Check to defermine if we need to set "ODTsEn" the same on each DCT |
| 394 | WLNegativeDelay, ///< Check to determine if the NB can tolerate a negtive WL delay value |
| 395 | SchedDlySlot1Extra, ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK |
| 396 | TwoStageDramInit, ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init. |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 397 | AdjustTrc, ///< Check to determine if we need to adjust Trc |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 398 | |
| 399 | EnumSize ///< Size of list |
| 400 | } NB_SUPPORTED; |
| 401 | |
| 402 | /// List for family specific functions that are supported |
| 403 | typedef enum { |
| 404 | BeforePhyFenceTraining, ///< Family specific tasks before Phy Fence Training |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 405 | BeforeMemClkFreqVal, ///< hook before setting MemClkFreqVal bit |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 406 | AfterMemClkFreqVal, ///< Override PllMult and PllDiv |
| 407 | OverridePllMult, ///< Override PllMult |
| 408 | OverridePllDiv, ///< Override PllDiv |
| 409 | BeforeMemClr, ///< Before MemClr |
| 410 | SendMrsCmdsPerCs, ///< Send MRS commands per CS |
| 411 | SetupHwTrainingEngine, ///< Setup Hardware training engine for specific training type |
| 412 | OverrideRcvEnSeed, ///< Override seed for hardware based RcvEn training |
| 413 | AddlMaxRdLatTrain, ///< Perform additional MaxRdLat training if needed |
| 414 | ForceAutoComp, ///< Force Auto Comp |
| 415 | DetectMemPllError, ///< Detect MemPll Divide by 3 bug |
| 416 | ReEnablePhyComp, ///< Re-Enable Phy Compensation after RcvEn Training |
| 417 | ExtractWLODT, ///< Extract WL ODT value thr given ODT pattern |
| 418 | DCTSelectSwitch, ///< Select DCT when we switch DCT |
| 419 | ScrubberErratum, ///< Erratum for setting scrubber rate |
| 420 | MR0_PPD, ///< Override MR0[PPD] |
| 421 | GetDdrMaxRate, ///< Interpret DdrMaxRate with Familiy-specific encoding |
| 422 | ExitPhyAssistedTraining, ///< Perform family specific tasks when exiting phy assisted training |
| 423 | AfterSaveRestore, ///< Action after save/restore execution |
| 424 | OverrideDataTxFifoWrDly, ///< Override DataTxFifoWrDly based on training result of WrDatDly |
| 425 | OverrideRcvEnSeedPassN, ///< Override seed for hardware based RcvEn training where N greater than 0 |
| 426 | AfterMemClkFreqChg, ///< Reprogram DIMMs' buffers after MEMCLK frequency change |
| 427 | AdjustTxpdll, ///< Adjust Txpdll value to encoded register value |
| 428 | CalcWrDqDqsEarly, ///< Calculate WrDqDqsEarly |
| 429 | TrainWlPerNibble, ///< Train Write Leveling per nibble |
| 430 | TrainWlPerNibbleAdjustWLDly, ///< Train WL per nibble and adjust the WL delay |
| 431 | TrainWlPerNibbleSeed, ///< Save the seed for WL nibble based training |
| 432 | TrainRxEnPerNibble, ///< Train Rx Enable Training per nibble |
| 433 | TrainRxEnAdjustDlyPerNibble, ///< Train Rx Enable Training nibble and adjust the RxEn delay |
| 434 | TrainRxEnGetAvgDlyPerNibble, ///< Display Rx Enable Training average nibble value for each BL |
| 435 | InitPerNibbleTrn, ///< Initiates Per Nibble Training. |
| 436 | BeforeSetCsTri, ///< Modify CS tri-state bit map. |
| 437 | ForceRdDqsPhaseB, ///< Force RdDqsDly to phase B |
| 438 | SetDqsODT, ///< Set DQS ODT |
| 439 | DisLowPwrDrvStr, ///< Hook to skip setting LowPowerDriveStrengthEn |
| 440 | AdjustRdDqsDlyOffset, ///< Adjust the bit offset of the RdDqsDly Bit Bitfield before writing and after reading |
| 441 | ResetRxFifoPtr, ///< Reset RxFifo pointer during Read DQS training |
| 442 | EnableParityAfterMemRst, ///< Enable DRAM Address Parity after memory reset. |
| 443 | FinalizeVDDIO, ///< Finalize VDDIO |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 444 | BfAfExcludeDimm, ///< Workaround before and after excluding dimms |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 445 | |
| 446 | NumberOfHooks ///< Size of list |
| 447 | } FAMILY_SPECIFIC_FUNC_INDEX; |
| 448 | |
| 449 | ///< Entry for SPD Timing |
| 450 | typedef struct { |
| 451 | BIT_FIELD_NAME BitField; ///< Bit field name of the timing |
| 452 | UINT8 Min; ///< Minimum value for timing |
| 453 | UINT8 Max; ///< Maximum value for timing |
| 454 | UINT8 Bias; ///< Bias from actual value |
| 455 | UINT8 Ratio_x2; ///< Actual value will be multiplied by (Ratio_x2/2) |
| 456 | } CTENTRY; |
| 457 | |
| 458 | /// Structure for northbridge block. |
| 459 | typedef struct _MEM_NB_BLOCK { |
| 460 | MEM_DATA_STRUCT *MemPtr; ///< Point to MEM_DATA_STRUCT. |
| 461 | MEM_PARAMETER_STRUCT *RefPtr; ///< Point to MEM_PARAMETER_STRUCT. |
| 462 | DIE_STRUCT *MCTPtr; ///< point to current Node's MCT struct |
| 463 | DCT_STRUCT *DCTPtr; ///< point to current Node's DCT struct |
| 464 | DCT_STRUCT *AllDCTPtr; ///< point to all Node's DCT structs |
| 465 | CH_DEF_STRUCT *ChannelPtr; ///< point to current channel data |
| 466 | SPD_DEF_STRUCT *SPDPtr; ///< Point to SPD data for current DCT. |
| 467 | struct _MEM_TECH_BLOCK *TechPtr; ///< point to technology block. |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 468 | CONST struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block. |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 469 | struct _MEM_SHARED_DATA *SharedPtr; ///< Pointer to Memory scratchpad area |
| 470 | SPD_DEF_STRUCT *AllNodeSPDPtr; ///< Point to SPD data for the system. |
| 471 | DIE_STRUCT *AllNodeMCTPtr; ///< point to all Node's MCT structs |
| 472 | UINT8 DimmToBeUsed; ///< Dimm to be used in recovery mode. |
| 473 | MEM_PS_BLOCK *PsPtr; ///< point to platform specific block |
| 474 | MEM_PS_BLOCK *PSBlock; ///< point to the first platform specific block on this node. |
| 475 | MEM_FREQ_CHANGE_PARAM *FreqChangeParam; ///< pointer to parameter of frequency change. |
| 476 | |
| 477 | PCI_ADDR PciAddr; ///< PCI address for this node |
| 478 | TSEFO NBRegTable[BFEndOfList]; ///< contains all bit field definitions |
| 479 | |
| 480 | UINT8 Node; ///< current node. |
| 481 | UINT8 Dct; ///< current DCT. |
| 482 | UINT8 Channel; ///< current channel. |
| 483 | UINT8 DctCount; ///< number of DCTs on the current NB. |
| 484 | UINT8 ChannelCount; ///< number of channels per DCT of the current NB. |
| 485 | UINT8 NodeCount; ///< number of Nodes supported |
| 486 | BOOLEAN Ganged; ///< mode for current MCT controller. |
| 487 | POS_TRN_PATTERN_TYPE PosTrnPattern; ///< specifies the pattern that should be used for position training. |
| 488 | BOOLEAN MemCleared; ///< memory clear flag. |
| 489 | UINT32 CPGInit; ///< continuous pattern generation flag. |
| 490 | UINT16 StartupSpeed; ///< startup speed for DDR3. |
| 491 | UINT16 RcvrEnDlyLimit; ///< maximum value that RcvrEnDly field can take. |
| 492 | UINT32 McaNbCtlReg; ///< reserve MCA reports. |
| 493 | UINT32 VarMtrrHiMsk; ///< variable MTRR mask for upper 32 bits. |
| 494 | UINT32 NBClkFreq; ///< Current NB Clock frequency |
| 495 | UINT8 DefDctSelIntLvAddr; ///< Default DctSelIntLvAddr |
| 496 | UINT8 TrainingSequenceIndex; ///< Index into the Training Sequence |
| 497 | RRW_SETTINGS RrwSettings; ///<Settings for Reliable Read/Write mode |
| 498 | |
| 499 | UINT16 MaxFreqVDDIO[VOLT1_25 + 1]; ///< Max Frequency each voltage supports. |
| 500 | |
| 501 | MEM_DCT_CACHE DctCache[MAX_CHANNELS_PER_SOCKET]; ///< Allocate space for MCT_DCT_CACHE. |
| 502 | MEM_DCT_CACHE *DctCachePtr; ///< pointer to current Node's Node struct |
| 503 | |
| 504 | /* Temporary storage */ |
| 505 | BOOLEAN ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory |
| 506 | UINT8 NbFreqChgState; ///< is used as a state index in NB frequency change state machine |
| 507 | UINT32 NbPsCtlReg; ///< is used to save/restore NB Pstate control register |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 508 | CONST UINT32 *RecModeDefRegArray; ///< points to an array of default register values that are set for recovery mode |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 509 | |
| 510 | ///< Determines if code should be executed on a give NB |
| 511 | BOOLEAN IsSupported[EnumSize]; |
| 512 | BOOLEAN (*FamilySpecificHook[NumberOfHooks]) (struct _MEM_NB_BLOCK *NBPtr, VOID *OptParam); ///< This array of pointers point to |
| 513 | ///< family specific functions. |
| 514 | |
| 515 | /* PUBLIC functions */ |
| 516 | VOID (*SwitchDCT) (struct _MEM_NB_BLOCK *NBPtr, UINT8 DCT); ///< Switch to current DCT. |
| 517 | VOID (*SwitchChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Channel); ///< Switch to current channel. |
| 518 | VOID (*SetMaxLatency) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxRcvEnDly); ///< Set Max Rd Latency. |
| 519 | VOID (*getMaxLatParams) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxDlyForMaxRdLat, UINT16 *MinDly, UINT16 *MaxDly, UINT16 *DlyBias); ///< retrieves the Max latency parameters. |
| 520 | BOOLEAN (*GetSysAddr) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver, UINT32 *Addr); ///< Get system address for training dimm. |
| 521 | BOOLEAN (*RankEnabled) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver); ///< Check if a rank has been enabled. |
| 522 | BOOLEAN (*InitializeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< MCT initialization. |
| 523 | BOOLEAN (*FinalizeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< sets final values in BUCFG and BUCFG2. |
| 524 | BOOLEAN (*InitMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< main entry call for memory initialization. |
| 525 | VOID (*SendMrsCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send MRS command. |
| 526 | VOID (*sendZQCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send ZQ command. |
| 527 | VOID (*TrainingFlow) (struct _MEM_NB_BLOCK *NBPtr); ///< Set the training flow control |
| 528 | VOID (*WritePattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT8 Pattern[], UINT16 ClCount); ///< Write training pattern. |
| 529 | VOID (*ReadPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT32 Address, UINT16 ClCount); ///< Read training pattern. |
| 530 | VOID (*GenHwRcvEnReads) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address); ///< generates a continuous burst of reads during HW RcvEn training. |
| 531 | UINT16 (*CompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern. |
| 532 | UINT16 (*InsDlyCompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern using 1 beat offset to check for insertion delay |
| 533 | BOOLEAN (*StitchMemory) (struct _MEM_NB_BLOCK *NBPtr); ///< combines all the memory into a contiguous map. |
| 534 | VOID (*ProgramCycTimings) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with SPD timings. |
| 535 | BOOLEAN (*AutoConfig) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with configuration parameters |
| 536 | BOOLEAN (*PlatformSpec) (struct _MEM_NB_BLOCK *NBPtr); ///< programs platform specific parameters. |
| 537 | VOID (*DisableDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< disable a DCT if no dimm presents. |
| 538 | VOID (*StartupDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< start a DCT. |
| 539 | VOID (*SyncTargetSpeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Check and sync the target speed of all channels of this node. |
| 540 | VOID (*ChangeFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Frequency change sequence. |
| 541 | BOOLEAN (*RampUpFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change frequency to the next supported level. |
| 542 | BOOLEAN (*ChangeNbFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change NB frequency. |
| 543 | VOID (*PhyFenceTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy fence training. |
| 544 | BOOLEAN (*SyncDctsReady) (struct _MEM_NB_BLOCK *NBPtr); ///< Synchronize DCTs. |
| 545 | BOOLEAN (*HtMemMapInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Memory map initialization. |
| 546 | VOID (*SyncAddrMapToAllNodes) (struct _MEM_NB_BLOCK *NBPtr); ///< copies the Node 0 map to all the other nodes. |
| 547 | BOOLEAN (*CpuMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting. |
| 548 | VOID (*BeforeDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed before DQS training. |
| 549 | VOID (*AfterDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed after DQS training. |
| 550 | BOOLEAN (*OtherTiming) (struct _MEM_NB_BLOCK *NBPtr); ///< setting non-spd timing. |
| 551 | VOID (*UMAMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting needed for UMA platform. |
| 552 | VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support. |
| 553 | UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket. |
| 554 | VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT. |
Frank Vibrans | ccad951 | 2011-05-05 16:49:11 +0000 | [diff] [blame] | 555 | UINT32 (*GetSysAddrRec) (VOID); ///< Get system address for training. |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 556 | VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node. |
| 557 | VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB. |
| 558 | VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size. |
| 559 | VOID (*GetTrainDlyParms) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, TRN_DLY_PARMS *Parms); ///< Retrieve Specific Delay range info for current NB under current conditions. |
| 560 | AGESA_STATUS (*TrainingPatternInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize the training Pattern |
| 561 | AGESA_STATUS (*TrainingPatternFinalize) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize the training Pattern |
| 562 | BOOLEAN (*GetApproximateWriteDatDelay) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Index, UINT8 *Value); ///< Retrieve the next WrDat Delay Approximation |
| 563 | UINT8 (*CSPerChannel) (struct _MEM_NB_BLOCK *NBPtr); ///< Return number of CS per channel. |
| 564 | UINT8 (*CSPerDelay) (struct _MEM_NB_BLOCK *NBPtr); ///< Return number of CS controlled per set of delay registers. |
| 565 | VOID (*FlushPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT16 ClCount); ///<Flush the training pattern |
| 566 | UINT8 (*MinDataEyeWidth) (struct _MEM_NB_BLOCK *NBPtr); ///<Get Min Data Eye Width in 32nds of a UI |
| 567 | VOID (*MemNCapSpeedBatteryLife) (struct _MEM_NB_BLOCK *NBPtr); ///< Caps speed based on battery life check. |
| 568 | UINT32 (*GetUmaSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Get Uma Size |
| 569 | UINT8 (*GetMemClkFreqId) (struct _MEM_NB_BLOCK *NBPtr, UINT16 Speed); ///< Translate MemClk frequency in MHz to MemClkFreq value |
| 570 | VOID (*EnableSwapIntlvRgn) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Base, UINT32 Limit); ///< Enable swapped interleaving region |
| 571 | BOOLEAN (*ChangeNbFrequencyWrap) (struct _MEM_NB_BLOCK *NBPr, UINT32 NBPstate); ///< Wrapper for NB Pstate change function |
| 572 | VOID (*WaitXMemClks) (struct _MEM_NB_BLOCK *NBPr, UINT32 MemClkCount); ///< Waits a specified number of MemClks |
| 573 | VOID (*ProgramNbPsDependentRegs) (struct _MEM_NB_BLOCK *NBPtr); ///< Programs NB Pstate dependent registers |
| 574 | VOID (*AllocateC6Storage) (struct _MEM_NB_BLOCK *NBPtr); ///< Allocates DRAM region for Core C6 |
| 575 | |
| 576 | /* PUBLIC Get/Set register field functions */ |
| 577 | UINT32 (*GetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName); ///< Pci register bit field read. |
| 578 | VOID (*SetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field write. |
| 579 | BOOLEAN (*BrdcstCheck) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast read. |
| 580 | VOID (*BrdcstSet) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast write. |
| 581 | VOID (*PollBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Field, UINT32 MicroSecond, BOOLEAN IfBroadCast); ///< Poll a Pci register bitfield. |
| 582 | UINT32 (*GetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar); ///< Training register bit field read. |
| 583 | VOID (*SetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Value); ///< Training register bit field write. |
| 584 | AGESA_STATUS (*InitRecovery) (struct _MEM_NB_BLOCK *NBPtr); ///< Recover mode memory init |
| 585 | VOID (*MemRecNInitializeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize MCT changes |
| 586 | VOID (*MemRecNFinalizeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize MCT changes |
| 587 | VOID (*MemNInitPhyComp) (struct _MEM_NB_BLOCK *NBPtr); ///< Init Phy compensation |
| 588 | VOID (*MemNBeforeDramInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Before Dram init |
| 589 | BOOLEAN (*MemNIsIdSupportedNb) (struct _MEM_NB_BLOCK *NBPtr, CPU_LOGICAL_ID *LogicalIdPtr); ///< Determines if a given CPU id is supported |
| 590 | BOOLEAN (*InitNBRegTableNb) (struct _MEM_NB_BLOCK *NBPtr, TSEFO NBRegTable[]); ///< Initializes register table |
| 591 | BOOLEAN (*MemNPlatformSpecificFormFactorInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Platform specific functions |
| 592 | VOID (*MemNSetOtherTimingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Set non-spd timings |
| 593 | VOID (*MemNBeforePlatformSpecNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Apply settings prior to platform specific settings |
| 594 | UINT32 (*MemNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< Sets a register value |
| 595 | UINT32 (*MemNcmnGetSetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< Sets a training delay field |
| 596 | VOID (*MemPPhyFenceTrainingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy Fence training |
| 597 | VOID (*MemPNodeMemBoundaryNb) (struct _MEM_NB_BLOCK *NBPtr, UINT32 *NodeSysLimit); ///< Phy Fence training |
| 598 | UINT32 (*MemRecNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< This functions sets bit fields in recover mode |
| 599 | UINT32 (*MemRecNcmnGetSetTrainDlyNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< This functions sets bit fields in recover mode |
| 600 | VOID (*MemRecNSwitchDctNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< S3 Exit self refresh register |
| 601 | VOID (*MemNPFenceAdjustNb) (struct _MEM_NB_BLOCK *NBPtr, UINT16 *Value16); ///< Adjust Avg PRE value of Phy fence training |
| 602 | VOID (*MemNPrepareRcvrEnDlySeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Seed valude for HW RxEn training |
| 603 | UINT8 (*MemNGetDramTerm) (struct _MEM_NB_BLOCK *NBPtr, UINT8 ChipSel); ///< Dram Term value |
| 604 | UINT8 (*MemNGetDynDramTerm) (struct _MEM_NB_BLOCK *NBPtr, UINT8 ChipSel); ///< Dynamic Dram Term value |
| 605 | UINT32 (*MemNGetMR0CL) (struct _MEM_NB_BLOCK *NBPtr); ///< MR0[CL] value |
| 606 | UINT32 (*MemNGetMR0WR) (struct _MEM_NB_BLOCK *NBPtr); ///< MR0[WR] value |
| 607 | UINT32 (*MemNGetMR2CWL) (struct _MEM_NB_BLOCK *NBPtr); ///< MR2[CWL] value |
| 608 | |
| 609 | } MEM_NB_BLOCK; |
| 610 | |
| 611 | /*---------------------------------------------------------------------------- |
| 612 | * FUNCTIONS PROTOTYPE |
| 613 | * |
| 614 | *---------------------------------------------------------------------------- |
| 615 | */ |
| 616 | VOID |
| 617 | MemNInitNBDataNb ( |
| 618 | IN OUT MEM_NB_BLOCK *NBPtr |
| 619 | ); |
| 620 | |
| 621 | VOID |
| 622 | MemNSwitchDCTNb ( |
| 623 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 624 | IN UINT8 Dct |
| 625 | ); |
| 626 | |
| 627 | VOID |
| 628 | MemNSwitchChannelNb ( |
| 629 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 630 | IN UINT8 Channel |
| 631 | ); |
| 632 | |
| 633 | UINT32 |
| 634 | MemNGetBitFieldNb ( |
| 635 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 636 | IN BIT_FIELD_NAME FieldName |
| 637 | ); |
| 638 | |
| 639 | VOID |
| 640 | MemNSetBitFieldNb ( |
| 641 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 642 | IN BIT_FIELD_NAME FieldName, |
| 643 | IN UINT32 Field |
| 644 | ); |
| 645 | |
| 646 | BOOLEAN |
| 647 | MemNBrdcstCheckNb ( |
| 648 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 649 | IN BIT_FIELD_NAME FieldName, |
| 650 | IN UINT32 Field |
| 651 | ); |
| 652 | |
| 653 | VOID |
| 654 | MemNBrdcstSetNb ( |
| 655 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 656 | IN BIT_FIELD_NAME FieldName, |
| 657 | IN UINT32 Field |
| 658 | ); |
| 659 | |
| 660 | |
| 661 | UINT32 |
| 662 | MemNGetTrainDlyNb ( |
| 663 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 664 | IN TRN_DLY_TYPE TrnDly, |
| 665 | IN DRBN DrbnVar |
| 666 | ); |
| 667 | |
| 668 | VOID |
| 669 | MemNSetTrainDlyNb ( |
| 670 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 671 | IN TRN_DLY_TYPE TrnDly, |
| 672 | IN DRBN DrbnVar, |
| 673 | IN UINT16 Field |
| 674 | ); |
| 675 | |
| 676 | BOOLEAN |
| 677 | MemNRankEnabledNb ( |
| 678 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 679 | IN UINT8 Receiver |
| 680 | ); |
| 681 | |
| 682 | UINT8 MemNGetSocketRelativeChannelNb ( |
| 683 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 684 | IN UINT8 Dct, |
| 685 | IN UINT8 Channel |
| 686 | ); |
| 687 | |
| 688 | VOID |
| 689 | MemNPhyFenceTrainingNb ( |
| 690 | IN OUT MEM_NB_BLOCK *NBPtr |
| 691 | ); |
| 692 | |
| 693 | BOOLEAN |
| 694 | MemNGetMCTSysAddrNb ( |
| 695 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 696 | IN UINT8 Receiver, |
| 697 | OUT UINT32 *AddrPtr |
| 698 | ); |
| 699 | |
| 700 | BOOLEAN |
| 701 | MemNPlatformSpecNb ( |
| 702 | IN OUT MEM_NB_BLOCK *NBPtr |
| 703 | ); |
| 704 | |
| 705 | BOOLEAN |
| 706 | MemNStitchMemoryNb ( |
| 707 | IN OUT MEM_NB_BLOCK *NBPtr |
| 708 | ); |
| 709 | |
| 710 | VOID |
| 711 | MemNDisableDCTNb ( |
| 712 | IN OUT MEM_NB_BLOCK *NBPtr |
| 713 | ); |
| 714 | |
| 715 | VOID |
| 716 | MemNDisableDCTClientNb ( |
| 717 | IN OUT MEM_NB_BLOCK *NBPtr |
| 718 | ); |
| 719 | |
| 720 | VOID |
| 721 | MemNStartupDCTNb ( |
| 722 | IN OUT MEM_NB_BLOCK *NBPtr |
| 723 | ); |
| 724 | |
| 725 | VOID |
| 726 | MemNStartupDCTUnb ( |
| 727 | IN OUT MEM_NB_BLOCK *NBPtr |
| 728 | ); |
| 729 | |
| 730 | VOID |
| 731 | MemNChangeFrequencyNb ( |
| 732 | IN OUT MEM_NB_BLOCK *NBPtr |
| 733 | ); |
| 734 | |
| 735 | BOOLEAN |
| 736 | MemNRampUpFrequencyNb ( |
| 737 | IN OUT MEM_NB_BLOCK *NBPtr |
| 738 | ); |
| 739 | |
| 740 | VOID |
| 741 | MemNProgramCycTimingsNb ( |
| 742 | IN OUT MEM_NB_BLOCK *NBPtr |
| 743 | ); |
| 744 | |
| 745 | VOID |
| 746 | MemNGetMaxLatParamsNb ( |
| 747 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 748 | IN UINT16 MaxRcvEnDly, |
| 749 | IN OUT UINT16 *MinDlyPtr, |
| 750 | IN OUT UINT16 *MaxDlyPtr, |
| 751 | IN OUT UINT16 *DlyBiasPtr |
| 752 | ); |
| 753 | |
| 754 | UINT16 |
| 755 | MemNTotalSyncComponentsNb ( |
| 756 | IN OUT MEM_NB_BLOCK *NBPtr |
| 757 | ); |
| 758 | |
| 759 | VOID |
| 760 | MemNSetMaxLatencyNb ( |
| 761 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 762 | IN UINT16 MaxRcvEnDly |
| 763 | ); |
| 764 | |
| 765 | VOID |
| 766 | MemNSendZQCmdNb ( |
| 767 | IN OUT MEM_NB_BLOCK *NBPtr |
| 768 | ); |
| 769 | |
| 770 | VOID |
| 771 | MemNSwapBitsNb ( |
| 772 | IN OUT MEM_NB_BLOCK *NBPtr |
| 773 | ); |
| 774 | |
| 775 | VOID |
| 776 | MemNSwapBitsUnb ( |
| 777 | IN OUT MEM_NB_BLOCK *NBPtr |
| 778 | ); |
| 779 | |
| 780 | VOID |
| 781 | MemNTrainPhyFenceNb ( |
| 782 | IN OUT MEM_NB_BLOCK *NBPtr |
| 783 | ); |
| 784 | |
| 785 | VOID |
| 786 | MemNInitPhyCompNb ( |
| 787 | IN OUT MEM_NB_BLOCK *NBPtr |
| 788 | ); |
| 789 | |
| 790 | VOID |
| 791 | MemNGetTrainDlyParmsNb ( |
| 792 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 793 | IN TRN_DLY_TYPE TrnDly, |
| 794 | IN OUT TRN_DLY_PARMS *Parms |
| 795 | ); |
| 796 | |
| 797 | |
| 798 | VOID |
| 799 | MemNGetTrainDlyParmsClientNb ( |
| 800 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 801 | IN TRN_DLY_TYPE TrnDly, |
| 802 | IN OUT TRN_DLY_PARMS *Parms |
| 803 | ); |
| 804 | |
| 805 | VOID |
| 806 | MemNBeforeDQSTrainingNb ( |
| 807 | IN OUT MEM_NB_BLOCK *NBPtr |
| 808 | ); |
| 809 | |
| 810 | UINT32 |
| 811 | MemNcmnGetSetTrainDlyNb ( |
| 812 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 813 | IN UINT8 IsSet, |
| 814 | IN TRN_DLY_TYPE TrnDly, |
| 815 | IN DRBN DrbnVar, |
| 816 | IN UINT16 Field |
| 817 | ); |
| 818 | |
| 819 | UINT32 |
| 820 | MemNcmnGetSetTrainDlyClientNb ( |
| 821 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 822 | IN UINT8 IsSet, |
| 823 | IN TRN_DLY_TYPE TrnDly, |
| 824 | IN DRBN DrbnVar, |
| 825 | IN UINT16 Field |
| 826 | ); |
| 827 | |
| 828 | VOID |
| 829 | MemNSyncTargetSpeedNb ( |
| 830 | IN OUT MEM_NB_BLOCK *NBPtr |
| 831 | ); |
| 832 | |
| 833 | BOOLEAN |
| 834 | MemNSyncDctsReadyNb ( |
| 835 | IN OUT MEM_NB_BLOCK *NBPtr |
| 836 | ); |
| 837 | |
| 838 | BOOLEAN |
| 839 | MemNHtMemMapInitNb ( |
| 840 | IN OUT MEM_NB_BLOCK *NBPtr |
| 841 | ); |
| 842 | |
| 843 | UINT8 |
| 844 | MemNGetTrdrdNb ( |
| 845 | IN OUT MEM_NB_BLOCK *NBPtr |
| 846 | ); |
| 847 | |
| 848 | UINT8 |
| 849 | MemNGetTwrwrNb ( |
| 850 | IN OUT MEM_NB_BLOCK *NBPtr |
| 851 | ); |
| 852 | |
| 853 | UINT8 |
| 854 | MemNGetTwrrdNb ( |
| 855 | IN OUT MEM_NB_BLOCK *NBPtr |
| 856 | ); |
| 857 | |
| 858 | UINT8 |
| 859 | MemNGetTrwtTONb ( |
| 860 | IN OUT MEM_NB_BLOCK *NBPtr |
| 861 | ); |
| 862 | |
| 863 | UINT8 |
| 864 | MemNGetTrwtWBNb ( |
| 865 | IN OUT MEM_NB_BLOCK *NBPtr |
| 866 | ); |
| 867 | |
| 868 | VOID |
| 869 | MemNPowerDownCtlNb ( |
| 870 | IN OUT MEM_NB_BLOCK *NBPtr |
| 871 | ); |
| 872 | |
| 873 | BOOLEAN |
| 874 | MemNCPUMemTypingNb ( |
| 875 | IN OUT MEM_NB_BLOCK *NBPtr |
| 876 | ); |
| 877 | |
| 878 | VOID |
| 879 | MemNUMAMemTypingNb ( |
| 880 | IN OUT MEM_NB_BLOCK *NBPtr |
| 881 | ); |
| 882 | |
| 883 | VOID |
| 884 | MemNSyncAddrMapToAllNodesNb ( |
| 885 | IN OUT MEM_NB_BLOCK *NBPtr |
| 886 | ); |
| 887 | |
| 888 | BOOLEAN |
| 889 | MemNInitMCTNb ( |
| 890 | IN OUT MEM_NB_BLOCK *NBPtr |
| 891 | ); |
| 892 | |
| 893 | VOID |
| 894 | MemNTechBlockSwitchNb ( |
| 895 | IN OUT MEM_NB_BLOCK *NBPtr |
| 896 | ); |
| 897 | |
| 898 | UINT32 |
| 899 | MemRecNGetBitFieldNb ( |
| 900 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 901 | IN BIT_FIELD_NAME FieldName |
| 902 | ); |
| 903 | |
| 904 | VOID |
| 905 | MemRecNSetBitFieldNb ( |
| 906 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 907 | IN BIT_FIELD_NAME FieldName, |
| 908 | IN UINT32 Field |
| 909 | ); |
| 910 | |
| 911 | UINT32 |
| 912 | MemRecNGetTrainDlyNb ( |
| 913 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 914 | IN TRN_DLY_TYPE TrnDly, |
| 915 | IN DRBN DrbnVar |
| 916 | ); |
| 917 | |
| 918 | VOID |
| 919 | MemRecNSetTrainDlyNb ( |
| 920 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 921 | IN TRN_DLY_TYPE TrnDly, |
| 922 | IN DRBN DrbnVar, |
| 923 | IN UINT16 Field |
| 924 | ); |
| 925 | |
| 926 | BOOLEAN |
| 927 | MemRecNAutoConfigNb ( |
| 928 | IN OUT MEM_NB_BLOCK *NBPtr |
| 929 | ); |
| 930 | |
| 931 | BOOLEAN |
| 932 | MemRecNPlatformSpecNb ( |
| 933 | IN OUT MEM_NB_BLOCK *NBPtr |
| 934 | ); |
| 935 | |
| 936 | VOID |
| 937 | MemRecNStartupDCTNb ( |
| 938 | IN OUT MEM_NB_BLOCK *NBPtr |
| 939 | ); |
| 940 | |
| 941 | VOID |
| 942 | MemRecNSetMaxLatencyNb ( |
| 943 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 944 | IN UINT16 MaxRcvEnDly |
| 945 | ); |
| 946 | |
| 947 | VOID |
| 948 | MemRecNSetDramOdtNb ( |
| 949 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 950 | IN ODT_MODE OdtMode, |
| 951 | IN UINT8 ChipSelect, |
| 952 | IN UINT8 TargetCS |
| 953 | ); |
| 954 | |
| 955 | VOID |
| 956 | MemRecNSendMrsCmdNb ( |
| 957 | IN OUT MEM_NB_BLOCK *NBPtr |
| 958 | ); |
| 959 | |
| 960 | |
| 961 | VOID |
| 962 | MemRecNSendZQCmdNb ( |
| 963 | IN OUT MEM_NB_BLOCK *NBPtr |
| 964 | ); |
| 965 | |
| 966 | VOID |
| 967 | MemRecNContReadPatternClientNb ( |
| 968 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 969 | IN UINT8 Buffer[], |
| 970 | IN UINT32 Address, |
| 971 | IN UINT16 ClCount |
| 972 | ); |
| 973 | |
| 974 | AGESA_STATUS |
| 975 | MemRecNMemInitNb ( |
| 976 | IN OUT MEM_NB_BLOCK *NBPtr |
| 977 | ); |
| 978 | |
| 979 | VOID |
| 980 | MemRecNCPUMemRecTypingNb ( |
| 981 | IN OUT MEM_NB_BLOCK *NBPtr |
| 982 | ); |
| 983 | |
| 984 | UINT32 |
| 985 | MemRecNGetMCTSysAddrNb ( |
Frank Vibrans | ccad951 | 2011-05-05 16:49:11 +0000 | [diff] [blame] | 986 | VOID |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 987 | ); |
| 988 | |
| 989 | UINT32 |
| 990 | MemRecGetVarMtrrHiMsk ( |
| 991 | IN CPU_LOGICAL_ID *LogicalIdPtr, |
| 992 | IN AMD_CONFIG_PARAMS *StdHeader |
| 993 | ); |
| 994 | |
| 995 | INT8 |
| 996 | MemNGetOptimalCGDDNb ( |
| 997 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 998 | IN TRN_DLY_TYPE TrnDly1, |
| 999 | IN TRN_DLY_TYPE TrnDly2 |
| 1000 | ); |
| 1001 | |
| 1002 | VOID |
| 1003 | MemNPollBitFieldNb ( |
| 1004 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1005 | IN BIT_FIELD_NAME FieldName, |
| 1006 | IN UINT32 Field, |
| 1007 | IN UINT32 MicroSecond, |
| 1008 | IN BOOLEAN IfBroadCast |
| 1009 | ); |
| 1010 | |
| 1011 | VOID |
| 1012 | MemNSetEccSymbolSizeNb ( |
| 1013 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1014 | ); |
| 1015 | |
| 1016 | BOOLEAN |
| 1017 | MemNDQSTiming3Nb ( |
| 1018 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1019 | ); |
| 1020 | |
| 1021 | BOOLEAN |
| 1022 | MemNDQSTiming2Nb ( |
| 1023 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1024 | ); |
| 1025 | |
| 1026 | BOOLEAN |
| 1027 | MemNTrainingFlowNb ( |
| 1028 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1029 | ); |
| 1030 | |
| 1031 | VOID |
| 1032 | MemNRecTrainingFlowNb ( |
| 1033 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1034 | ); |
| 1035 | |
| 1036 | VOID |
| 1037 | MemNRecTrainingFlowClientNb ( |
| 1038 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1039 | ); |
| 1040 | |
| 1041 | UINT32 |
| 1042 | MemRecNTotalSyncComponentsClientNb ( |
| 1043 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1044 | ); |
| 1045 | |
| 1046 | VOID |
| 1047 | MemRecNStartupDCTClientNb ( |
| 1048 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1049 | ); |
| 1050 | |
| 1051 | |
| 1052 | VOID |
| 1053 | MemRecNPhyVoltageLevelNb ( |
| 1054 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1055 | ); |
| 1056 | |
| 1057 | VOID |
| 1058 | MemRecNPhyFenceTrainingNb ( |
| 1059 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1060 | ); |
| 1061 | |
| 1062 | AGESA_STATUS |
| 1063 | MemNTrainingPatternInitNb ( |
| 1064 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1065 | ); |
| 1066 | |
| 1067 | BOOLEAN |
| 1068 | MemNGetApproximateWriteDatDelayNb ( |
| 1069 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1070 | IN UINT8 Index, |
| 1071 | IN OUT UINT8 *Value |
| 1072 | ); |
| 1073 | |
| 1074 | AGESA_STATUS |
| 1075 | MemNTrainingPatternFinalizeNb ( |
| 1076 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1077 | ); |
| 1078 | |
| 1079 | VOID |
| 1080 | MemNFlushPatternNb ( |
| 1081 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1082 | IN UINT32 Address, |
| 1083 | IN UINT16 ClCount |
| 1084 | ); |
| 1085 | |
| 1086 | UINT8 |
| 1087 | MemNCSPerChannelNb ( |
| 1088 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1089 | ); |
| 1090 | |
| 1091 | UINT8 |
| 1092 | MemNCSPerDelayNb ( |
| 1093 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1094 | ); |
| 1095 | |
| 1096 | UINT8 |
| 1097 | MemNMinDataEyeWidthNb ( |
| 1098 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1099 | ); |
| 1100 | |
| 1101 | UINT16 |
| 1102 | MemNCompareTestPatternNb ( |
| 1103 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1104 | IN UINT8 Buffer[], |
| 1105 | IN UINT8 Pattern[], |
| 1106 | IN UINT16 ByteCount |
| 1107 | ); |
| 1108 | |
| 1109 | UINT16 |
| 1110 | MemNInsDlyCompareTestPatternNb ( |
| 1111 | IN MEM_NB_BLOCK *NBPtr, |
| 1112 | IN UINT8 Buffer[], |
| 1113 | IN UINT8 Pattern[], |
| 1114 | IN UINT16 ByteCount |
| 1115 | ); |
| 1116 | |
| 1117 | |
| 1118 | UINT32 |
| 1119 | MemNGetUmaSizeNb ( |
| 1120 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1121 | ); |
| 1122 | |
| 1123 | BOOLEAN |
| 1124 | MemNSetMTRRUmaRegionUCNb ( |
| 1125 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1126 | IN UINT32 *BasePtr, |
| 1127 | IN OUT UINT32 *LimitPtr |
| 1128 | ); |
| 1129 | |
| 1130 | UINT8 |
| 1131 | MemNGetMemClkFreqIdNb ( |
| 1132 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1133 | IN UINT16 Speed |
| 1134 | ); |
| 1135 | |
| 1136 | UINT8 |
| 1137 | MemNGetMemClkFreqIdClientNb ( |
| 1138 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1139 | IN UINT16 Speed |
| 1140 | ); |
| 1141 | |
| 1142 | UINT8 |
| 1143 | MemNGetMemClkFreqIdUnb ( |
| 1144 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1145 | IN UINT16 Speed |
| 1146 | ); |
| 1147 | |
| 1148 | UINT16 |
| 1149 | MemNGetMemClkFreqUnb ( |
| 1150 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1151 | IN UINT8 FreqId |
| 1152 | ); |
| 1153 | |
| 1154 | BOOLEAN |
| 1155 | MemNGetPlatformCfgNb ( |
| 1156 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1157 | ); |
| 1158 | |
| 1159 | BOOLEAN |
| 1160 | MemNPlatformSpecUnb ( |
| 1161 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1162 | ); |
| 1163 | |
| 1164 | VOID |
| 1165 | MemNProgramPlatformSpecNb ( |
| 1166 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1167 | ); |
| 1168 | |
| 1169 | VOID |
| 1170 | MemNProgramCycTimingsClientNb ( |
| 1171 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1172 | ); |
| 1173 | |
| 1174 | INT16 |
| 1175 | MemNCalcCDDNb ( |
| 1176 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1177 | IN TRN_DLY_TYPE TrnDlyType1, |
| 1178 | IN TRN_DLY_TYPE TrnDlyType2, |
| 1179 | IN BOOLEAN SameDimm, |
| 1180 | IN BOOLEAN DiffDimm |
| 1181 | ); |
| 1182 | |
| 1183 | VOID |
| 1184 | MemNChangeFrequencyUnb ( |
| 1185 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1186 | ); |
| 1187 | |
| 1188 | VOID |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1189 | MemNProgramNbPstateDependentRegistersClientNb ( |
| 1190 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1191 | ); |
| 1192 | |
| 1193 | VOID |
| 1194 | MemNAllocateC6StorageClientNb ( |
| 1195 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1196 | ); |
| 1197 | |
| 1198 | VOID |
| 1199 | MemNAllocateC6StorageUnb ( |
| 1200 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1201 | ); |
| 1202 | |
| 1203 | VOID |
| 1204 | MemNPhyVoltageLevelNb ( |
| 1205 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1206 | ); |
| 1207 | |
| 1208 | VOID |
| 1209 | MemNPhyFenceTrainingUnb ( |
| 1210 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1211 | ); |
| 1212 | |
| 1213 | VOID |
| 1214 | MemNPFenceAdjustUnb ( |
| 1215 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1216 | IN OUT UINT16 *Value16 |
| 1217 | ); |
| 1218 | |
| 1219 | VOID |
| 1220 | MemNInitPhyCompClientNb ( |
| 1221 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1222 | ); |
| 1223 | |
| 1224 | UINT32 |
| 1225 | MemNTotalSyncComponentsClientNb ( |
| 1226 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1227 | ); |
| 1228 | |
| 1229 | VOID |
| 1230 | MemNEnableSwapIntlvRgnNb ( |
| 1231 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1232 | IN UINT32 Base, |
| 1233 | IN UINT32 Limit |
| 1234 | ); |
| 1235 | |
| 1236 | VOID |
| 1237 | MemNPhyPowerSavingClientNb ( |
| 1238 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1239 | ); |
| 1240 | |
| 1241 | VOID |
| 1242 | MemNSetASRSRTNb ( |
| 1243 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1244 | ); |
| 1245 | |
| 1246 | VOID |
| 1247 | MemNPrepareRcvrEnDlySeedNb ( |
| 1248 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1249 | ); |
| 1250 | |
| 1251 | BOOLEAN |
| 1252 | MemNChangeNbFrequencyUnb ( |
| 1253 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1254 | ); |
| 1255 | |
| 1256 | BOOLEAN |
| 1257 | MemNChangeNbFrequencyNb ( |
| 1258 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1259 | ); |
| 1260 | |
| 1261 | VOID |
| 1262 | MemNWaitXMemClksNb ( |
| 1263 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1264 | IN UINT32 MemClkCount |
| 1265 | ); |
| 1266 | |
| 1267 | BOOLEAN |
| 1268 | memNSequenceDDR3Nb ( |
| 1269 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1270 | ); |
| 1271 | |
| 1272 | UINT16 |
| 1273 | GetTrainDlyFromHeapNb ( |
| 1274 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1275 | IN TRN_DLY_TYPE TrnDlyType, |
| 1276 | IN DRBN Drbn |
| 1277 | ); |
| 1278 | |
| 1279 | BOOLEAN |
| 1280 | MemNTrainingFlowUnb ( |
| 1281 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1282 | ); |
| 1283 | |
| 1284 | BOOLEAN |
| 1285 | MemNSetupHwTrainingEngineUnb ( |
| 1286 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1287 | IN VOID* OptParam |
| 1288 | ); |
| 1289 | |
| 1290 | BOOLEAN |
| 1291 | MemNBeforePhyFenceTrainingClientNb ( |
| 1292 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1293 | IN OUT VOID *OptParam |
| 1294 | ); |
| 1295 | |
| 1296 | BOOLEAN |
| 1297 | MemNReEnablePhyCompNb ( |
| 1298 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1299 | IN OUT VOID *OptParam |
| 1300 | ); |
| 1301 | |
| 1302 | UINT8 |
| 1303 | MemNGetDramTermNb ( |
| 1304 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1305 | IN UINT8 ChipSel |
| 1306 | ); |
| 1307 | |
| 1308 | UINT8 |
| 1309 | MemNGetDynDramTermNb ( |
| 1310 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1311 | IN UINT8 ChipSel |
| 1312 | ); |
| 1313 | |
| 1314 | UINT32 |
| 1315 | MemNGetMR0CLNb ( |
| 1316 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1317 | ); |
| 1318 | |
| 1319 | UINT32 |
| 1320 | MemNGetMR0WRNb ( |
| 1321 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1322 | ); |
| 1323 | |
| 1324 | UINT32 |
| 1325 | MemNGetMR2CWLNb ( |
| 1326 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1327 | ); |
| 1328 | |
| 1329 | BOOLEAN |
| 1330 | MemNDctCfgSelectUnb ( |
| 1331 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1332 | IN VOID *Dct |
| 1333 | ); |
| 1334 | |
| 1335 | BOOLEAN |
| 1336 | MemNGetMaxDdrRateUnb ( |
| 1337 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1338 | IN VOID *DdrMaxRate |
| 1339 | ); |
| 1340 | |
| 1341 | BOOLEAN |
| 1342 | MemRecNReEnablePhyCompNb ( |
| 1343 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1344 | IN OUT VOID *OptParam |
| 1345 | ); |
| 1346 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1347 | UINT32 |
| 1348 | MemRecNcmnGetSetTrainDlyClientNb ( |
| 1349 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1350 | IN UINT8 IsSet, |
| 1351 | IN TRN_DLY_TYPE TrnDly, |
| 1352 | IN DRBN DrbnVar, |
| 1353 | IN UINT16 Field |
| 1354 | ); |
| 1355 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1356 | VOID |
| 1357 | MemNSetTxpNb ( |
| 1358 | IN OUT MEM_NB_BLOCK *NBPtr |
| 1359 | ); |
| 1360 | |
| 1361 | BOOLEAN |
| 1362 | MemNAdjustTxpdllClientNb ( |
| 1363 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1364 | IN OUT VOID *OptParam |
| 1365 | ); |
| 1366 | |
| 1367 | BOOLEAN |
| 1368 | MemNCalcWrDqDqsEarlyUnb ( |
| 1369 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1370 | IN OUT VOID *OptParam |
| 1371 | ); |
| 1372 | |
| 1373 | VOID |
| 1374 | MemNGetTrainDlyParmsUnb ( |
| 1375 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1376 | IN TRN_DLY_TYPE TrnDly, |
| 1377 | IN OUT TRN_DLY_PARMS *Parms |
| 1378 | ); |
| 1379 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 1380 | BOOLEAN |
| 1381 | MemNBfAfExcludeDimmClientNb ( |
| 1382 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1383 | IN OUT VOID *IsBefore |
| 1384 | ); |
| 1385 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1386 | #endif /* _MN_H_ */ |