Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mfS3.h |
| 6 | * |
| 7 | * S3 resume memory related functions. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Feat/S3) |
| 12 | * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $ |
| 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _MFS3_H_ |
| 48 | #define _MFS3_H_ |
| 49 | |
| 50 | /*---------------------------------------------------------------------------- |
| 51 | * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) |
| 52 | * |
| 53 | *---------------------------------------------------------------------------- |
| 54 | */ |
| 55 | |
| 56 | /*----------------------------------------------------------------------------- |
| 57 | * DEFINITIONS AND MACROS |
| 58 | * |
| 59 | *----------------------------------------------------------------------------- |
| 60 | */ |
| 61 | #define PRESELFREF 0 |
| 62 | #define POSTSELFREF 1 |
| 63 | #define DCT0 0 |
| 64 | #define DCT1 1 |
| 65 | #define DCT0_MASK 0x1 |
| 66 | #define DCT1_MASK 0x2 |
| 67 | #define DCT0_NBPSTATE_SUPPORT_MASK 0x4 |
| 68 | #define DCT1_NBPSTATE_SUPPORT_MASK 0x8 |
| 69 | #define DCT0_DDR3_MASK 0x10 |
| 70 | #define DCT1_DDR3_MASK 0x20 |
| 71 | #define NODE_WITHOUT_DIMM_MASK 0x80 |
| 72 | #define DCT0_ANY_DIMM_MASK 0x55 |
| 73 | #define DCT1_ANY_DIMM_MASK 0xAA |
| 74 | #define ANY_DIMM_MASK 0xFF |
| 75 | |
| 76 | #define DCT_PHY_FLAG 0 |
| 77 | #define DCT_EXTRA_FLAG 1 |
| 78 | #define SET_S3_SPECIAL_OFFSET(AccessType, Dct, Offset) ((AccessType << 11) | (Dct << 10) | Offset) |
| 79 | |
| 80 | /*---------------------------------------------------------------------------- |
| 81 | * TYPEDEFS, STRUCTURES, ENUMS |
| 82 | * |
| 83 | *---------------------------------------------------------------------------- |
| 84 | */ |
| 85 | /// struct for all the descriptor for pre exit self refresh and post exit self refresh |
| 86 | typedef struct _DESCRIPTOR_GROUP { |
| 87 | PCI_DEVICE_DESCRIPTOR PCIDevice[2]; ///< PCI device descriptor |
| 88 | CONDITIONAL_PCI_DEVICE_DESCRIPTOR CPCIDevice[2]; ///< Conditional PCI device descriptor |
| 89 | MSR_DEVICE_DESCRIPTOR MSRDevice[2]; ///< MSR device descriptor |
| 90 | CONDITIONAL_MSR_DEVICE_DESCRIPTOR CMSRDevice[2]; ///< Conditional MSR device descriptor |
| 91 | } DESCRIPTOR_GROUP; |
| 92 | |
| 93 | /// Northbridge block to be used in S3 resume and save. |
| 94 | typedef struct _S3_MEM_NB_BLOCK { |
| 95 | UINT8 MemS3SpecialCaseHeapSize; ///< Heap size for the special case register heap. |
| 96 | struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to the north bridge block. |
| 97 | VOID (*MemS3ExitSelfRefReg) (MEM_NB_BLOCK *NBPtr, AMD_CONFIG_PARAMS *StdHeaderPtr); ///< S3 Exit self refresh register |
| 98 | VOID (*MemS3GetConPCIMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for PCI register setting |
| 99 | VOID (*MemS3GetConMSRMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for MSR register setting |
| 100 | UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register |
| 101 | BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh |
| 102 | VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base |
| 103 | AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device |
| 104 | } S3_MEM_NB_BLOCK; |
| 105 | |
| 106 | /// Header for heap space to store the special case register. |
| 107 | typedef struct _S3_SPECIAL_CASE_HEAP_HEADER { |
Jonathan Neuschäfer | 45e6c82 | 2018-12-11 17:53:07 +0100 | [diff] [blame] | 108 | UINT8 Node; ///< Node ID for the header |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 109 | UINT8 Offset; ///< Offset for the target node |
| 110 | } S3_SPECIAL_CASE_HEAP_HEADER; |
| 111 | /*---------------------------------------------------------------------------- |
| 112 | * FUNCTIONS PROTOTYPE |
| 113 | * |
| 114 | *---------------------------------------------------------------------------- |
| 115 | */ |
| 116 | AGESA_STATUS |
| 117 | AmdMemS3Resume ( |
| 118 | IN AMD_CONFIG_PARAMS *StdHeader |
| 119 | ); |
| 120 | |
| 121 | AGESA_STATUS |
| 122 | MemS3ResumeInitNB ( |
| 123 | IN AMD_CONFIG_PARAMS *StdHeader |
| 124 | ); |
| 125 | |
| 126 | AGESA_STATUS |
| 127 | MemS3Deallocate ( |
| 128 | IN AMD_CONFIG_PARAMS *StdHeader |
| 129 | ); |
| 130 | |
| 131 | AGESA_STATUS |
| 132 | MemFS3GetPciDeviceRegisterList ( |
| 133 | IN PCI_DEVICE_DESCRIPTOR *Device, |
| 134 | OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, |
| 135 | IN AMD_CONFIG_PARAMS *StdHeader |
| 136 | ); |
| 137 | |
| 138 | AGESA_STATUS |
| 139 | MemFS3GetCPciDeviceRegisterList ( |
| 140 | IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, |
| 141 | OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, |
| 142 | IN AMD_CONFIG_PARAMS *StdHeader |
| 143 | ); |
| 144 | |
| 145 | AGESA_STATUS |
| 146 | MemFS3GetMsrDeviceRegisterList ( |
| 147 | IN MSR_DEVICE_DESCRIPTOR *Device, |
| 148 | OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, |
| 149 | IN AMD_CONFIG_PARAMS *StdHeader |
| 150 | ); |
| 151 | |
| 152 | AGESA_STATUS |
| 153 | MemFS3GetCMsrDeviceRegisterList ( |
| 154 | IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, |
| 155 | OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, |
| 156 | IN AMD_CONFIG_PARAMS *StdHeader |
| 157 | ); |
| 158 | |
| 159 | AGESA_STATUS |
| 160 | MemFS3GetDeviceList ( |
| 161 | IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr, |
| 162 | IN AMD_CONFIG_PARAMS *StdHeader |
| 163 | ); |
| 164 | |
| 165 | VOID |
| 166 | MemFS3Wait10ns ( |
| 167 | IN UINT32 Count, |
| 168 | IN OUT MEM_DATA_STRUCT *MemPtr |
| 169 | ); |
| 170 | |
| 171 | BOOLEAN |
| 172 | MemNS3ResumeNb ( |
| 173 | IN OUT S3_MEM_NB_BLOCK *S3NBPtr, |
| 174 | IN UINT8 NodeID |
| 175 | ); |
| 176 | |
| 177 | BOOLEAN |
| 178 | MemNS3ResumeClientNb ( |
| 179 | IN OUT S3_MEM_NB_BLOCK *S3NBPtr, |
| 180 | IN UINT8 NodeID |
| 181 | ); |
| 182 | |
| 183 | VOID |
| 184 | MemNS3GetConPCIMaskNb ( |
| 185 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 186 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 187 | ); |
| 188 | |
| 189 | VOID |
| 190 | MemNS3GetCSRNb ( |
| 191 | IN ACCESS_WIDTH AccessWidth, |
| 192 | IN PCI_ADDR Address, |
| 193 | IN VOID *Value, |
| 194 | IN OUT VOID *ConfigPtr |
| 195 | ); |
| 196 | |
| 197 | VOID |
| 198 | MemNS3SetCSRNb ( |
| 199 | IN ACCESS_WIDTH AccessWidth, |
| 200 | IN PCI_ADDR Address, |
| 201 | IN OUT VOID *Value, |
| 202 | IN OUT VOID *ConfigPtr |
| 203 | ); |
| 204 | |
| 205 | VOID |
| 206 | MemNS3GetBitFieldNb ( |
| 207 | IN ACCESS_WIDTH AccessWidth, |
| 208 | IN PCI_ADDR Address, |
| 209 | IN OUT VOID *Value, |
| 210 | IN OUT VOID *ConfigPtr |
| 211 | ); |
| 212 | |
| 213 | VOID |
| 214 | MemNS3SetBitFieldNb ( |
| 215 | IN ACCESS_WIDTH AccessWidth, |
| 216 | IN PCI_ADDR Address, |
| 217 | IN OUT VOID *Value, |
| 218 | IN OUT VOID *ConfigPtr |
| 219 | ); |
| 220 | |
| 221 | VOID |
| 222 | MemNS3RestoreScrubNb ( |
| 223 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 224 | IN UINT8 Node |
| 225 | ); |
| 226 | |
| 227 | AGESA_STATUS |
| 228 | MemS3InitNB ( |
| 229 | IN OUT S3_MEM_NB_BLOCK **S3NBPtr, |
| 230 | IN OUT MEM_DATA_STRUCT **MemPtr, |
| 231 | IN OUT MEM_MAIN_DATA_BLOCK *mmData, |
| 232 | IN AMD_CONFIG_PARAMS *StdHeader |
| 233 | ); |
| 234 | |
| 235 | VOID |
| 236 | MemNS3DisNbPsDbgNb ( |
| 237 | IN ACCESS_WIDTH AccessWidth, |
| 238 | IN PCI_ADDR Address, |
| 239 | IN OUT VOID *Value, |
| 240 | IN OUT VOID *ConfigPtr |
| 241 | ); |
| 242 | |
| 243 | VOID |
| 244 | MemNS3EnNbPsDbg1Nb ( |
| 245 | IN ACCESS_WIDTH AccessWidth, |
| 246 | IN PCI_ADDR Address, |
| 247 | IN OUT VOID *Value, |
| 248 | IN OUT VOID *ConfigPtr |
| 249 | ); |
| 250 | |
| 251 | VOID |
| 252 | MemNS3SetDynModeChangeNb ( |
| 253 | IN ACCESS_WIDTH AccessWidth, |
| 254 | IN PCI_ADDR Address, |
| 255 | IN OUT VOID *Value, |
| 256 | IN OUT VOID *ConfigPtr |
| 257 | ); |
| 258 | |
| 259 | VOID |
| 260 | MemNS3DisableChannelNb ( |
| 261 | IN ACCESS_WIDTH AccessWidth, |
| 262 | IN PCI_ADDR Address, |
| 263 | IN OUT VOID *Value, |
| 264 | IN OUT VOID *ConfigPtr |
| 265 | ); |
| 266 | |
| 267 | VOID |
| 268 | MemNS3SetDisAutoCompUnb ( |
| 269 | IN ACCESS_WIDTH AccessWidth, |
| 270 | IN PCI_ADDR Address, |
| 271 | IN OUT VOID *Value, |
| 272 | IN OUT VOID *ConfigPtr |
| 273 | ); |
| 274 | |
| 275 | VOID |
| 276 | MemNS3SetPreDriverCalUnb ( |
| 277 | IN ACCESS_WIDTH AccessWidth, |
| 278 | IN PCI_ADDR Address, |
| 279 | IN OUT VOID *Value, |
| 280 | IN OUT VOID *ConfigPtr |
| 281 | ); |
| 282 | |
| 283 | #endif //_MFS3_H_ |