Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mpuon3.c |
| 6 | * |
| 7 | * Platform specific settings for ON DDR3 U-DIMM system |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Ps/ON) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12 | * @e \$Revision: 46937 $ @e \$Date: 2011-02-11 08:50:58 -0700 (Fri, 11 Feb 2011) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | |
| 48 | #include "AGESA.h" |
| 49 | #include "Ids.h" |
| 50 | #include "AdvancedApi.h" |
| 51 | #include "mport.h" |
| 52 | #include "PlatformMemoryConfiguration.h" |
| 53 | #include "ma.h" |
| 54 | #include "cpuFamRegisters.h" |
| 55 | #include "mm.h" |
| 56 | #include "mn.h" |
| 57 | #include "mp.h" |
| 58 | #include "Filecode.h" |
| 59 | #define FILECODE PROC_MEM_PS_ON_MPUON3_FILECODE |
| 60 | /*---------------------------------------------------------------------------- |
| 61 | * DEFINITIONS AND MACROS |
| 62 | * |
| 63 | *---------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | /*---------------------------------------------------------------------------- |
| 67 | * TYPEDEFS AND STRUCTURES |
| 68 | * |
| 69 | *---------------------------------------------------------------------------- |
| 70 | */ |
| 71 | |
| 72 | /*---------------------------------------------------------------------------- |
| 73 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 74 | * |
| 75 | *---------------------------------------------------------------------------- |
| 76 | */ |
| 77 | BOOLEAN |
| 78 | STATIC |
| 79 | MemPDoPsUON3 ( |
| 80 | IN OUT MEM_NB_BLOCK *NBPtr |
| 81 | ); |
| 82 | |
| 83 | VOID |
| 84 | STATIC |
| 85 | MemPGetPORFreqLimitUON3 ( |
| 86 | IN OUT MEM_NB_BLOCK *NBPtr |
| 87 | ); |
| 88 | /* |
| 89 | *----------------------------------------------------------------------------- |
| 90 | * EXPORTED FUNCTIONS |
| 91 | * |
| 92 | *----------------------------------------------------------------------------- |
| 93 | */ |
| 94 | |
| 95 | STATIC CONST DRAM_TERM_ENTRY OnUDdr3DramTerm[] = { |
| 96 | {DDR800 + DDR1066, ONE_DIMM, NO_DIMM, 2, 0, 0}, |
| 97 | {DDR1333, ONE_DIMM, NO_DIMM, 1, 0, 0}, |
| 98 | {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, |
| 99 | {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2} |
| 100 | }; |
| 101 | |
| 102 | /* -----------------------------------------------------------------------------*/ |
| 103 | /** |
| 104 | * |
| 105 | * This function is the constructor for the platform specific settings for U-DDR3 ON DDR3 |
| 106 | * |
| 107 | * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE |
| 108 | * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT |
| 109 | * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK |
| 110 | * |
| 111 | * @return AGESA_SUCCESS |
| 112 | * |
| 113 | */ |
| 114 | |
| 115 | AGESA_STATUS |
| 116 | MemPConstructPsUON3 ( |
| 117 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 118 | IN OUT CH_DEF_STRUCT *ChannelPtr, |
| 119 | IN OUT MEM_PS_BLOCK *PsPtr |
| 120 | ) |
| 121 | { |
| 122 | ASSERT (MemPtr != 0); |
| 123 | ASSERT (ChannelPtr != 0); |
| 124 | |
| 125 | if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_14_ON) == 0) { |
| 126 | return AGESA_UNSUPPORTED; |
| 127 | } |
| 128 | if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { |
| 129 | return AGESA_UNSUPPORTED; |
| 130 | } |
| 131 | if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { |
| 132 | return AGESA_UNSUPPORTED; |
| 133 | } |
| 134 | PsPtr->MemPDoPs = MemPDoPsUON3; |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 135 | |
| 136 | if ((ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 137 | PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUON3; |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 138 | } else { |
| 139 | // Do not force frequency limit for Rev C |
| 140 | PsPtr->MemPGetPORFreqLimit = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; |
| 141 | } |
| 142 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 143 | return AGESA_SUCCESS; |
| 144 | } |
| 145 | |
| 146 | /* -----------------------------------------------------------------------------*/ |
| 147 | /** |
| 148 | * |
| 149 | * This is function sets the platform specific settings for U-DDR3 ON DDR3 |
| 150 | * |
| 151 | * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK |
| 152 | * |
| 153 | * @return TRUE - Find settings for corresponding platform and dimm population. |
| 154 | * @return FALSE - Fail to find settings for corresponding platform and dimm population. |
| 155 | * |
| 156 | */ |
| 157 | |
| 158 | BOOLEAN |
| 159 | STATIC |
| 160 | MemPDoPsUON3 ( |
| 161 | IN OUT MEM_NB_BLOCK *NBPtr |
| 162 | ) |
| 163 | { |
| 164 | if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (OnUDdr3DramTerm), OnUDdr3DramTerm)) { |
| 165 | return FALSE; |
| 166 | } |
| 167 | return TRUE; |
| 168 | } |
| 169 | |
| 170 | /* -----------------------------------------------------------------------------*/ |
| 171 | /** |
| 172 | * |
| 173 | * This is function gets the POR speed limit for U-DDR3 of ON |
| 174 | * |
| 175 | * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK |
| 176 | * |
| 177 | * |
| 178 | */ |
| 179 | |
| 180 | VOID |
| 181 | STATIC |
| 182 | MemPGetPORFreqLimitUON3 ( |
| 183 | IN OUT MEM_NB_BLOCK *NBPtr |
| 184 | ) |
| 185 | { |
| 186 | if ((NBPtr->DCTPtr->Timings.TargetSpeed == DDR1333_FREQUENCY) && (MemNGetBitFieldNb (NBPtr, BFFixedErrataSkipPorFreqCap) == 0)) { |
| 187 | NBPtr->DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY; |
| 188 | } |
| 189 | } |