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review.coreboot.org / coreboot / dbdf170dcdf9edbc860766606e53c6d647d89d38 / . / src / vendorcode / amd / agesa / f14 / Proc / Mem / NB / mntrain2.c
blob: 7902e36eee9427edd52efa03359528799c2ddba7 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * mntrain2.c
6 *
7 * Common Northbridge function for training flow for DDR2
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: (Mem/NB)
12 * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
13 *
14 **/
15/*
16 *****************************************************************************
17 *
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]20 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]30 * from this software without specific prior written permission.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]31 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]42 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]43 * ***************************************************************************
44 *
45 */
46
47/*
48 *----------------------------------------------------------------------------
49 * MODULES USED
50 *
51 *----------------------------------------------------------------------------
52 */
53
54
55
56#include "AGESA.h"
57#include "amdlib.h"
58#include "Ids.h"
59#include "OptionMemory.h"
60#include "mm.h"
61#include "mn.h"
62#include "mt.h"
63#include "Filecode.h"
64CODE_GROUP (G1_PEICC)
65RDATA_GROUP (G1_PEICC)
66
67#define FILECODE PROC_MEM_NB_MNTRAIN2_FILECODE
68/* features */
69#include "mftds.h"
70/*----------------------------------------------------------------------------
71 * DEFINITIONS AND MACROS
72 *
73 *----------------------------------------------------------------------------
74 */
75
76/*----------------------------------------------------------------------------
77 * TYPEDEFS AND STRUCTURES
78 *
79 *----------------------------------------------------------------------------
80 */
81
82/*----------------------------------------------------------------------------
83 * PROTOTYPES OF LOCAL FUNCTIONS
84 *
85 *----------------------------------------------------------------------------
86 */
87
88/*----------------------------------------------------------------------------
89 * EXPORTED FUNCTIONS
90 *
91 *----------------------------------------------------------------------------
92 */
93extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2;
94
95/* -----------------------------------------------------------------------------*/
96/**
97 *
98 * This function initiates DQS training
99 *
100 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
101 *
102 */
103
104BOOLEAN
105MemNDQSTiming2Nb (
106 IN OUT MEM_NB_BLOCK *NBPtr
107 )
108{
109 MEM_TECH_BLOCK *TechPtr;
110
111 TechPtr = NBPtr->TechPtr;
112 if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {
113 AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
114 AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr);
115 AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
116 //Execute Technology specific training features
117 if (memTechTrainingFeatDDR2.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {
118 if (memTechTrainingFeatDDR2.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {
119 MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);
120 if (memTechTrainingFeatDDR2.NonOptimizedSRdWrPosTraining (TechPtr)) {
121 if (memTechTrainingFeatDDR2.OptimizedSRdWrPosTraining (TechPtr)) {
122 MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);
123 if (memTechTrainingFeatDDR2.MaxRdLatencyTraining (TechPtr)) {
124 MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);
125 }
126 }
127 }
128 }
129 }
130 MemTMarkTrainFail (TechPtr);
131 }
132 return TRUE;
133}