Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mnregon.c |
| 6 | * |
| 7 | * Common Northbridge register related functions for ON |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/NB/ON) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12 | * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 0deb355 | 2014-05-15 21:07:16 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 0deb355 | 2014-05-15 21:07:16 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 0deb355 | 2014-05-15 21:07:16 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 0deb355 | 2014-05-15 21:07:16 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | /* |
| 47 | *---------------------------------------------------------------------------- |
| 48 | * MODULES USED |
| 49 | * |
| 50 | *---------------------------------------------------------------------------- |
| 51 | */ |
| 52 | |
| 53 | |
| 54 | |
| 55 | #include "AGESA.h" |
| 56 | #include "AdvancedApi.h" |
| 57 | #include "amdlib.h" |
| 58 | #include "Ids.h" |
| 59 | #include "OptionMemory.h" |
| 60 | #include "mm.h" |
| 61 | #include "mn.h" |
| 62 | #include "mnon.h" |
| 63 | #include "merrhdl.h" |
| 64 | #include "cpuRegisters.h" |
| 65 | #include "cpuFamRegisters.h" |
| 66 | #include "cpuFamilyTranslation.h" |
| 67 | #include "heapManager.h" |
| 68 | #include "Filecode.h" |
| 69 | #define FILECODE PROC_MEM_NB_ON_MNREGON_FILECODE |
| 70 | /*---------------------------------------------------------------------------- |
| 71 | * DEFINITIONS AND MACROS |
| 72 | * |
| 73 | *---------------------------------------------------------------------------- |
| 74 | */ |
| 75 | #define PHY_DIRECT_ADDRESS_MASK 0x0D000000 |
| 76 | |
| 77 | STATIC CONST UINT8 InstancesPerTypeON[8] = {8, 2, 1, 0, 2, 0, 1, 1}; |
| 78 | |
| 79 | /*---------------------------------------------------------------------------- |
| 80 | * TYPEDEFS AND STRUCTURES |
| 81 | * |
| 82 | *---------------------------------------------------------------------------- |
| 83 | */ |
| 84 | |
| 85 | /*---------------------------------------------------------------------------- |
| 86 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 87 | * |
| 88 | *---------------------------------------------------------------------------- |
| 89 | */ |
| 90 | |
| 91 | /*---------------------------------------------------------------------------- |
| 92 | * EXPORTED FUNCTIONS |
| 93 | * |
| 94 | *---------------------------------------------------------------------------- |
| 95 | */ |
| 96 | /*-----------------------------------------------------------------------------*/ |
| 97 | /** |
| 98 | * |
| 99 | * This function matches the CPU_LOGICAL_ID with certain criteria to |
| 100 | * determine if it is supported by this NBBlock. |
| 101 | * |
| 102 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 103 | * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID |
| 104 | * |
| 105 | * @return TRUE - This node is a Ontario. |
| 106 | * @return FALSE - This node is not a Ontario. |
| 107 | */ |
| 108 | BOOLEAN |
| 109 | MemNIsIdSupportedON ( |
| 110 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 111 | IN CPU_LOGICAL_ID *LogicalIdPtr |
| 112 | ) |
| 113 | { |
| 114 | if (((LogicalIdPtr->Family & AMD_FAMILY_14_ON) != 0) |
| 115 | && ((LogicalIdPtr->Revision & AMD_F14_ALL) != 0)) { |
| 116 | return TRUE; |
| 117 | } else { |
| 118 | return FALSE; |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | /* -----------------------------------------------------------------------------*/ |
| 123 | /** |
| 124 | * |
| 125 | * Check if bitfields of all enabled DCTs on a die have the expected value. Ignore |
| 126 | * DCTs that are disabled. |
| 127 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 128 | * @param[in] FieldName - Bit Field name |
| 129 | * @param[in] Field - Value to be checked |
| 130 | * |
| 131 | * @return TRUE - All enabled DCTs have the expected value on the bitfield. |
| 132 | * @return FALSE - Not all enabled DCTs have the expected value on the bitfield. |
| 133 | * |
| 134 | * ---------------------------------------------------------------------------- |
| 135 | */ |
| 136 | BOOLEAN |
| 137 | MemNBrdcstCheckON ( |
| 138 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 139 | IN BIT_FIELD_NAME FieldName, |
| 140 | IN UINT32 Field |
| 141 | ) |
| 142 | { |
| 143 | if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) { |
| 144 | return FALSE; |
| 145 | } |
| 146 | return TRUE; |
| 147 | } |
| 148 | |
| 149 | /*---------------------------------------------------------------------------- |
| 150 | * LOCAL FUNCTIONS |
| 151 | * |
| 152 | *----------------------------------------------------------------------------*/ |
| 153 | |
| 154 | /* -----------------------------------------------------------------------------*/ |
| 155 | /** |
| 156 | * |
| 157 | * |
| 158 | * This function gets or sets a value to a bit field in a PCI register. |
| 159 | * |
| 160 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 161 | * @param[in] FieldName - Bit Field to be programmed |
| 162 | * @param[in] Field - Value to be programmed |
| 163 | * @param[in] IsSet - Indicates if the function will set or get |
| 164 | * |
| 165 | * @return value read, if the function is used as a "get" |
| 166 | */ |
| 167 | |
| 168 | UINT32 |
| 169 | MemNCmnGetSetFieldON ( |
| 170 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 171 | IN UINT8 IsSet, |
| 172 | IN BIT_FIELD_NAME FieldName, |
| 173 | IN UINT32 Field |
| 174 | ) |
| 175 | { |
| 176 | TSEFO Address; |
| 177 | PCI_ADDR PciAddr; |
| 178 | UINT8 Type; |
| 179 | UINT8 IsLinked; |
| 180 | UINT32 Value; |
| 181 | UINT32 Highbit; |
| 182 | UINT32 Lowbit; |
| 183 | UINT32 Mask; |
| 184 | UINT8 IsPhyDirectAccess; |
| 185 | UINT8 IsWholeRegAccess; |
| 186 | UINT8 NumOfInstances; |
| 187 | UINT8 Instance; |
| 188 | |
| 189 | Value = 0; |
Edward O'Callaghan | 0deb355 | 2014-05-15 21:07:16 +1000 | [diff] [blame] | 190 | if (FieldName < BFEndOfList) { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 191 | Address = NBPtr->NBRegTable[FieldName]; |
| 192 | if (Address) { |
| 193 | Lowbit = TSEFO_END (Address); |
| 194 | Highbit = TSEFO_START (Address); |
| 195 | Type = (UINT8) TSEFO_TYPE (Address); |
| 196 | IsLinked = (UINT8) TSEFO_LINKED (Address); |
| 197 | IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address); |
| 198 | IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address); |
| 199 | |
| 200 | ASSERT ((Address & ((UINT32) 1) << 29) == 0); // Old Phy direct access method is not supported |
| 201 | |
| 202 | Address = TSEFO_OFFSET (Address); |
| 203 | |
| 204 | // By default, a bit field has only one instance |
| 205 | NumOfInstances = 1; |
| 206 | |
| 207 | if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { |
| 208 | Address |= PHY_DIRECT_ADDRESS_MASK; |
| 209 | if (IsWholeRegAccess) { |
| 210 | // In the case of whole regiter access (bit 0 to 15), |
| 211 | // HW broadcast and nibble mask will be used. |
| 212 | Address |= Lowbit << 16; |
| 213 | Lowbit = 0; |
| 214 | Highbit = 15; |
| 215 | } else { |
| 216 | // In the case only some bits on a register is accessed, |
| 217 | // BIOS will do read-mod-write to all chiplets manually. |
| 218 | // And nibble mask will be 1111b always. |
| 219 | Address |= 0x000F0000; |
| 220 | Field >>= Lowbit; |
| 221 | if ((Address & 0x0F00) == 0x0F00) { |
| 222 | // Broadcast mode |
| 223 | // Find out how many instances to write to |
| 224 | NumOfInstances = InstancesPerTypeON[(Address >> 13) & 0x7]; |
| 225 | if (!IsSet) { |
| 226 | // For read, only read from instance 0 in broadcast mode |
| 227 | NumOfInstances = 1; |
| 228 | } |
| 229 | } |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | ASSERT (NumOfInstances > 0); |
| 234 | |
| 235 | for (Instance = 0; Instance < NumOfInstances; Instance++) { |
| 236 | if (Type == NB_ACCESS) { |
| 237 | PciAddr.AddressValue = Address; |
| 238 | PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; |
| 239 | PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; |
| 240 | PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; |
| 241 | Address = PciAddr.AddressValue; |
| 242 | LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); |
| 243 | if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && |
| 244 | (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { |
Konstantin Aladyshev | 8656914 | 2017-08-01 14:29:20 +0300 | [diff] [blame] | 245 | IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 246 | } |
| 247 | } else if (Type == DCT_PHY_ACCESS) { |
| 248 | if (IsPhyDirectAccess && (NumOfInstances > 1)) { |
| 249 | Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8); |
| 250 | } |
| 251 | MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); |
| 252 | MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); |
| 253 | Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); |
| 254 | IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); |
| 255 | } else if (Type == DCT_EXTRA) { |
| 256 | MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); |
| 257 | MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); |
| 258 | Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); |
| 259 | IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); |
| 260 | } else { |
| 261 | IDS_ERROR_TRAP; |
| 262 | } |
| 263 | |
| 264 | if (IsSet) { |
| 265 | // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case |
| 266 | if ((Highbit - Lowbit) != 31) { |
| 267 | Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); |
| 268 | } else { |
| 269 | Mask = (UINT32)0xFFFFFFFF; |
| 270 | } |
| 271 | Value &= ~(Mask << Lowbit); |
| 272 | Value |= (Field & Mask) << Lowbit; |
| 273 | |
| 274 | if (Type == NB_ACCESS) { |
| 275 | PciAddr.AddressValue = Address; |
| 276 | LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); |
| 277 | if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && |
| 278 | (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { |
Konstantin Aladyshev | 8656914 | 2017-08-01 14:29:20 +0300 | [diff] [blame] | 279 | IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 280 | } |
| 281 | } else if (Type == DCT_PHY_ACCESS) { |
| 282 | MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); |
| 283 | Address |= DCT_ACCESS_WRITE; |
| 284 | MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); |
| 285 | MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); |
| 286 | IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); |
| 287 | } else if (Type == DCT_EXTRA) { |
| 288 | MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); |
| 289 | Address |= DCT_ACCESS_WRITE; |
| 290 | MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); |
| 291 | MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); |
| 292 | IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); |
| 293 | } else { |
| 294 | IDS_ERROR_TRAP; |
| 295 | } |
| 296 | if (IsLinked) { |
| 297 | MemNCmnGetSetFieldON (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); |
| 298 | } |
| 299 | } else { |
| 300 | Value = Value >> Lowbit; // Shift |
| 301 | // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case |
| 302 | if ((Highbit - Lowbit) != 31) { |
| 303 | Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); |
| 304 | } |
| 305 | if (IsLinked) { |
| 306 | Value |= MemNCmnGetSetFieldON (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); |
| 307 | } |
| 308 | // For direct phy access, shift the bit back for compatibility reason. |
| 309 | if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { |
| 310 | Value <<= Lowbit; |
| 311 | } |
| 312 | } |
| 313 | } |
| 314 | } |
| 315 | } else { |
| 316 | IDS_ERROR_TRAP; // Invalid bit field index |
| 317 | } |
| 318 | return Value; |
| 319 | } |
| 320 | |
| 321 | |
| 322 | /* -----------------------------------------------------------------------------*/ |
| 323 | /** |
| 324 | * |
| 325 | * This function initializes bit field translation table |
| 326 | * |
| 327 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 328 | * @param[in,out] NBRegTable[] - Pointer to the bit field data structure |
| 329 | * |
| 330 | */ |
| 331 | |
| 332 | VOID |
| 333 | MemNInitNBRegTableON ( |
| 334 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 335 | IN OUT TSEFO NBRegTable[] |
| 336 | ) |
| 337 | { |
| 338 | UINT16 i; |
| 339 | for (i = 0; i < BFEndOfList; i++) { |
| 340 | NBRegTable[i] = 0; |
| 341 | } |
| 342 | |
| 343 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); |
| 344 | |
| 345 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); |
| 346 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); |
| 347 | |
| 348 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); |
| 349 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); |
| 350 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 351 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 352 | |
| 353 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); |
| 354 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); |
| 355 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); |
| 356 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); |
| 357 | |
| 358 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); |
| 359 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); |
| 360 | |
| 361 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); |
| 362 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); |
| 363 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); |
| 364 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); |
| 365 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); |
| 366 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); |
| 367 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); |
| 368 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); |
| 369 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); |
| 370 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); |
| 371 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); |
| 372 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); |
| 373 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); |
| 374 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); |
| 375 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); |
| 376 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); |
| 377 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); |
| 378 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); |
| 379 | |
| 380 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); |
| 381 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); |
| 382 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 6, 6, BFRxPtrInitReq); |
| 383 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); |
| 384 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); |
| 385 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); |
| 386 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn); |
| 387 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 20, 20, BFForceCasToSlot0); |
| 388 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 21, 21, BFDisCutThroughMode); |
| 389 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); |
| 390 | |
| 391 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); |
| 392 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); |
| 393 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); |
| 394 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); |
| 395 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); |
| 396 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); |
| 397 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); |
| 398 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); |
| 399 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); |
| 400 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); |
| 401 | |
| 402 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); |
| 403 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); |
| 404 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); |
| 405 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); |
| 406 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); |
| 407 | |
| 408 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); |
| 409 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); |
| 410 | |
| 411 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); |
| 412 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); |
| 413 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); |
| 414 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); |
| 415 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); |
| 416 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); |
| 417 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); |
| 418 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); |
| 419 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); |
| 420 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); |
| 421 | |
| 422 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); |
| 423 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); |
| 424 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); |
| 425 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 22, 21, BFIdleCycInit); |
| 426 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 25, 25, BFEnDispAutoPrecharge); |
| 427 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 26, 26, BFDbeSkidBufDis); |
| 428 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); |
| 429 | |
| 430 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 4, 0, BFMemClkFreq); |
| 431 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 7, 7, BFMemClkFreqVal); |
| 432 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); |
| 433 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); |
| 434 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); |
| 435 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); |
| 436 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); |
| 437 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); |
| 438 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); |
| 439 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); |
| 440 | |
| 441 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 0, 0, BFDoubleTrefRateEn); |
| 442 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 2, 1, BFThrottleEn); |
| 443 | |
| 444 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 21, BFDbeGskMemClkAlignMode); |
| 445 | |
| 446 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xAC), 0, 0, BFMemTempHot); |
| 447 | |
| 448 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xC0), 0, 0, BFTraceModeEn); |
| 449 | |
| 450 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); |
| 451 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); |
| 452 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); |
| 453 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); |
| 454 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 9, 9, BFDctSelBankSwap); |
| 455 | |
| 456 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 19, 19, BFC6DramLock); |
| 457 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); |
| 458 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFDctWrLimit); |
| 459 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 23, 23, BFRdTrainGo); |
| 460 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 22, 22, BFRdDramTrainMode); |
| 461 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 20, 20, BFDramTrainPdbDis); |
| 462 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 17, 2, BFTrainLength); |
| 463 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 1, 1, BFWrTrainGo); |
| 464 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 0, 0, BFWrDramTrainMode); |
| 465 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C8), 31, 0, BFWrTrainAdrPtrLo); |
| 466 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1CC), 17, 16, BFWrTrainAdrPtrHi); |
| 467 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D0), 9, 0, BFWrTrainBufAddr); |
| 468 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D4), 31, 0, BFWrTrainBufDat); |
| 469 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 15, 8, BFTrainCmpSts2); |
| 470 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 7, 0, BFTrainCmpSts); |
| 471 | |
| 472 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 19, 19, BFNclkFreqDone); |
| 473 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 5, 0, BFMainPllOpFreqId); |
| 474 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 26, 20, BFNbPs0NclkDiv); |
| 475 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); |
| 476 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 22, 22, BFEnCpuSerRdBehindNpIoWr); |
| 477 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 6, 0, BFNbPs1NclkDiv); |
| 478 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 28, 28, BFNbPsForceReq); |
| 479 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 30, 30, BFNbPsCtrlDis); |
| 480 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 30, 30, BFNbPsCsrAccSel); |
| 481 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 31, 31, BFNbPsDbgEn); |
| 482 | |
| 483 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x12C), 11, 0, BFC6Base); |
| 484 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x164), 0, 0, BFFixedErrataSkipPorFreqCap); |
| 485 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 29, 29, BFDramSrHysEn); |
| 486 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 28, 26, BFDramSrHys); |
| 487 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn); |
| 488 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn); |
| 489 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 0, BFAcpiPwrStsCtrlHi); |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 490 | MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x1FC), 2, 2, BFLowPowerDefault); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 491 | |
| 492 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren); |
| 493 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren); |
| 494 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10, 8, BFAddrCmdDrvStren); |
| 495 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren); |
| 496 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren); |
| 497 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren); |
| 498 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 30, 28, BFProcOdt); |
| 499 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); |
| 500 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); |
| 501 | |
| 502 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); |
| 503 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); |
| 504 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); |
| 505 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 4, 4, BFTrDimmSel); |
| 506 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 7, 6, BFFenceTrSel); |
| 507 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); |
| 508 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); |
| 509 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); |
| 510 | |
| 511 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg); |
| 512 | |
| 513 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); |
| 514 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); |
| 515 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); |
| 516 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); |
| 517 | |
| 518 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 25, 24, BFRxDLLWakeupTime); |
| 519 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 22, 20, BFRxCPUpdPeriod); |
| 520 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock); |
| 521 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 9, 8, BFTxDLLWakeupTime); |
| 522 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 6, 4, BFTxCPUpdPeriod); |
| 523 | MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 3, 0, BFTxMaxDurDllNoLock); |
| 524 | |
| 525 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby); |
| 526 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 7, 0, BFPhy0x0D0F0F13Bit0to7); |
| 527 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal); |
| 528 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime); |
| 529 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2030, 4, 4, BFPhyClkConfig0); |
| 530 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2130, 4, 4, BFPhyClkConfig1); |
| 531 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC000, 8, 8, BFLowPowerDrvStrengthEn); |
| 532 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15, 0, BFAddrCmdTri); |
| 533 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks); |
| 534 | |
| 535 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14, 0, BFDataFence2); |
| 536 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31, 4, 0, BFClkFence2); |
| 537 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31, 4, 0, BFCmdFence2); |
| 538 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031, 4, 0, BFAddrFence2); |
| 539 | |
| 540 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal); |
| 541 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15, 0, BFDataByteTxPreDriverCal2Pad1); |
| 542 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15, 0, BFDataByteTxPreDriverCal2Pad2); |
| 543 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15, 0, BFCmdAddr0TxPreDriverCal2Pad1); |
| 544 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15, 0, BFCmdAddr0TxPreDriverCal2Pad2); |
| 545 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15, 0, BFCmdAddr1TxPreDriverCal2Pad1); |
| 546 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15, 0, BFCmdAddr1TxPreDriverCal2Pad2); |
| 547 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15, 0, BFAddrTxPreDriverCal2Pad1); |
| 548 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15, 0, BFAddrTxPreDriverCal2Pad2); |
| 549 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15, 0, BFAddrTxPreDriverCal2Pad3); |
| 550 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15, 0, BFAddrTxPreDriverCal2Pad4); |
| 551 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 0, BFCmdAddr0TxPreDriverCalPad0); |
| 552 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 0, BFCmdAddr1TxPreDriverCalPad0); |
| 553 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 0, BFAddrTxPreDriverCalPad0); |
| 554 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 0, BFClock0TxPreDriverCalPad0); |
| 555 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 0, BFClock1TxPreDriverCalPad0); |
| 556 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1C00, 15, 0, BFPNOdtCal); |
| 557 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1D00, 15, 0, BFPNDrvCal); |
| 558 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D081E00, 15, 0, BFCalVal); |
| 559 | |
| 560 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl); |
| 561 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl); |
| 562 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl); |
| 563 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl); |
| 564 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl); |
| 565 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 566 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F00, 6, 4, BFDQOdt03); |
| 567 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F08, 6, 4, BFDQOdt47); |
| 568 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 569 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1E, 14, 12, BFDllCSRBisaTrimDByte); |
| 570 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1E, 14, 12, BFDllCSRBisaTrimClk); |
| 571 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1E, 14, 12, BFDllCSRBisaTrimCsOdt); |
| 572 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FCF1E, 14, 12, BFDllCSRBisaTrimAByte2); |
| 573 | MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F38, 14, 13, BFReduceLoop); |
| 574 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 575 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11, 8, BFTwrrdSD); |
| 576 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); |
| 577 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); |
| 578 | |
| 579 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x30, 12, 0, BFDbeGskFifoNumerator); |
| 580 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x31, 12, 0, BFDbeGskFifoDenominator); |
| 581 | |
| 582 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 4, 0, BFDataTxFifoSchedDlySlot0); |
| 583 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 7, 7, BFDataTxFifoSchedDlyNegSlot0); |
| 584 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 12, 8, BFDataTxFifoSchedDlySlot1); |
| 585 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 15, 15, BFDataTxFifoSchedDlyNegSlot1); |
| 586 | |
| 587 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 3, 0, BFTrcd); |
| 588 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 11, 8, BFTrp); |
| 589 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 20, 16, BFTras); |
| 590 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 29, 24, BFTrc); |
| 591 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 2, 0, BFTrtp); |
| 592 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 10, 8, BFTrrd); |
| 593 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 18, 16, BFTwtr); |
| 594 | |
| 595 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 2, 0, BFRdOdtTrnOnDly); |
| 596 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 6, 4, BFRdOdtOnDuration); |
| 597 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 8, 8, BFWrOdtTrnOnDly); |
| 598 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 14, 12, BFWrOdtOnDuration); |
| 599 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFRdOdtPatReg); |
| 600 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFWrOdtPatReg); |
| 601 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 3, 0, BFTxp); |
| 602 | MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 12, 8, BFTxpdll); |
| 603 | |
| 604 | LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); |
| 605 | LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); |
| 606 | LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); |
| 607 | } |