Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mmNodeInterleave.c |
| 6 | * |
| 7 | * Main Memory Feature implementation file for Node Interleaving |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Main) |
| 12 | * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ |
| 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /* |
| 48 | *---------------------------------------------------------------------------- |
| 49 | * MODULES USED |
| 50 | * |
| 51 | *---------------------------------------------------------------------------- |
| 52 | */ |
| 53 | |
| 54 | |
| 55 | #include "Porting.h" |
| 56 | #include "AGESA.h" |
| 57 | #include "amdlib.h" |
| 58 | #include "Ids.h" |
| 59 | #include "cpuRegisters.h" |
| 60 | #include "cpuServices.h" |
| 61 | #include "cpuApicUtilities.h" |
| 62 | #include "GeneralServices.h" |
| 63 | #include "OptionMemory.h" |
| 64 | #include "mm.h" |
| 65 | #include "mn.h" |
| 66 | #include "mt.h" |
| 67 | #include "ma.h" |
| 68 | #include "mu.h" |
| 69 | #include "mfParallelTraining.h" |
| 70 | #include "GeneralServices.h" |
| 71 | #include "heapManager.h" |
| 72 | #include "merrhdl.h" |
| 73 | #include "Filecode.h" |
| 74 | CODE_GROUP (G2_PEI) |
| 75 | RDATA_GROUP (G2_PEI) |
| 76 | |
| 77 | #define FILECODE PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE |
| 78 | |
| 79 | extern MEM_FEAT_BLOCK_MAIN MemFeatMain; |
| 80 | /*----------------------------------------------------------------------------- |
| 81 | * EXPORTED FUNCTIONS |
| 82 | * |
| 83 | *----------------------------------------------------------------------------- |
| 84 | */ |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 85 | |
| 86 | BOOLEAN |
| 87 | MemMParallelTraining ( |
| 88 | IN OUT MEM_MAIN_DATA_BLOCK *mmPtr |
| 89 | ); |
| 90 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 91 | /* -----------------------------------------------------------------------------*/ |
| 92 | /** |
| 93 | * |
| 94 | * |
| 95 | * |
| 96 | * |
| 97 | * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK |
| 98 | * |
| 99 | * @return TRUE - No fatal error occurs. |
| 100 | * @return FALSE - Fatal error occurs. |
| 101 | */ |
| 102 | BOOLEAN |
| 103 | MemMParallelTraining ( |
| 104 | IN OUT MEM_MAIN_DATA_BLOCK *mmPtr |
| 105 | ) |
| 106 | { |
| 107 | AMD_CONFIG_PARAMS *StdHeader; |
| 108 | MEM_DATA_STRUCT *MemPtr; |
| 109 | MEM_NB_BLOCK *NBPtr; |
| 110 | DIE_INFO TrainInfo[MAX_NODES_SUPPORTED]; |
| 111 | AP_DATA_TRANSFER ReturnData; |
| 112 | AGESA_STATUS Status; |
| 113 | UINT8 ApSts; |
| 114 | UINT8 Die; |
| 115 | UINT8 Socket; |
| 116 | UINT32 Module; |
| 117 | UINT32 LowCore; |
| 118 | UINT32 HighCore; |
| 119 | UINT32 Time; |
| 120 | UINT32 TimeOut; |
| 121 | BOOLEAN StillTraining; |
| 122 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 123 | UINT8 *BufferPtr; |
| 124 | BOOLEAN TimeoutEn; |
| 125 | |
| 126 | NBPtr = mmPtr->NBPtr; |
| 127 | MemPtr = mmPtr->MemPtr; |
| 128 | StdHeader = &(mmPtr->MemPtr->StdHeader); |
| 129 | Time = 0; |
| 130 | TimeOut = PARALLEL_TRAINING_TIMEOUT; |
| 131 | TimeoutEn = TRUE; |
| 132 | IDS_TIMEOUT_CTL (&TimeoutEn); |
| 133 | |
| 134 | IDS_HDT_CONSOLE (MEM_STATUS, "\nStart parallel training\n"); |
| 135 | AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, StdHeader); |
| 136 | // |
| 137 | // Initialize Training Info Array |
| 138 | // |
| 139 | for (Die = 0; Die < mmPtr->DieCount; Die ++) { |
| 140 | Socket = TrainInfo[Die].Socket = NBPtr[Die].MCTPtr->SocketId; |
| 141 | Module = NBPtr[Die].MCTPtr->DieId; |
| 142 | GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); |
| 143 | TrainInfo[Die].Core = (UINT8) (LowCore & 0x000000FF); |
| 144 | IDS_HDT_CONSOLE (MEM_FLOW, "\tLaunch core %d of socket %d\n", LowCore, Socket); |
| 145 | TrainInfo[Die].Training = FALSE; |
| 146 | } |
| 147 | // |
| 148 | // Start Training on Each remote die. |
| 149 | // |
| 150 | for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { |
| 151 | if (Die != BSP_DIE) { |
| 152 | NBPtr[Die].BeforeDqsTraining (&(mmPtr->NBPtr[Die])); |
| 153 | if (NBPtr[Die].MCTPtr->NodeMemSize != 0) { |
| 154 | if (!NBPtr[Die].FeatPtr->Training (&(mmPtr->NBPtr[Die]))) { |
| 155 | // Fail to launch code on AP |
| 156 | PutEventLog (AGESA_ERROR, MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); |
| 157 | SetMemError (AGESA_ERROR, NBPtr[Die].MCTPtr); |
| 158 | MemPtr->ErrorHandling (NBPtr[Die].MCTPtr, EXCLUDE_ALL_DCT, EXCLUDE_ALL_CHIPSEL, &MemPtr->StdHeader); |
| 159 | } else { |
| 160 | TrainInfo[Die].Training = TRUE; |
| 161 | } |
| 162 | } |
| 163 | } |
| 164 | } |
| 165 | // |
| 166 | // Call training on BSP |
| 167 | // |
| 168 | IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr[BSP_DIE].Node); |
| 169 | NBPtr[BSP_DIE].BeforeDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); |
| 170 | NBPtr[BSP_DIE].TrainingFlow (&(mmPtr->NBPtr[BSP_DIE])); |
| 171 | NBPtr[BSP_DIE].AfterDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); |
| 172 | |
| 173 | // |
| 174 | // Get Results from remote processors training |
| 175 | // |
| 176 | do { |
| 177 | StillTraining = FALSE; |
| 178 | for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { |
| 179 | // |
| 180 | // For each Die that is training, read the status |
| 181 | // |
| 182 | if (TrainInfo[Die].Training == TRUE) { |
| 183 | ApSts = ApUtilReadRemoteControlByte (TrainInfo[Die].Socket, TrainInfo[Die].Core, StdHeader); |
| 184 | if ((ApSts & 0x80) == 0) { |
| 185 | // |
| 186 | // Allocate buffer for received data |
| 187 | // |
| 188 | AllocHeapParams.RequestedBufferSize = ( |
| 189 | sizeof (DIE_STRUCT) + |
| 190 | NBPtr[Die].DctCount * ( |
| 191 | sizeof (DCT_STRUCT) + ( |
| 192 | NBPtr[Die].ChannelCount * ( |
| 193 | sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( |
| 194 | (NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * |
| 195 | NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * |
| 196 | NUMBER_OF_DELAY_TABLES) + |
| 197 | (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) |
| 198 | ) |
| 199 | ) |
| 200 | ) |
| 201 | ) |
| 202 | ) + 3; |
| 203 | AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Die, 0, 0); |
| 204 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 205 | if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { |
| 206 | // |
| 207 | // Receive Training Results |
| 208 | // |
| 209 | |
| 210 | ReturnData.DataPtr = AllocHeapParams.BufferPtr; |
| 211 | ReturnData.DataSizeInDwords = (UINT16) AllocHeapParams.RequestedBufferSize / 4; |
| 212 | ReturnData.DataTransferFlags = 0; |
| 213 | Status = ApUtilReceiveBuffer (TrainInfo[Die].Socket, TrainInfo[Die].Core, &ReturnData, StdHeader); |
| 214 | if (Status != AGESA_SUCCESS) { |
| 215 | SetMemError (Status, NBPtr[Die].MCTPtr); |
| 216 | } |
| 217 | |
| 218 | BufferPtr = AllocHeapParams.BufferPtr; |
| 219 | LibAmdMemCopy (NBPtr[Die].MCTPtr, BufferPtr, sizeof (DIE_STRUCT), StdHeader); |
| 220 | BufferPtr += sizeof (DIE_STRUCT); |
| 221 | LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData, |
| 222 | BufferPtr, |
| 223 | NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)), |
| 224 | StdHeader); |
| 225 | BufferPtr += NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)); |
| 226 | LibAmdMemCopy ( NBPtr[Die].PSBlock, |
| 227 | BufferPtr, |
| 228 | NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK), |
| 229 | StdHeader); |
| 230 | BufferPtr += NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK); |
| 231 | LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData[0].ChData[0].RcvEnDlys, |
| 232 | BufferPtr, |
| 233 | (NBPtr[Die].DctCount * NBPtr[Die].ChannelCount) * |
| 234 | ((NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * |
| 235 | NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * |
| 236 | NUMBER_OF_DELAY_TABLES) + |
| 237 | (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) |
| 238 | ), |
| 239 | StdHeader); |
| 240 | |
| 241 | HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); |
| 242 | |
| 243 | NBPtr[Die].AfterDqsTraining (&(mmPtr->NBPtr[Die])); |
| 244 | TrainInfo[Die].Training = FALSE; |
| 245 | } else { |
| 246 | PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA, NBPtr[Die].Node, 0, 0, 0, StdHeader); |
| 247 | SetMemError (AGESA_FATAL, NBPtr[Die].MCTPtr); |
| 248 | ASSERT(FALSE); // Insufficient Heap Space allocation for parallel training buffer |
| 249 | } |
| 250 | } else if (ApSts == CORE_IDLE) { |
| 251 | // AP does not have buffer to transmit to BSP |
| 252 | // AP fails to locate a buffer for data transfer |
| 253 | TrainInfo[Die].Training = FALSE; |
| 254 | } else { |
| 255 | // Signal to loop through again |
| 256 | StillTraining = TRUE; |
| 257 | } |
| 258 | } |
| 259 | } |
| 260 | // Wait for 1 us |
| 261 | MemUWait10ns (100, NBPtr->MemPtr); |
| 262 | Time ++; |
| 263 | } while ((StillTraining) && ((Time < TimeOut) || !TimeoutEn)); // Continue until all Dies are finished |
| 264 | // if cannot finish in 1 s, do fatal exit |
| 265 | |
| 266 | if (StillTraining && TimeoutEn) { |
| 267 | // Parallel training time out, do fatal exit, as there is at least one AP hangs. |
| 268 | PutEventLog (AGESA_FATAL, MEM_ERROR_PARALLEL_TRAINING_TIME_OUT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); |
| 269 | SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); |
| 270 | ASSERT(FALSE); // Timeout occurred while still training |
| 271 | } |
| 272 | |
| 273 | for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { |
| 274 | if (NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { |
| 275 | return FALSE; |
| 276 | } |
| 277 | } |
| 278 | return TRUE; |
| 279 | } |