Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mmLvDdr3.c |
| 6 | * |
| 7 | * Main Memory Feature implementation file for low voltage DDR3 support |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Main) |
| 12 | * @e \$Revision: 38415 $ @e \$Date: 2010-09-24 03:30:59 +0800 (Fri, 24 Sep 2010) $ |
| 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /* |
| 48 | *---------------------------------------------------------------------------- |
| 49 | * MODULES USED |
| 50 | * |
| 51 | *---------------------------------------------------------------------------- |
| 52 | */ |
| 53 | |
| 54 | |
| 55 | #include "AGESA.h" |
| 56 | #include "Ids.h" |
| 57 | #include "amdlib.h" |
| 58 | #include "OptionMemory.h" |
| 59 | #include "mm.h" |
| 60 | #include "mn.h" |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 61 | #include "mmlvddr3.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 62 | #include "Filecode.h" |
| 63 | CODE_GROUP (G1_PEICC) |
| 64 | RDATA_GROUP (G1_PEICC) |
| 65 | |
| 66 | #define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE |
| 67 | |
| 68 | extern MEM_FEAT_BLOCK_MAIN MemFeatMain; |
| 69 | /*----------------------------------------------------------------------------- |
| 70 | * EXPORTED FUNCTIONS |
| 71 | * |
| 72 | *----------------------------------------------------------------------------- |
| 73 | */ |
| 74 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 75 | BOOLEAN |
| 76 | MemMLvDdr3 ( |
| 77 | IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr |
| 78 | ); |
| 79 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 80 | /* -----------------------------------------------------------------------------*/ |
| 81 | /** |
| 82 | * |
| 83 | * Find the common supported voltage on all nodes. |
| 84 | * |
| 85 | * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK |
| 86 | * |
| 87 | * @return TRUE - No fatal error occurs. |
| 88 | * @return FALSE - Fatal error occurs. |
| 89 | */ |
| 90 | BOOLEAN |
| 91 | MemMLvDdr3 ( |
| 92 | IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr |
| 93 | ) |
| 94 | { |
| 95 | UINT8 Node; |
| 96 | BOOLEAN RetVal; |
| 97 | BOOLEAN SecondLoop; |
| 98 | MEM_NB_BLOCK *NBPtr; |
| 99 | MEM_PARAMETER_STRUCT *ParameterPtr; |
| 100 | MEM_SHARED_DATA *mmSharedPtr; |
| 101 | |
| 102 | NBPtr = MemMainPtr->NBPtr; |
| 103 | mmSharedPtr = MemMainPtr->mmSharedPtr; |
| 104 | ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; |
| 105 | mmSharedPtr->VoltageMap = 0xFF; |
| 106 | SecondLoop = FALSE; |
| 107 | RetVal = TRUE; |
| 108 | |
| 109 | for (Node = 0; Node < MemMainPtr->DieCount; Node++) { |
| 110 | NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]); |
| 111 | // Check if there is no common supported voltage |
| 112 | if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) { |
| 113 | // restart node loop by setting node to 0xFF |
| 114 | Node = 0xFF; |
| 115 | SecondLoop = TRUE; |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | if (mmSharedPtr->VoltageMap == 0) { |
| 120 | ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED; |
| 121 | } else { |
| 122 | ParameterPtr->DDR3Voltage = (DIMM_VOLTAGE) LibAmdBitScanReverse (mmSharedPtr->VoltageMap); |
| 123 | } |
| 124 | |
| 125 | for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { |
| 126 | RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); |
| 127 | } |
| 128 | |
| 129 | return RetVal; |
| 130 | } |
| 131 | |
| 132 | /* -----------------------------------------------------------------------------*/ |
| 133 | /** |
| 134 | * |
| 135 | * Find the common supported voltage on all nodes, taken into account of the |
| 136 | * user option for performance and power saving. |
| 137 | * |
| 138 | * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK |
| 139 | * |
| 140 | * @return TRUE - No fatal error occurs. |
| 141 | * @return FALSE - Fatal error occurs. |
| 142 | */ |
| 143 | BOOLEAN |
| 144 | MemMLvDdr3PerformanceEnhPre ( |
| 145 | IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr |
| 146 | ) |
| 147 | { |
| 148 | UINT8 Node; |
| 149 | BOOLEAN RetVal; |
| 150 | DIMM_VOLTAGE VDDIO; |
| 151 | MEM_NB_BLOCK *NBPtr; |
| 152 | MEM_PARAMETER_STRUCT *ParameterPtr; |
| 153 | MEM_SHARED_DATA *mmSharedPtr; |
| 154 | PLATFORM_POWER_POLICY PowerPolicy; |
| 155 | |
| 156 | NBPtr = MemMainPtr->NBPtr; |
| 157 | mmSharedPtr = MemMainPtr->mmSharedPtr; |
| 158 | ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; |
| 159 | PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy; |
| 160 | |
| 161 | IDS_OPTION_HOOK (IDS_SKIP_PERFORMANCE_OPT, &PowerPolicy, &NBPtr->MemPtr->StdHeader); |
| 162 | IDS_HDT_CONSOLE (MEM_STATUS, (PowerPolicy == Performance) ? "Maximize Performance\n" : "Maximize Battery Life\n"); |
| 163 | |
| 164 | RetVal = MemMLvDdr3 (MemMainPtr); |
| 165 | |
| 166 | VDDIO = ParameterPtr->DDR3Voltage; |
| 167 | ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED; |
| 168 | |
| 169 | if (mmSharedPtr->VoltageMap == 0) { |
| 170 | // When there is no commonly supported voltage, do not optimize performance |
| 171 | mmSharedPtr->VoltageMap = VDDIO_DETERMINED; |
| 172 | } else if (PowerPolicy == BatteryLife) { |
| 173 | ParameterPtr->DDR3Voltage = VDDIO; |
| 174 | } |
| 175 | |
| 176 | IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader); |
| 177 | |
| 178 | if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) { |
| 179 | // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance |
| 180 | mmSharedPtr->VoltageMap = VDDIO_DETERMINED; |
| 181 | IDS_HDT_CONSOLE (MEM_STATUS, "VDDIO is determined. No further optimization will be done.\n"); |
| 182 | } else { |
| 183 | for (Node = 0; Node < MemMainPtr->DieCount; Node++) { |
| 184 | NBPtr[Node].MaxFreqVDDIO[VOLT1_5] = UNSUPPORTED_DDR_FREQUENCY; |
| 185 | NBPtr[Node].MaxFreqVDDIO[VOLT1_35] = UNSUPPORTED_DDR_FREQUENCY; |
| 186 | NBPtr[Node].MaxFreqVDDIO[VOLT1_25] = UNSUPPORTED_DDR_FREQUENCY; |
| 187 | } |
| 188 | } |
| 189 | |
| 190 | // Reprogram the leveling result |
| 191 | ParameterPtr->DDR3Voltage = VDDIO; |
| 192 | |
| 193 | return RetVal; |
| 194 | } |
| 195 | |
| 196 | /* -----------------------------------------------------------------------------*/ |
| 197 | /** |
| 198 | * |
| 199 | * Finalize the VDDIO for the board for performance enhancement. |
| 200 | * |
| 201 | * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK |
| 202 | * |
| 203 | * @return TRUE - No fatal error occurs. |
| 204 | * @return FALSE - Fatal error occurs. |
| 205 | */ |
| 206 | BOOLEAN |
| 207 | MemMLvDdr3PerformanceEnhFinalize ( |
| 208 | IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr |
| 209 | ) |
| 210 | { |
| 211 | UINT8 Dct; |
| 212 | UINT8 Node; |
| 213 | UINT8 NodeCnt[VOLT1_25 + 1]; |
| 214 | UINT8 MaxCnt; |
| 215 | MEM_NB_BLOCK *NBPtr; |
| 216 | MEM_PARAMETER_STRUCT *ParameterPtr; |
| 217 | MEM_SHARED_DATA *mmSharedPtr; |
| 218 | DIMM_VOLTAGE CurrentVoltage; |
| 219 | DIMM_VOLTAGE Voltage; |
| 220 | MEMORY_BUS_SPEED HighestFreq; |
| 221 | |
| 222 | ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; |
| 223 | mmSharedPtr = MemMainPtr->mmSharedPtr; |
| 224 | NBPtr = MemMainPtr->NBPtr; |
| 225 | |
| 226 | LibAmdMemFill (NodeCnt, 0, VOLT1_25 + 1, &NBPtr->MemPtr->StdHeader); |
| 227 | if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) { |
| 228 | Voltage = ParameterPtr->DDR3Voltage; |
| 229 | for (Node = 0; Node < MemMainPtr->DieCount; Node++) { |
| 230 | HighestFreq = 0; |
| 231 | // Find out what the highest frequency that can be reached is on this node across different voltage. |
| 232 | for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) { |
| 233 | if (HighestFreq < NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]) { |
| 234 | HighestFreq = NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]; |
| 235 | } |
| 236 | } |
| 237 | // Figure out what voltage we can have when attaining the highest frequency. |
| 238 | for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) { |
| 239 | if (NBPtr[Node].MaxFreqVDDIO[CurrentVoltage] == HighestFreq) { |
| 240 | NodeCnt[CurrentVoltage] ++; |
| 241 | } |
| 242 | } |
| 243 | } |
| 244 | MaxCnt = 0; |
| 245 | // Use the VDDIO at which most nodes can run at higher frequency |
| 246 | for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) { |
| 247 | if (MaxCnt <= NodeCnt[CurrentVoltage]) { |
| 248 | MaxCnt = NodeCnt[CurrentVoltage]; |
| 249 | ParameterPtr->DDR3Voltage = CurrentVoltage; |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | mmSharedPtr->VoltageMap = VDDIO_DETERMINED; |
| 254 | if (Voltage != ParameterPtr->DDR3Voltage) { |
| 255 | // Finalize frequency with updated finalized VDDIO |
| 256 | for (Node = 0; Node < MemMainPtr->DieCount; Node++) { |
| 257 | // Need to re-sync target speed and different VDDIO may cause different settings |
| 258 | NBPtr[Node].TechPtr->SpdGetTargetSpeed (NBPtr[Node].TechPtr); |
| 259 | for (Dct = 0; Dct < NBPtr[Node].DctCount; Dct++) { |
| 260 | NBPtr[Node].SwitchDCT (&(NBPtr[Node]), Dct); |
| 261 | if (NBPtr[Node].DCTPtr->Timings.CsEnabled != 0) { |
| 262 | if (!NBPtr[Node].PlatformSpec (&(NBPtr[Node]))) { |
| 263 | return FALSE; |
| 264 | } |
| 265 | } |
| 266 | } |
| 267 | } |
| 268 | } |
| 269 | } |
| 270 | return TRUE; |
| 271 | } |