Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /* |
| 3 | * @file |
| 4 | * |
| 5 | * mauon3.c |
| 6 | * |
| 7 | * Platform specific settings for ON DDR3 unbuffered dimms |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Ardk/ON) |
| 12 | * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ |
| 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /* This file contains routine that add platform specific support AM3 */ |
| 48 | |
| 49 | |
| 50 | #include "AGESA.h" |
| 51 | #include "PlatformMemoryConfiguration.h" |
| 52 | #include "mport.h" |
| 53 | #include "ma.h" |
| 54 | #include "Ids.h" |
| 55 | #include "cpuFamRegisters.h" |
| 56 | #include "Filecode.h" |
| 57 | #define FILECODE PROC_MEM_ARDK_ON_MAUON3_FILECODE |
| 58 | /*---------------------------------------------------------------------------- |
| 59 | * DEFINITIONS AND MACROS |
| 60 | * |
| 61 | *---------------------------------------------------------------------------- |
| 62 | */ |
| 63 | |
| 64 | /*---------------------------------------------------------------------------- |
| 65 | * TYPEDEFS AND STRUCTURES |
| 66 | * |
| 67 | *---------------------------------------------------------------------------- |
| 68 | */ |
| 69 | |
| 70 | /*---------------------------------------------------------------------------- |
| 71 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 72 | * |
| 73 | *---------------------------------------------------------------------------- |
| 74 | */ |
| 75 | |
| 76 | /* |
| 77 | *----------------------------------------------------------------------------- |
| 78 | * EXPORTED FUNCTIONS |
| 79 | * |
| 80 | *----------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | STATIC CONST UINT8 ROMDATA OnUDdr3CLKDis[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; |
| 84 | STATIC CONST UINT8 ROMDATA OnUDdr3CKETri[] = {0xFF, 0xFF}; |
| 85 | STATIC CONST UINT8 ROMDATA OnUDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08}; |
| 86 | STATIC CONST UINT8 ROMDATA OnUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; |
| 87 | |
| 88 | /* -----------------------------------------------------------------------------*/ |
| 89 | /** |
| 90 | * |
| 91 | * This is function sets the platform specific settings for ON DDR3 Unbuffered dimms |
| 92 | * |
| 93 | * |
| 94 | * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE |
| 95 | * @param[in] SocketID Socket number |
| 96 | * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT |
| 97 | * |
| 98 | * @return AGESA_SUCCESS |
| 99 | * @return CurrentChannel->MemClkDisMap Points this pointer to LN MemClkDis table |
| 100 | * @return CurrentChannel->ChipSelTriMap Points this pointer to LN CS table |
| 101 | * @return CurrentChannel->CKETriMap Points this pointer to LN ODT table |
| 102 | * @return CurrentChannel->ODTTriMap Points this pointer to LN CKE table |
| 103 | * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC |
| 104 | * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte |
| 105 | * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel |
| 106 | * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel |
| 107 | * @return CurrentChannel->SlowMode Slow Mode |
| 108 | * |
| 109 | */ |
| 110 | |
| 111 | AGESA_STATUS |
| 112 | MemAGetPsCfgUON3 ( |
| 113 | IN OUT MEM_DATA_STRUCT *MemData, |
| 114 | IN UINT8 SocketID, |
| 115 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 116 | ) |
| 117 | { |
| 118 | CONST ADV_PSCFG_ENTRY PSCfg[] = { |
| 119 | {DDR800_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x00112223, 1}, |
| 120 | {DDR800_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x003B0000, 0x00112223, 1}, |
| 121 | {DDR800_FREQUENCY, ANY_, 0x00390039, 0x20222323, 2}, |
| 122 | {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x10112223, 1}, |
| 123 | {DDR1066_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00380000, 0x10112223, 1}, |
| 124 | {DDR1066_FREQUENCY, ANY_, 0x00350037, 0x30222323, 2}, |
| 125 | {DDR1333_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x30112223, 1}, |
| 126 | {DDR1333_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00360000, 0x30112223, 1}, |
| 127 | {DDR1333_FREQUENCY, ANY_, 0x00000035, 0x30222323, 2} |
| 128 | }; |
| 129 | |
| 130 | // |
| 131 | // DIMM ODT Pattern |
| 132 | // |
| 133 | // Dimm Config , |
| 134 | // Fn2_F4 180, Fn2_F4 181, Fn2_F4 182, Fn2_F4 183, # Dimms to match |
| 135 | // |
| 136 | STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfgDIMMsODT[] = { |
| 137 | {SR_DIMM0, \ |
| 138 | 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, |
| 139 | {DR_DIMM0, \ |
| 140 | 0x00000000, 0x00000000, 0x00000201, 0x00000000, 1}, |
| 141 | {SR_DIMM1, \ |
| 142 | 0x00000000, 0x00000000, 0x00040000, 0x00000000, 1}, |
| 143 | {DR_DIMM1, \ |
| 144 | 0x00000000, 0x00000000, 0x08040000, 0x00000000, 1}, |
| 145 | {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ |
| 146 | 0x01010404, 0x00000000, 0x09050605, 0x00000000, 2} |
| 147 | }; |
| 148 | |
| 149 | UINT16 i; |
| 150 | UINT16 j; |
| 151 | UINT8 Dimms; |
| 152 | UINT16 Speed; |
| 153 | UINT16 DIMMRankType; |
| 154 | UINT16 _DIMMRankType; |
| 155 | UINT32 AddrTmgCTL; |
| 156 | UINT32 DctOdcCtl; |
| 157 | UINT8 PhyWLODT[4]; |
| 158 | UINT32 PhyRODTCS; |
| 159 | UINT32 PhyWODTCS; |
| 160 | BOOLEAN SlowMode; |
| 161 | UINT8 DimmTpMatch; |
| 162 | |
| 163 | ASSERT (MemData != 0); |
| 164 | ASSERT (CurrentChannel != 0); |
| 165 | |
| 166 | AddrTmgCTL = 0; |
| 167 | DctOdcCtl = 0; |
| 168 | PhyWLODT[0] = 0x0F; |
| 169 | PhyWLODT[1] = 0x0F; |
| 170 | PhyWLODT[2] = 0x0F; |
| 171 | PhyWLODT[3] = 0x0F; |
| 172 | PhyRODTCS = 0; |
| 173 | PhyWODTCS = 0; |
| 174 | |
| 175 | if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_ON) == 0) { |
| 176 | return AGESA_UNSUPPORTED; |
| 177 | } |
| 178 | if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { |
| 179 | return AGESA_UNSUPPORTED; |
| 180 | } |
| 181 | if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) { |
| 182 | return AGESA_UNSUPPORTED; |
| 183 | } |
| 184 | |
| 185 | // Prepare inputs |
| 186 | Dimms = CurrentChannel->Dimms; |
| 187 | Speed = CurrentChannel->DCTPtr->Timings.Speed; |
| 188 | |
| 189 | DIMMRankType = MemAGetPsRankType (CurrentChannel); |
| 190 | |
| 191 | if ((Speed == DDR1333_FREQUENCY) && (Dimms == 2)) { |
| 192 | SlowMode = TRUE; // 2T |
| 193 | } else { |
| 194 | SlowMode = FALSE; // 1T |
| 195 | } |
| 196 | |
| 197 | for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { |
| 198 | if ((PSCfg[i].Dimms == ANY_) || (PSCfg[i].Dimms == Dimms)) { |
| 199 | if ((PSCfg[i].Speed == ANY_) || (PSCfg[i].Speed == Speed)) { |
| 200 | if ((PSCfg[i].Loads == ANY_) || ((PSCfg[i].Loads & DIMMRankType) != 0)) { |
| 201 | AddrTmgCTL = PSCfg[i].AddrTmg; |
| 202 | DctOdcCtl = PSCfg[i].Odc; |
| 203 | break; |
| 204 | } |
| 205 | } |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | ASSERT (i < GET_SIZE_OF (PSCfg)); |
| 210 | |
| 211 | // |
| 212 | // Programmable Dimm ODT |
| 213 | // |
| 214 | for (i = 0; i < GET_SIZE_OF (PSCfgDIMMsODT); i++) { |
| 215 | if (Dimms != PSCfgDIMMsODT[i].Dimms) { |
| 216 | continue; |
| 217 | } |
| 218 | DimmTpMatch = 0; |
| 219 | _DIMMRankType = DIMMRankType & PSCfgDIMMsODT[i].DIMMRankType; |
| 220 | for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { |
| 221 | if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { |
| 222 | DimmTpMatch++; |
| 223 | } |
| 224 | } |
| 225 | if (DimmTpMatch == PSCfgDIMMsODT[i].Dimms) { |
| 226 | PhyRODTCS = PSCfgDIMMsODT[i].PhyRODTCSLow; |
| 227 | PhyWODTCS = PSCfgDIMMsODT[i].PhyWODTCSLow; |
| 228 | break; |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | // |
| 233 | //WL ODT |
| 234 | // |
| 235 | PhyWLODT[0] = (UINT8) (PhyWODTCS & 0x0F); |
| 236 | PhyWLODT[1] = (UINT8) ((PhyWODTCS >> 16) & 0x0F); |
| 237 | PhyWLODT[2] = PhyWLODT[3] = 0; |
| 238 | |
| 239 | // |
| 240 | // Overrides and/or exceptions |
| 241 | // |
| 242 | CurrentChannel->MemClkDisMap = (UINT8 *) OnUDdr3CLKDis; |
| 243 | CurrentChannel->CKETriMap = (UINT8 *) OnUDdr3CKETri; |
| 244 | CurrentChannel->ODTTriMap = (UINT8 *) OnUDdr3ODTTri; |
| 245 | CurrentChannel->ChipSelTriMap = (UINT8 *) OnUDdr3CSTri; |
| 246 | |
| 247 | CurrentChannel->DctEccDqsLike = 0x0403; |
| 248 | CurrentChannel->DctEccDqsScale = 0x70; |
| 249 | CurrentChannel->DctAddrTmg = AddrTmgCTL; |
| 250 | CurrentChannel->DctOdcCtl = DctOdcCtl; |
| 251 | CurrentChannel->PhyRODTCSLow = PhyRODTCS; |
| 252 | CurrentChannel->PhyWODTCSLow = PhyWODTCS; |
| 253 | for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { |
| 254 | CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; |
| 255 | } |
| 256 | CurrentChannel->SlowMode = SlowMode; |
| 257 | |
| 258 | return AGESA_SUCCESS; |
| 259 | } |