Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD IDS Routines |
| 6 | * |
| 7 | * Contains AMD AGESA Integrated Debug Macros |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: IDS |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12 | * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | */ |
| 14 | /* |
| 15 | ***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 19 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 29 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 30 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 41 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | #ifndef _IDS_LIB_H_ |
| 47 | #define _IDS_LIB_H_ |
| 48 | #include "OptionsIds.h" |
| 49 | #include "cpuRegisters.h" |
| 50 | #include "cpuApicUtilities.h" |
| 51 | #include "Table.h" |
| 52 | ///Specific time stamp performance analysis which need ids control support |
| 53 | #if IDSOPT_CONTROL_ENABLED == TRUE |
| 54 | #define PERF_SPEC_TS_ANALYSE(StdHeader) |
| 55 | #else |
| 56 | #define PERF_SPEC_TS_ANALYSE(StdHeader) |
| 57 | #endif |
| 58 | |
| 59 | |
| 60 | #define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader) |
| 61 | #define IDS_GET_MASK32(HighBit, LowBit) |
| 62 | |
| 63 | #define IDS_MAX_MEM_ITEMS 80 ///< Maximum IDS Mem Table Size in Heap. |
| 64 | |
| 65 | |
| 66 | // TYPEDEFS, STRUCTURES, ENUMS |
| 67 | // |
| 68 | |
| 69 | |
| 70 | ///Structure define for MSR register |
| 71 | typedef struct _REG_MSR { |
| 72 | UINT32 msraddr; ///< Address of MSR Register |
| 73 | UINT32 andmaskhi; ///< And Mask Bit63:32 |
| 74 | UINT32 andmasklo; ///< And Mask Bit31:0 |
| 75 | UINT32 ormaskhi; ///< Or Mask Bit63:32 |
| 76 | UINT32 ormasklo; ///< Or Mask Bit31:0 |
| 77 | } REG_MSR; |
| 78 | |
| 79 | typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader); |
| 80 | |
| 81 | ///Structure define for IdsAgesaRunFcnOnApLate |
| 82 | typedef struct _IDSAPLATETASK { |
| 83 | PF_IDS_AP_TASK ApTask; ///< Point function which AP need to do |
| 84 | VOID *ApTaskPara; ///< Point to Ap function parameter1 |
| 85 | } IDSAPLATETASK; |
| 86 | |
| 87 | /// Data Structure defining IDS Data in HEAP |
| 88 | /// This data structure contains information that is stored in HEAP and will be |
| 89 | /// used in IDS backend function. It includes the size of memory to be allocated |
| 90 | /// for IDS, the relative offsets of the mapping table IDS setup options, the GRA |
| 91 | /// table and the register table to override mem setting. It also includes a base |
| 92 | /// address of IDS override image which will be used to control the behavior of |
| 93 | /// AGESA testpoint if this feature is enabled. |
| 94 | typedef struct { |
| 95 | BOOLEAN IgnoreIdsDefault; ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset |
| 96 | UINT64 IdsImageBase; ///< IDS Override Image Base Address |
| 97 | UINT32 IdsHeapMemSize; ///< IDS Total Memory Size in Heap |
| 98 | UINT32 IdsNvTableOffset; ///< Offset of IDS NV Table |
| 99 | UINT32 IdsMemTableOffset; ///< Offset of IDS Mem Table |
| 100 | UINT32 IdsExtendOffset; ///< Offset of Ids extend heap |
| 101 | } IDS_CONTROL_STRUCT; |
| 102 | |
| 103 | |
| 104 | /// Data Structure of Parameters for TestPoint_TSC. |
| 105 | typedef struct { |
| 106 | UINT8 TestPoint; ///< The TestPoint of TestPoint_TSC |
| 107 | UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC |
| 108 | } TestPoint_TSC; |
| 109 | |
| 110 | /// Data Structure of Parameters for TP_Perf_STRUCT. |
| 111 | typedef struct { |
| 112 | UINT8 Index; ///< The Index of TP_Perf_STRUCT |
| 113 | UINT32 TscInMhz; ///< Tsc counter in 1 mhz |
| 114 | TestPoint_TSC TP[EndAgesaTps]; ///< The TP of TP_Perf_STRUCT |
| 115 | } TP_Perf_STRUCT; |
| 116 | |
| 117 | |
| 118 | ///Bus speed Optimization |
| 119 | typedef enum { |
| 120 | IDS_POWER_POLICY_PERFORMANCE = 0, ///< Performance |
| 121 | IDS_POWER_POLICY_POWER = 1, ///< Power |
| 122 | IDS_POWER_POLICY_AUTO = 3, ///< Auto |
| 123 | } IDS_NV_AMDBUSSPEEDOPTIMIZATION; |
| 124 | |
| 125 | #define IDS_CPB_BOOST_DIS_IGNORE 0xFFFFFFFF |
| 126 | |
| 127 | #endif //_IDS_LIB_H_ |
| 128 | |