Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe port initialization service procedure |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | #include "AGESA.h" |
| 52 | #include "Ids.h" |
| 53 | #include "Gnb.h" |
| 54 | #include "GnbPcie.h" |
| 55 | #include "PcieFamilyServices.h" |
| 56 | #include "PcieMiscLib.h" |
| 57 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 58 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 59 | #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) |
| 60 | #include "GnbRegistersON.h" |
| 61 | #include "Filecode.h" |
| 62 | #define FILECODE PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE |
| 63 | /*---------------------------------------------------------------------------------------- |
| 64 | * D E F I N I T I O N S A N D M A C R O S |
| 65 | *---------------------------------------------------------------------------------------- |
| 66 | */ |
| 67 | |
| 68 | |
| 69 | /*---------------------------------------------------------------------------------------- |
| 70 | * T Y P E D E F S A N D S T R U C T U R E S |
| 71 | *---------------------------------------------------------------------------------------- |
| 72 | */ |
| 73 | |
| 74 | |
| 75 | /*---------------------------------------------------------------------------------------- |
| 76 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 77 | *---------------------------------------------------------------------------------------- |
| 78 | */ |
| 79 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 80 | VOID |
| 81 | PcieSlotPowerLimit ( |
| 82 | IN PCIe_ENGINE_CONFIG *Engine, |
| 83 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 84 | ); |
| 85 | |
| 86 | AGESA_STATUS |
| 87 | PciePortLateInit ( |
| 88 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 89 | ); |
| 90 | |
| 91 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 92 | PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = { |
| 93 | { |
| 94 | DxF0xE4_xA2_ADDRESS, |
| 95 | DxF0xE4_xA2_LcDynLanesPwrState_MASK, |
| 96 | (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET) |
| 97 | }, |
| 98 | { |
| 99 | DxF0xE4_xC0_ADDRESS, |
| 100 | DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, |
| 101 | (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) |
| 102 | } |
| 103 | }; |
| 104 | |
| 105 | /*----------------------------------------------------------------------------------------*/ |
| 106 | /** |
| 107 | * Enable ASPM |
| 108 | * |
| 109 | * |
| 110 | * |
| 111 | * @param[in] Engine Pointer to engine config descriptor |
| 112 | * @param[in] Pcie Pointer to global PCIe configuration |
| 113 | * |
| 114 | */ |
| 115 | |
| 116 | VOID |
| 117 | STATIC |
| 118 | PcieEnableAspm ( |
| 119 | IN PCIe_ENGINE_CONFIG *Engine, |
| 120 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 121 | ) |
| 122 | { |
| 123 | if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) { |
| 124 | if (Engine->Type.Port.IsSB != 0) { |
| 125 | PcieSbLinkAspmControl (Engine, Pcie); |
| 126 | } else { |
| 127 | PcieLinkAspmEnable ( |
| 128 | Engine->Type.Port.Address, |
| 129 | Engine->Type.Port.PortData.LinkAspm, |
| 130 | GnbLibGetHeader (Pcie) |
| 131 | ); |
| 132 | } |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | /*----------------------------------------------------------------------------------------*/ |
| 137 | /** |
| 138 | * Set slot power limit |
| 139 | * |
| 140 | * |
| 141 | * |
| 142 | * @param[in] Engine Pointer to engine config descriptor |
| 143 | * @param[in] Pcie Pointer to global PCIe configuration |
| 144 | * |
| 145 | */ |
| 146 | |
| 147 | VOID |
| 148 | PcieSlotPowerLimit ( |
| 149 | IN PCIe_ENGINE_CONFIG *Engine, |
| 150 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 151 | ) |
| 152 | { |
| 153 | DxF0x6C_STRUCT DxF0x6C; |
| 154 | GnbLibPciRead ( |
| 155 | Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, |
| 156 | AccessWidth32, |
| 157 | &DxF0x6C.Value, |
| 158 | GnbLibGetHeader (Pcie) |
| 159 | ); |
| 160 | |
| 161 | DxF0x6C.Field.SlotPwrLimitValue = 75; |
| 162 | DxF0x6C.Field.PhysicalSlotNumber = Engine->Type.Port.Address.Address.Device; |
| 163 | |
| 164 | GnbLibPciWrite ( |
| 165 | Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, |
| 166 | AccessS3SaveWidth32, |
| 167 | &DxF0x6C.Value, |
| 168 | GnbLibGetHeader (Pcie) |
| 169 | ); |
| 170 | PcieFmEnableSlotPowerLimit (Engine, Pcie); |
| 171 | } |
| 172 | |
| 173 | |
| 174 | /*----------------------------------------------------------------------------------------*/ |
| 175 | /** |
| 176 | * Callback to init various features on all active ports |
| 177 | * |
| 178 | * |
| 179 | * |
| 180 | * |
| 181 | * @param[in] Engine Pointer to engine config descriptor |
| 182 | * @param[in, out] Buffer Not used |
| 183 | * @param[in] Pcie Pointer to global PCIe configuration |
| 184 | * |
| 185 | */ |
| 186 | |
| 187 | VOID |
| 188 | STATIC |
| 189 | PciePortLateInitCallback ( |
| 190 | IN PCIe_ENGINE_CONFIG *Engine, |
| 191 | IN OUT VOID *Buffer, |
| 192 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 193 | ) |
| 194 | { |
| 195 | PciePortProgramRegisterTable (PortLateInitTable, (sizeof (PortLateInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, TRUE, Pcie); |
| 196 | if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { |
| 197 | PcieSlotPowerLimit (Engine, Pcie); |
| 198 | } |
| 199 | PcieEnableAspm (Engine, Pcie); |
| 200 | if (Engine->Type.Port.IsSB != 0) { |
| 201 | PcieSbLinkVcEnable (Engine, Pcie); |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | /*----------------------------------------------------------------------------------------*/ |
| 206 | /** |
| 207 | * Master procedure to init various features on all active ports |
| 208 | * |
| 209 | * |
| 210 | * |
| 211 | * |
| 212 | * @param[in] Pcie Pointer to global PCIe configuration |
| 213 | * @retval AGESA_STATUS |
| 214 | * |
| 215 | */ |
| 216 | |
| 217 | AGESA_STATUS |
| 218 | PciePortLateInit ( |
| 219 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 220 | ) |
| 221 | { |
| 222 | AGESA_STATUS Status; |
| 223 | PCIE_LINK_SPEED_CAP GlobalSpeedCap; |
| 224 | |
| 225 | Status = AGESA_SUCCESS; |
| 226 | PcieConfigRunProcForAllEngines ( |
| 227 | DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, |
| 228 | PciePortLateInitCallback, |
| 229 | NULL, |
| 230 | Pcie |
| 231 | ); |
| 232 | |
| 233 | GlobalSpeedCap = PcieUtilGlobalGenCapability ( |
| 234 | PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, |
| 235 | Pcie |
| 236 | ); |
| 237 | |
| 238 | PcieFmSetBootUpVoltage (GlobalSpeedCap, Pcie); |
| 239 | |
| 240 | return Status; |
| 241 | } |