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review.coreboot.org / coreboot / dbdf170dcdf9edbc860766606e53c6d647d89d38 / . / src / vendorcode / amd / agesa / f14 / Proc / GNB / PCIe / PcieInitAtLatePost.c
blob: 19504a2d901a23e1377860fe97b5fe04ae2f7c2d [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * PCIe late post initialization.
6 *
7 *
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: GNB
12 * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
13 *
14 */
15/*
16 *****************************************************************************
17 *
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]20 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]30 * from this software without specific prior written permission.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]31 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]42 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]43 * ***************************************************************************
44 *
45 */
46/*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
49 */
50#include "AGESA.h"
51#include "Ids.h"
52#include "Gnb.h"
53#include "GnbPcie.h"
54#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
55#include "PcieInit.h"
56#include "PcieLateInit.h"
57#include "PciePortLateInit.h"
58#include "PcieInitAtLatePost.h"
59#include "Filecode.h"
60#define FILECODE PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE
61/*----------------------------------------------------------------------------------------
62 * D E F I N I T I O N S A N D M A C R O S
63 *----------------------------------------------------------------------------------------
64 */
65
66
67/*----------------------------------------------------------------------------------------
68 * T Y P E D E F S A N D S T R U C T U R E S
69 *----------------------------------------------------------------------------------------
70 */
71
72
73/*----------------------------------------------------------------------------------------
74 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
75 *----------------------------------------------------------------------------------------
76 */
77
78/*----------------------------------------------------------------------------------------*/
79/**
80 * PCIe Mid Init
81 *
82 *
83 *
84 * @param[in] StdHeader Standard configuration header
85 * @retval AGESA_STATUS
86 */
87AGESA_STATUS
88PcieInitAtMid (
89 IN AMD_CONFIG_PARAMS *StdHeader
90 )
91{
92 AGESA_STATUS AgesaStatus;
93 AGESA_STATUS Status;
94 PCIe_PLATFORM_CONFIG *Pcie;
95 IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Enter\n");
96 AgesaStatus = AGESA_SUCCESS;
97 Status = PcieLocateConfigurationData (StdHeader, &Pcie);
98 AGESA_STATUS_UPDATE (Status, AgesaStatus);
99 if (Status == AGESA_SUCCESS) {
100 PciePortsVisibilityControl (UnhidePorts, Pcie);
101
102 Status = PciePortLateInit (Pcie);
103 AGESA_STATUS_UPDATE (Status, AgesaStatus);
104 ASSERT (Status == AGESA_SUCCESS);
105
106 Status = PcieLateInit (Pcie);
107 AGESA_STATUS_UPDATE (Status, AgesaStatus);
108 ASSERT (Status == AGESA_SUCCESS);
109
110 PciePortsVisibilityControl (HidePorts, Pcie);
111 }
112 IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Exit [0x%x]\n", AgesaStatus);
113 return AgesaStatus;
114}