Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Family specific PCIe wrapper configuration services |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12 | * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | #include "AGESA.h" |
| 52 | #include "Ids.h" |
| 53 | #include "Gnb.h" |
| 54 | #include "GnbPcie.h" |
| 55 | #include "PcieFamilyServices.h" |
| 56 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 57 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 58 | #include "PcieMiscLib.h" |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 59 | #include "GnbPcieFamServices.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 60 | #include "OntarioDefinitions.h" |
| 61 | #include "GnbRegistersON.h" |
| 62 | #include "NbSmuLib.h" |
| 63 | #include "Filecode.h" |
| 64 | #define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE |
| 65 | /*---------------------------------------------------------------------------------------- |
| 66 | * D E F I N I T I O N S A N D M A C R O S |
| 67 | *---------------------------------------------------------------------------------------- |
| 68 | */ |
| 69 | extern BUILD_OPT_CFG UserOptions; |
| 70 | |
| 71 | /*---------------------------------------------------------------------------------------- |
| 72 | * T Y P E D E F S A N D S T R U C T U R E S |
| 73 | *---------------------------------------------------------------------------------------- |
| 74 | */ |
| 75 | |
| 76 | |
| 77 | /*---------------------------------------------------------------------------------------- |
| 78 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 79 | *---------------------------------------------------------------------------------------- |
| 80 | */ |
| 81 | |
| 82 | AGESA_STATUS |
| 83 | STATIC |
| 84 | PcieOnConfigureGppEnginesLaneAllocation ( |
| 85 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 86 | IN UINT8 ConfigurationId |
| 87 | ); |
| 88 | |
| 89 | AGESA_STATUS |
| 90 | STATIC |
| 91 | PcieOnConfigureDdiEnginesLaneAllocation ( |
| 92 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 93 | IN UINT8 ConfigurationId |
| 94 | ); |
| 95 | |
| 96 | VOID |
| 97 | PcieFmExecuteNativeGen1Reconfig ( |
| 98 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 99 | ); |
| 100 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 101 | AGESA_STATUS |
| 102 | PcieOnGetGppConfigurationValue ( |
| 103 | IN UINT64 ConfigurationSignature, |
| 104 | OUT UINT8 *ConfigurationValue |
| 105 | ); |
| 106 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 107 | /*---------------------------------------------------------------------------------------- |
| 108 | * T A B L E S |
| 109 | *---------------------------------------------------------------------------------------- |
| 110 | */ |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame] | 111 | CONST PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 112 | { |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 113 | PHY_SPACE (0, 0, D0F0xE4_PHY_6440_ADDRESS), |
| 114 | D0F0xE4_PHY_6440_RxInCalForce_MASK, |
| 115 | 0x1 << D0F0xE4_PHY_6440_RxInCalForce_OFFSET |
| 116 | }, |
| 117 | { |
| 118 | PHY_SPACE (0, 0, D0F0xE4_PHY_6480_ADDRESS), |
| 119 | D0F0xE4_PHY_6480_RxInCalForce_MASK, |
| 120 | 0x1 << D0F0xE4_PHY_6480_RxInCalForce_OFFSET |
| 121 | }, |
| 122 | { |
| 123 | PHY_SPACE (0, 0, D0F0xE4_PHY_6500_ADDRESS), |
| 124 | D0F0xE4_PHY_6500_RxInCalForce_MASK, |
| 125 | 0x1 << D0F0xE4_PHY_6500_RxInCalForce_OFFSET |
| 126 | }, |
| 127 | { |
| 128 | PHY_SPACE (0, 0, D0F0xE4_PHY_6600_ADDRESS), |
| 129 | D0F0xE4_PHY_6600_RxInCalForce_MASK, |
| 130 | 0x1 << D0F0xE4_PHY_6600_RxInCalForce_OFFSET |
| 131 | }, |
| 132 | { |
| 133 | PHY_SPACE (0, 0, D0F0xE4_PHY_6840_ADDRESS), |
| 134 | D0F0xE4_PHY_6840_RxInCalForce_MASK, |
| 135 | 0x1 << D0F0xE4_PHY_6840_RxInCalForce_OFFSET |
| 136 | }, |
| 137 | { |
| 138 | PHY_SPACE (0, 0, D0F0xE4_PHY_6880_ADDRESS), |
| 139 | D0F0xE4_PHY_6880_RxInCalForce_MASK, |
| 140 | 0x1 << D0F0xE4_PHY_6880_RxInCalForce_OFFSET |
| 141 | }, |
| 142 | { |
| 143 | PHY_SPACE (0, 0, D0F0xE4_PHY_6900_ADDRESS), |
| 144 | D0F0xE4_PHY_6900_RxInCalForce_MASK, |
| 145 | 0x1 << D0F0xE4_PHY_6900_RxInCalForce_OFFSET |
| 146 | }, |
| 147 | { |
| 148 | PHY_SPACE (0, 0, D0F0xE4_PHY_6A00_ADDRESS), |
| 149 | D0F0xE4_PHY_6A00_RxInCalForce_MASK, |
| 150 | 0x1 << D0F0xE4_PHY_6A00_RxInCalForce_OFFSET |
| 151 | }, |
| 152 | { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 153 | WRAP_SPACE (0, D0F0xE4_WRAP_8016_ADDRESS), |
| 154 | D0F0xE4_WRAP_8016_CalibAckLatency_MASK, |
| 155 | 0 |
| 156 | }, |
| 157 | { |
| 158 | PHY_SPACE (0, 0, D0F0xE4_PHY_4004_ADDRESS), |
| 159 | D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_MASK | D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_MASK, |
| 160 | (0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_OFFSET) | (0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_OFFSET) |
| 161 | }, |
| 162 | { |
| 163 | D0F0xE4_x0108_8071_ADDRESS, |
| 164 | D0F0xE4_x0108_8071_RxAdjust_MASK, |
| 165 | 0x3 << D0F0xE4_x0108_8071_RxAdjust_OFFSET |
| 166 | }, |
| 167 | { |
| 168 | D0F0xE4_x0108_8072_ADDRESS, |
| 169 | D0F0xE4_x0108_8072_TxAdjust_MASK, |
| 170 | 0x3 << D0F0xE4_x0108_8072_TxAdjust_OFFSET |
| 171 | }, |
| 172 | }; |
| 173 | |
| 174 | /*----------------------------------------------------------------------------------------*/ |
| 175 | /** |
| 176 | * Configure engine list to support lane allocation according to configuration ID. |
| 177 | * |
| 178 | * |
| 179 | * |
| 180 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 181 | * @param[in] EngineType Engine Type |
| 182 | * @param[in] ConfigurationId Configuration ID |
| 183 | * @retval AGESA_SUCCESS Configuration successfully applied |
| 184 | * @retval AGESA_UNSUPPORTED No more configuration available for given engine type |
| 185 | * @retval AGESA_ERROR Requested configuration not supported |
| 186 | */ |
| 187 | AGESA_STATUS |
| 188 | PcieFmConfigureEnginesLaneAllocation ( |
| 189 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 190 | IN PCIE_ENGINE_TYPE EngineType, |
| 191 | IN UINT8 ConfigurationId |
| 192 | ) |
| 193 | { |
| 194 | AGESA_STATUS Status; |
| 195 | Status = AGESA_ERROR; |
| 196 | switch (Wrapper->WrapId) { |
| 197 | case GPP_WRAP_ID: |
| 198 | if (EngineType != PciePortEngine) { |
| 199 | return AGESA_UNSUPPORTED; |
| 200 | } |
| 201 | Status = PcieOnConfigureGppEnginesLaneAllocation (Wrapper, ConfigurationId); |
| 202 | break; |
| 203 | case DDI_WRAP_ID: |
| 204 | if (EngineType != PcieDdiEngine) { |
| 205 | return AGESA_UNSUPPORTED; |
| 206 | } |
| 207 | Status = PcieOnConfigureDdiEnginesLaneAllocation (Wrapper, ConfigurationId); |
| 208 | break; |
| 209 | default: |
| 210 | ASSERT (FALSE); |
| 211 | |
| 212 | } |
| 213 | return Status; |
| 214 | } |
| 215 | |
| 216 | CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { |
| 217 | //4 5 6 7 8 (SB) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 218 | {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, |
| 219 | {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, |
| 220 | {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, |
| 221 | {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, |
| 222 | {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3}, |
| 223 | {4, 4, 5, 5, 6, 6, 7, 7, 0, 3} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 224 | }; |
| 225 | |
| 226 | CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = { |
| 227 | //4 5 6 7 8 (SB) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 228 | {1, 2, 3, 4, 0}, |
| 229 | {1, 2, 3, 4, 0}, |
| 230 | {1, 3, 2, 4, 0}, |
| 231 | {1, 2, 3, 4, 0}, |
| 232 | {1, 4, 2, 3, 0}, |
| 233 | {1, 2, 3, 4, 0} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 234 | }; |
| 235 | |
| 236 | /*----------------------------------------------------------------------------------------*/ |
| 237 | /** |
| 238 | * Configure GFX engine list to support lane allocation according to configuration ID. |
| 239 | * |
| 240 | * |
| 241 | * |
| 242 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 243 | * @param[in] ConfigurationId Configuration ID |
| 244 | * @retval AGESA_SUCCESS Configuration successfully applied |
| 245 | * @retval AGESA_ERROR Requested configuration not supported |
| 246 | */ |
| 247 | |
| 248 | |
| 249 | AGESA_STATUS |
| 250 | STATIC |
| 251 | PcieOnConfigureGppEnginesLaneAllocation ( |
| 252 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 253 | IN UINT8 ConfigurationId |
| 254 | ) |
| 255 | { |
| 256 | PCIe_ENGINE_CONFIG *EnginesList; |
| 257 | UINTN CoreLaneIndex; |
| 258 | UINTN PortIdIndex; |
| 259 | if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) { |
| 260 | return AGESA_ERROR; |
| 261 | } |
| 262 | EnginesList = PcieWrapperGetEngineList (Wrapper); |
| 263 | CoreLaneIndex = 0; |
| 264 | PortIdIndex = 0; |
| 265 | do { |
efdesign98 | 4d2d5d5 | 2011-09-14 19:34:13 -0600 | [diff] [blame] | 266 | if (PortIdIndex > 0) EnginesList++; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 267 | EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED; |
| 268 | EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++]; |
| 269 | EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; |
| 270 | EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; |
| 271 | |
efdesign98 | 4d2d5d5 | 2011-09-14 19:34:13 -0600 | [diff] [blame] | 272 | } while (IS_LAST_DESCRIPTOR (EnginesList)); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 273 | return AGESA_SUCCESS; |
| 274 | } |
| 275 | |
| 276 | |
| 277 | CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 278 | {0, 3, 4, 7, 8, 11} |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 279 | }; |
| 280 | |
| 281 | /*----------------------------------------------------------------------------------------*/ |
| 282 | /** |
| 283 | * Configure DDI engine list to support lane allocation according to configuration ID. |
| 284 | * |
| 285 | * |
| 286 | * |
| 287 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 288 | * @param[in] ConfigurationId Configuration ID |
| 289 | * @retval AGESA_SUCCESS Configuration successfully applied |
| 290 | * @retval AGESA_ERROR Requested configuration not supported |
| 291 | */ |
| 292 | |
| 293 | |
| 294 | AGESA_STATUS |
| 295 | STATIC |
| 296 | PcieOnConfigureDdiEnginesLaneAllocation ( |
| 297 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 298 | IN UINT8 ConfigurationId |
| 299 | ) |
| 300 | { |
| 301 | PCIe_ENGINE_CONFIG *EnginesList; |
| 302 | UINTN LaneIndex; |
| 303 | EnginesList = PcieWrapperGetEngineList (Wrapper); |
| 304 | if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) { |
| 305 | return AGESA_ERROR; |
| 306 | } |
| 307 | LaneIndex = 0; |
| 308 | do { |
efdesign98 | 4d2d5d5 | 2011-09-14 19:34:13 -0600 | [diff] [blame] | 309 | if (LaneIndex > 0) EnginesList++; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 310 | EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED; |
| 311 | EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + |
| 312 | Wrapper->StartPhyLane; |
| 313 | EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + |
| 314 | Wrapper->StartPhyLane; |
efdesign98 | 4d2d5d5 | 2011-09-14 19:34:13 -0600 | [diff] [blame] | 315 | } while (IS_LAST_DESCRIPTOR (EnginesList)); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 316 | return AGESA_SUCCESS; |
| 317 | } |
| 318 | |
| 319 | /*----------------------------------------------------------------------------------------*/ |
| 320 | /** |
| 321 | * Configure clock to run out of the wrapper at specific speed |
| 322 | * |
| 323 | * |
| 324 | * @param[in] LinkSpeedCapability Link Speed capability |
| 325 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 326 | * @param[in] Pcie Pointer to global PCIe configuration |
| 327 | */ |
| 328 | VOID |
| 329 | PcieFmConfigureClock ( |
| 330 | IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, |
| 331 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 332 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 333 | ) |
| 334 | { |
| 335 | } |
| 336 | |
| 337 | |
| 338 | /*----------------------------------------------------------------------------------------*/ |
| 339 | /** |
| 340 | * Get configuration Value for GPP wrapper |
| 341 | * |
| 342 | * |
| 343 | * |
| 344 | * @param[in] ConfigurationSignature Configuration signature |
| 345 | * @param[out] ConfigurationValue Configuration value |
| 346 | * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue |
| 347 | * @retval AGESA_ERROR ConfigurationSignature is incorrect |
| 348 | */ |
| 349 | AGESA_STATUS |
| 350 | PcieOnGetGppConfigurationValue ( |
| 351 | IN UINT64 ConfigurationSignature, |
| 352 | OUT UINT8 *ConfigurationValue |
| 353 | ) |
| 354 | { |
| 355 | switch (ConfigurationSignature) { |
| 356 | case GPP_CORE_x4x1x1x1x1: |
| 357 | *ConfigurationValue = 0x4; |
| 358 | break; |
| 359 | case GPP_CORE_x4x2x1x1: |
| 360 | case GPP_CORE_x4x2x1x1_ST: |
| 361 | //Configuration 2:1:1 - Device Numbers 4:5:6 |
| 362 | //Configuration 2:1:1 - Device Numbers 4:6:7 |
| 363 | *ConfigurationValue = 0x3; |
| 364 | break; |
| 365 | case GPP_CORE_x4x2x2: |
| 366 | case GPP_CORE_x4x2x2_ST: |
| 367 | //Configuration 2:2 - Device Numbers 4:5 |
| 368 | //Configuration 2:2 - Device Numbers 4:6 |
| 369 | *ConfigurationValue = 0x2; |
| 370 | break; |
| 371 | case GPP_CORE_x4x4: |
| 372 | *ConfigurationValue = 0x1; |
| 373 | break; |
| 374 | default: |
| 375 | ASSERT (FALSE); |
| 376 | return AGESA_ERROR; |
| 377 | } |
| 378 | return AGESA_SUCCESS; |
| 379 | } |
| 380 | |
| 381 | /*----------------------------------------------------------------------------------------*/ |
| 382 | /** |
| 383 | * Get core configuration value |
| 384 | * |
| 385 | * |
| 386 | * |
| 387 | * @param[in] Wrapper Pointer to internal configuration data area |
| 388 | * @param[in] CoreId Core ID |
| 389 | * @param[in] ConfigurationSignature Configuration signature |
| 390 | * @param[out] ConfigurationValue Configuration value (for core configuration) |
| 391 | * @retval AGESA_SUCCESS Configuration successfully applied |
| 392 | * @retval AGESA_ERROR Core configuration value can not be determined |
| 393 | */ |
| 394 | AGESA_STATUS |
| 395 | PcieFmGetCoreConfigurationValue ( |
| 396 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 397 | IN UINT8 CoreId, |
| 398 | IN UINT64 ConfigurationSignature, |
| 399 | IN UINT8 *ConfigurationValue |
| 400 | ) |
| 401 | { |
| 402 | AGESA_STATUS Status; |
| 403 | |
| 404 | if (Wrapper->WrapId == GPP_WRAP_ID) { |
| 405 | Status = PcieOnGetGppConfigurationValue (ConfigurationSignature, ConfigurationValue); |
| 406 | } else { |
| 407 | Status = AGESA_ERROR; |
| 408 | } |
| 409 | return Status; |
| 410 | } |
| 411 | |
| 412 | /*----------------------------------------------------------------------------------------*/ |
| 413 | /** |
| 414 | * Get max link speed capability supported by this port |
| 415 | * |
| 416 | * |
| 417 | * |
| 418 | * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX |
| 419 | * @param[in] Engine Pointer to engine config descriptor |
| 420 | * @param[in] Pcie Pointer to global PCIe configuration |
| 421 | * @retval PcieGen1/PcieGen2 Max supported link gen capability |
| 422 | */ |
| 423 | PCIE_LINK_SPEED_CAP |
| 424 | PcieFmGetLinkSpeedCap ( |
| 425 | IN UINT32 Flags, |
| 426 | IN PCIe_ENGINE_CONFIG *Engine, |
| 427 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 428 | ) |
| 429 | { |
| 430 | PCIE_LINK_SPEED_CAP LinkSpeedCapability; |
| 431 | ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen); |
| 432 | LinkSpeedCapability = PcieGen2; |
| 433 | if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { |
| 434 | Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; |
| 435 | } |
| 436 | if (Pcie->PsppPolicy == PsppPowerSaving) { |
| 437 | LinkSpeedCapability = PcieGen1; |
| 438 | } |
| 439 | if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { |
| 440 | LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; |
| 441 | } |
| 442 | if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 443 | if (Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 444 | LinkSpeedCapability = PcieGen1; |
| 445 | } |
| 446 | } |
| 447 | return LinkSpeedCapability; |
| 448 | } |
| 449 | |
| 450 | |
| 451 | /*----------------------------------------------------------------------------------------*/ |
| 452 | /** |
| 453 | * Various initialization needed prior topology and configuration initialization |
| 454 | * |
| 455 | * |
| 456 | * |
| 457 | * @param[in] Pcie Pointer to global PCIe configuration |
| 458 | * |
| 459 | */ |
| 460 | VOID |
| 461 | PcieFmPreInit ( |
| 462 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 463 | ) |
| 464 | { |
| 465 | UINT32 Index; |
| 466 | PCIe_SILICON_CONFIG *Silicon; |
| 467 | PCIE_LINK_SPEED_CAP GlobalCapability; |
| 468 | F14_PCIe_WRAPPER_CONFIG *F14PcieWrapper; |
| 469 | |
| 470 | Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]); |
| 471 | F14PcieWrapper = &((F14_COMPLEX_CONFIG*) Silicon)->FmGppWrapper ; |
| 472 | GlobalCapability = PcieUtilGlobalGenCapability ( |
| 473 | PCIE_PORT_GEN_CAP_MAX | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, |
| 474 | Pcie |
| 475 | ); |
| 476 | if ((GlobalCapability == PcieGen1) && (F14PcieWrapper->NativeGen1Support == TRUE)) { |
| 477 | PcieFmExecuteNativeGen1Reconfig (Pcie); |
| 478 | } |
| 479 | Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]); |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 480 | for (Index = 0; Index < ARRAY_SIZE(PcieInitTable); Index++) { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 481 | PcieSiliconRegisterRMW ( |
| 482 | Silicon, |
| 483 | PcieInitTable[Index].Reg, |
| 484 | PcieInitTable[Index].Mask, |
| 485 | PcieInitTable[Index].Data, |
| 486 | FALSE, |
| 487 | Pcie |
| 488 | ); |
| 489 | } |
| 490 | |
| 491 | // Set PCIe SSID. |
| 492 | PcieSiliconRegisterRMW ( |
| 493 | Silicon, |
| 494 | WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS), |
| 495 | D0F0xE4_WRAP_8002_SubsystemVendorID_MASK | D0F0xE4_WRAP_8002_SubsystemID_MASK, |
| 496 | UserOptions.CfgGnbPcieSSID, |
| 497 | FALSE, |
| 498 | Pcie |
| 499 | ); |
| 500 | } |
| 501 | |
| 502 | /*----------------------------------------------------------------------------------------*/ |
| 503 | /** |
| 504 | * Check if engine can be remapped to Device/function number requested by user |
| 505 | * defined engine descriptor |
| 506 | * |
| 507 | * Function only called if requested device/function does not much native device/function |
| 508 | * |
| 509 | * @param[in] PortDescriptor Pointer to user defined engine descriptor |
| 510 | * @param[in] Engine Pointer engine configuration |
| 511 | * @retval TRUE Descriptor can be mapped to engine |
| 512 | * @retval FALSE Descriptor can NOT be mapped to engine |
| 513 | */ |
| 514 | |
| 515 | BOOLEAN |
| 516 | PcieFmCheckPortPciDeviceMapping ( |
| 517 | IN PCIe_PORT_DESCRIPTOR *PortDescriptor, |
| 518 | IN PCIe_ENGINE_CONFIG *Engine |
| 519 | ) |
| 520 | { |
| 521 | return FALSE; |
| 522 | } |
| 523 | |
| 524 | /*----------------------------------------------------------------------------------------*/ |
| 525 | /** |
| 526 | * Get core configuration string |
| 527 | * |
| 528 | * Debug function for logging configuration |
| 529 | * |
| 530 | * @param[in] Wrapper Pointer to internal configuration data area |
| 531 | * @param[in] ConfigurationValue Configuration value |
| 532 | * @retval Configuration string |
| 533 | */ |
| 534 | |
| 535 | CONST CHAR8* |
| 536 | PcieFmDebugGetCoreConfigurationString ( |
| 537 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 538 | IN UINT8 ConfigurationValue |
| 539 | ) |
| 540 | { |
| 541 | switch (ConfigurationValue) { |
| 542 | case 4: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 543 | return (CONST CHAR8*)"1x4, 4x1"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 544 | case 3: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 545 | return (CONST CHAR8*)"1x4, 1x2, 2x1"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 546 | case 2: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 547 | return (CONST CHAR8*)"1x4, 2x2"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 548 | case 1: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 549 | return (CONST CHAR8*)"1x4, 1x4"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 550 | default: |
| 551 | break; |
| 552 | } |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 553 | return (CONST CHAR8*)" !!! Something Wrong !!!"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 554 | } |
| 555 | |
| 556 | /*----------------------------------------------------------------------------------------*/ |
| 557 | /** |
| 558 | * Get wrapper name |
| 559 | * |
| 560 | * Debug function for logging wrapper name |
| 561 | * |
| 562 | * @param[in] Wrapper Pointer to internal configuration data area |
| 563 | * @retval Wrapper Name string |
| 564 | */ |
| 565 | |
| 566 | CONST CHAR8* |
| 567 | PcieFmDebugGetWrapperNameString ( |
| 568 | IN PCIe_WRAPPER_CONFIG *Wrapper |
| 569 | ) |
| 570 | { |
| 571 | switch (Wrapper->WrapId) { |
| 572 | case GPP_WRAP_ID: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 573 | return (CONST CHAR8*)"GPPSB"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 574 | case DDI_WRAP_ID: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 575 | return (CONST CHAR8*)"Virtual DDI"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 576 | default: |
| 577 | break; |
| 578 | } |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 579 | return (CONST CHAR8*)" !!! Something Wrong !!!"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 580 | } |
| 581 | |
| 582 | /*----------------------------------------------------------------------------------------*/ |
| 583 | /** |
| 584 | * Get register address name |
| 585 | * |
| 586 | * Debug function for logging register trace |
| 587 | * |
| 588 | * @param[in] AddressFrame Address Frame |
| 589 | * @retval Register address name |
| 590 | */ |
| 591 | CONST CHAR8* |
| 592 | PcieFmDebugGetHostRegAddressSpaceString ( |
| 593 | IN UINT16 AddressFrame |
| 594 | ) |
| 595 | { |
| 596 | switch (AddressFrame) { |
| 597 | case 0x130: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 598 | return (CONST CHAR8*)"GPP WRAP"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 599 | case 0x110: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 600 | return (CONST CHAR8*)"GPP PIF0"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 601 | case 0x120: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 602 | return (CONST CHAR8*)"GPP PHY0"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 603 | case 0x101: |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 604 | return (CONST CHAR8*)"GPP CORE"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 605 | default: |
| 606 | break; |
| 607 | } |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 608 | return (CONST CHAR8*)" !!! Something Wrong !!!"; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 609 | } |
| 610 | |
| 611 | |
| 612 | /*----------------------------------------------------------------------------------------*/ |
| 613 | /** |
| 614 | * Execute/clean up reconfiguration for Gen 1 native mode |
| 615 | * |
| 616 | * |
| 617 | * |
| 618 | * @param[in] Pcie Pointer to global PCIe configuration |
| 619 | */ |
| 620 | VOID |
| 621 | PcieFmExecuteNativeGen1Reconfig ( |
| 622 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 623 | ) |
| 624 | { |
| 625 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n"); |
| 626 | NbSmuServiceRequest (19, FALSE, GnbLibGetHeader (Pcie)); |
| 627 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n"); |
| 628 | } |
| 629 | |
| 630 | /*----------------------------------------------------------------------------------------*/ |
| 631 | /** |
| 632 | * Check if the lane can be muxed by link width requested by user |
| 633 | * defined engine descriptor |
| 634 | * |
| 635 | * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). |
| 636 | * Check Engine StartCoreLane could be aligned by user requested link width x2. |
| 637 | * |
| 638 | * @param[in] PortDescriptor Pointer to user defined engine descriptor |
| 639 | * @param[in] Engine Pointer engine configuration |
| 640 | * @retval TRUE Lane can be muxed |
| 641 | * @retval FALSE LAne can NOT be muxed |
| 642 | */ |
| 643 | |
| 644 | BOOLEAN |
| 645 | PcieFmCheckPortPcieLaneCanBeMuxed ( |
| 646 | IN PCIe_PORT_DESCRIPTOR *PortDescriptor, |
| 647 | IN PCIe_ENGINE_CONFIG *Engine |
| 648 | ) |
| 649 | { |
| 650 | UINT16 DescriptorHiLane; |
| 651 | UINT16 DescriptorLoLane; |
| 652 | UINT16 DescriptorNumberOfLanes; |
| 653 | PCIe_WRAPPER_CONFIG *Wrapper; |
| 654 | UINT16 NormalizedLoPhyLane; |
| 655 | BOOLEAN Result; |
| 656 | |
| 657 | Result = FALSE; |
| 658 | Wrapper = (PCIe_WRAPPER_CONFIG *)Engine->Wrapper; |
| 659 | DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); |
| 660 | DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); |
| 661 | DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; |
| 662 | |
| 663 | NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; |
| 664 | |
| 665 | if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { |
| 666 | Result = TRUE; |
| 667 | } else { |
| 668 | if (((Engine->Type.Port.StartCoreLane % 2) == 0) || (Engine->Type.Port.StartCoreLane == 0)) { |
| 669 | if (NormalizedLoPhyLane == 0) { |
| 670 | Result = TRUE; |
| 671 | } else { |
| 672 | if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) { |
| 673 | Result = TRUE; |
| 674 | } |
| 675 | } |
| 676 | } |
| 677 | } |
| 678 | |
| 679 | return Result; |
| 680 | } |