Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Family specific PCIe complex initialization services |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "Gnb.h" |
| 53 | #include "GnbPcie.h" |
| 54 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 55 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 56 | #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) |
| 57 | #include "OntarioDefinitions.h" |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 58 | #include "GnbPcieFamServices.h" |
| 59 | #include "PcieFamilyServices.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 60 | #include "GnbRegistersON.h" |
| 61 | #include "NbSmuLib.h" |
| 62 | #include "Filecode.h" |
| 63 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 64 | #define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE |
| 65 | /*---------------------------------------------------------------------------------------- |
| 66 | * D E F I N I T I O N S A N D M A C R O S |
| 67 | *---------------------------------------------------------------------------------------- |
| 68 | */ |
| 69 | |
| 70 | /*---------------------------------------------------------------------------------------- |
| 71 | * T Y P E D E F S A N D S T R U C T U R E S |
| 72 | *---------------------------------------------------------------------------------------- |
| 73 | */ |
| 74 | |
| 75 | |
| 76 | /*---------------------------------------------------------------------------------------- |
| 77 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 78 | *---------------------------------------------------------------------------------------- |
| 79 | */ |
| 80 | |
| 81 | |
| 82 | /*----------------------------------------------------------------------------------------*/ |
| 83 | /** |
| 84 | * Control port visability |
| 85 | * |
| 86 | * |
| 87 | * @param[in] Control Hide/Unhide |
| 88 | * @param[in] Silicon Pointer to silicon configuration descriptor |
| 89 | * @param[in] Pcie Pointer to global PCIe configuration |
| 90 | */ |
| 91 | |
| 92 | VOID |
| 93 | PcieFmPortVisabilityControl ( |
| 94 | IN PCIE_PORT_VISIBILITY Control, |
| 95 | IN PCIe_SILICON_CONFIG *Silicon, |
| 96 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 97 | ) |
| 98 | { |
| 99 | switch (Control) { |
| 100 | case UnhidePorts: |
| 101 | PcieSiliconUnHidePorts (Silicon, Pcie); |
| 102 | break; |
| 103 | case HidePorts: |
| 104 | PcieSiliconHidePorts (Silicon, Pcie); |
| 105 | break; |
| 106 | default: |
| 107 | ASSERT (FALSE); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | /*----------------------------------------------------------------------------------------*/ |
| 112 | /** |
| 113 | * Request boot up voltage |
| 114 | * |
| 115 | * |
| 116 | * |
| 117 | * @param[in] LinkCap Global GEN capability |
| 118 | * @param[in] Pcie Pointer to PCIe configuration data area |
| 119 | */ |
| 120 | VOID |
| 121 | PcieFmSetBootUpVoltage ( |
| 122 | IN PCIE_LINK_SPEED_CAP LinkCap, |
| 123 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 124 | ) |
| 125 | { |
| 126 | FCRxFE00_70A2_STRUCT FCRxFE00_70A2; |
| 127 | D18F3x15C_STRUCT D18F3x15C; |
| 128 | UINT8 TargetVidIndex; |
| 129 | UINT32 Temp; |
| 130 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Enter\n"); |
| 131 | ASSERT (LinkCap <= PcieGen2); |
| 132 | GnbLibPciRead ( |
| 133 | MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), |
| 134 | AccessWidth32, |
| 135 | &D18F3x15C.Value, |
| 136 | GnbLibGetHeader (Pcie) |
| 137 | ); |
| 138 | Temp = D18F3x15C.Value; |
| 139 | if (LinkCap > PcieGen1) { |
| 140 | FCRxFE00_70A2.Value = NbSmuReadEfuse (FCRxFE00_70A2_ADDRESS, GnbLibGetHeader (Pcie)); |
| 141 | TargetVidIndex = (UINT8) FCRxFE00_70A2.Field.PcieGen2Vid; |
| 142 | } else { |
| 143 | TargetVidIndex = PcieSiliconGetGen1VoltageIndex (GnbLibGetHeader (Pcie)); |
| 144 | } |
| 145 | IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid Index %d\n", LinkCap, TargetVidIndex); |
| 146 | if (TargetVidIndex == 3) { |
| 147 | D18F3x15C.Field.SclkVidLevel2 = D18F3x15C.Field.SclkVidLevel3; |
| 148 | GnbLibPciWrite ( |
| 149 | MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), |
| 150 | AccessWidth32, |
| 151 | &D18F3x15C.Value, |
| 152 | GnbLibGetHeader (Pcie) |
| 153 | ); |
| 154 | PcieSiliconRequestVoltage (2, GnbLibGetHeader (Pcie)); |
| 155 | } |
| 156 | GnbLibPciWrite ( |
| 157 | MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), |
| 158 | AccessWidth32, |
| 159 | &Temp, |
| 160 | GnbLibGetHeader (Pcie) |
| 161 | ); |
| 162 | PcieSiliconRequestVoltage (TargetVidIndex, GnbLibGetHeader (Pcie)); |
| 163 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n"); |
| 164 | } |
| 165 | |
| 166 | /*----------------------------------------------------------------------------------------*/ |
| 167 | /** |
| 168 | * Map engine to specific PCI device address |
| 169 | * |
| 170 | * |
| 171 | * |
| 172 | * @param[in] Engine Pointer to engine configuration |
| 173 | * @param[in] Pcie Pointer to PCIe configuration |
| 174 | * @retval AGESA_ERROR Fail to map PCI device address |
| 175 | * @retval AGESA_SUCCESS Successfully allocate PCI address |
| 176 | */ |
| 177 | |
| 178 | AGESA_STATUS |
| 179 | PcieFmMapPortPciAddress ( |
| 180 | IN PCIe_ENGINE_CONFIG *Engine, |
| 181 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 182 | ) |
| 183 | { |
| 184 | PCIe_WRAPPER_CONFIG *Wrapper; |
| 185 | UINT64 ConfigurationSignature; |
| 186 | |
| 187 | Wrapper = PcieEngineGetParentWrapper (Engine); |
| 188 | |
| 189 | if (Wrapper->WrapId == GPP_WRAP_ID) { |
| 190 | ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId); |
| 191 | if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) { |
| 192 | //Enable device remapping |
| 193 | GnbLibPciIndirectRMW ( |
| 194 | MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), |
| 195 | 0x20 | IOC_WRITE_ENABLE, |
| 196 | AccessS3SaveWidth32, |
| 197 | ~(UINT32) (1 << 1), |
| 198 | 0x0, |
| 199 | GnbLibGetHeader (Pcie) |
| 200 | ); |
| 201 | } |
| 202 | } |
| 203 | if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { |
| 204 | Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; |
| 205 | Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; |
| 206 | return AGESA_SUCCESS; |
| 207 | } |
| 208 | if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber && |
| 209 | Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) { |
| 210 | return AGESA_SUCCESS; |
| 211 | } |
| 212 | return AGESA_ERROR; |
| 213 | } |
| 214 | |
| 215 | /*----------------------------------------------------------------------------------------*/ |
| 216 | /** |
| 217 | * Map engine to specific PCI device address |
| 218 | * |
| 219 | * |
| 220 | * |
| 221 | * @param[in] Engine Pointer to engine configuration |
| 222 | * @param[in] Pcie Pointer to PCIe configuration |
| 223 | */ |
| 224 | |
| 225 | |
| 226 | VOID |
| 227 | PcieFmEnableSlotPowerLimit ( |
| 228 | IN PCIe_ENGINE_CONFIG *Engine, |
| 229 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 230 | ) |
| 231 | { |
| 232 | ASSERT (Engine->EngineData.EngineType == PciePortEngine); |
| 233 | if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !Engine->Type.Port.IsSB) { |
| 234 | IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); |
| 235 | GnbLibPciIndirectRMW ( |
| 236 | MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), |
| 237 | (D0F0x64_x55_ADDRESS + (Engine->Type.Port.Address.Address.Device - 4) * 2) | IOC_WRITE_ENABLE, |
| 238 | AccessS3SaveWidth32, |
| 239 | 0xffffffff, |
| 240 | 1 << D0F0x64_x55_SetPowEn_OFFSET, |
| 241 | GnbLibGetHeader (Pcie) |
| 242 | ); |
| 243 | } |
| 244 | } |
| 245 | |