Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * NB power management features |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12 | * @e \$Revision: 47490 $ @e \$Date: 2011-02-22 08:34:28 -0700 (Tue, 22 Feb 2011) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | #include "AGESA.h" |
| 52 | #include "amdlib.h" |
| 53 | #include "Ids.h" |
| 54 | #include "Gnb.h" |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 55 | #include "GnbFuseTable.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 56 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 57 | #include "NbConfigData.h" |
| 58 | #include "NbSmuLib.h" |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 59 | #include "NbFamilyServices.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 60 | #include "NbPowerMgmt.h" |
| 61 | #include "OptionGnb.h" |
| 62 | #include "GfxLib.h" |
| 63 | #include "GnbRegistersON.h" |
| 64 | #include "Filecode.h" |
| 65 | #define FILECODE PROC_GNB_NB_NBPOWERMGMT_FILECODE |
| 66 | /*---------------------------------------------------------------------------------------- |
| 67 | * D E F I N I T I O N S A N D M A C R O S |
| 68 | *---------------------------------------------------------------------------------------- |
| 69 | */ |
| 70 | extern GNB_BUILD_OPTIONS GnbBuildOptions; |
| 71 | |
| 72 | /*---------------------------------------------------------------------------------------- |
| 73 | * T Y P E D E F S A N D S T R U C T U R E S |
| 74 | *---------------------------------------------------------------------------------------- |
| 75 | */ |
| 76 | |
| 77 | |
| 78 | /*---------------------------------------------------------------------------------------- |
| 79 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 80 | *---------------------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | VOID |
| 84 | NbInitLclkDeepSleep ( |
| 85 | IN GNB_PLATFORM_CONFIG *Gnb |
| 86 | ); |
| 87 | |
| 88 | VOID |
| 89 | NbInitClockGating ( |
| 90 | IN GNB_PLATFORM_CONFIG *Gnb |
| 91 | ); |
| 92 | |
| 93 | /*----------------------------------------------------------------------------------------*/ |
| 94 | /** |
| 95 | * Init various power management features |
| 96 | * |
| 97 | * |
| 98 | * |
| 99 | * @param[in] Gnb Pointer to global Gnb configuration |
| 100 | * @retval AGESA_SUCCESS LCLK DPM initialization success |
| 101 | * @retval AGESA_ERROR LCLK DPM initialization error |
| 102 | */ |
| 103 | |
| 104 | AGESA_STATUS |
| 105 | NbInitPowerManagement ( |
| 106 | IN GNB_PLATFORM_CONFIG *Gnb |
| 107 | ) |
| 108 | { |
| 109 | AGESA_STATUS Status; |
| 110 | Status = AGESA_SUCCESS; |
| 111 | NbInitLclkDeepSleep (Gnb); |
| 112 | NbInitClockGating (Gnb); |
| 113 | return Status; |
| 114 | } |
| 115 | |
| 116 | |
| 117 | /*----------------------------------------------------------------------------------------*/ |
| 118 | /** |
| 119 | * Init NB LCLK Deep Sleep |
| 120 | * |
| 121 | * |
| 122 | * |
| 123 | * @param[in] Gnb Pointer to global Gnb configuration |
| 124 | */ |
| 125 | |
| 126 | VOID |
| 127 | NbInitLclkDeepSleep ( |
| 128 | IN GNB_PLATFORM_CONFIG *Gnb |
| 129 | ) |
| 130 | { |
| 131 | SMUx1B_STRUCT SMUx1B; |
| 132 | SMUx1D_STRUCT SMUx1D; |
| 133 | UINT32 LclkDpSlpEn; |
| 134 | IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Enter\n"); |
| 135 | LclkDpSlpEn = GnbBuildOptions.LclkDeepSleepEn ? 1 : 0; |
| 136 | NbSmuIndirectRead (SMUx1B_ADDRESS, AccessWidth16, &SMUx1B.Value, Gnb->StdHeader); |
| 137 | NbSmuIndirectRead (SMUx1D_ADDRESS, AccessWidth16, &SMUx1D.Value, Gnb->StdHeader); |
| 138 | SMUx1B.Field.LclkDpSlpDiv = 5; |
| 139 | SMUx1B.Field.LclkDpSlpMask = (GfxLibIsControllerPresent (Gnb->StdHeader) ? (0xFF) : 0xEF); |
| 140 | SMUx1B.Field.RampDis = 0; |
| 141 | SMUx1D.Field.LclkDpSlpHyst = 0xf; |
| 142 | IDS_OPTION_HOOK (IDS_GNB_LCLK_DEEP_SLEEP, &LclkDpSlpEn, Gnb->StdHeader); |
| 143 | SMUx1D.Field.LclkDpSlpEn = LclkDpSlpEn; |
| 144 | IDS_HDT_CONSOLE (GNB_TRACE, " LCLK Deep Sleep [%s]\n", (LclkDpSlpEn != 0) ? "Enabled" : "Disabled"); |
| 145 | NbSmuIndirectWrite (SMUx1B_ADDRESS, AccessS3SaveWidth16, &SMUx1B.Value, Gnb->StdHeader); |
| 146 | NbSmuIndirectWrite (SMUx1D_ADDRESS, AccessS3SaveWidth16, &SMUx1D.Value, Gnb->StdHeader); |
| 147 | IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Exit\n"); |
| 148 | } |
| 149 | |
| 150 | /** |
| 151 | * Init NB SMU clock gating |
| 152 | * |
| 153 | * |
| 154 | * |
| 155 | * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure |
| 156 | * @param[in] Gnb Pointer to global Gnb configuration |
| 157 | */ |
| 158 | |
| 159 | VOID |
| 160 | NbInitSmuClockGating ( |
| 161 | IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, |
| 162 | IN GNB_PLATFORM_CONFIG *Gnb |
| 163 | ) |
| 164 | { |
| 165 | BOOLEAN Smu_Lclk_Gating; |
| 166 | BOOLEAN Smu_Sclk_Gating; |
| 167 | SMUx73_STRUCT SMUx73; |
| 168 | UINT32 Value; |
| 169 | |
| 170 | Smu_Lclk_Gating = NbClkGatingCtrl->Smu_Lclk_Gating; |
| 171 | Smu_Sclk_Gating = NbClkGatingCtrl->Smu_Sclk_Gating; |
| 172 | //SMUx6F |
| 173 | Value = 0x006001F0; |
| 174 | NbSmuIndirectWrite (SMUx6F_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader); |
| 175 | //SMUx71 |
| 176 | Value = 0x007001F0; |
| 177 | NbSmuIndirectWrite (SMUx71_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader); |
| 178 | //SMUx73 |
| 179 | NbSmuIndirectRead (SMUx73_ADDRESS, AccessWidth16, &SMUx73.Value, Gnb->StdHeader); |
| 180 | SMUx73.Field.DisLclkGating = Smu_Lclk_Gating ? 0 : 1; |
| 181 | SMUx73.Field.DisSclkGating = Smu_Sclk_Gating ? 0 : 1; |
| 182 | NbSmuIndirectWrite (SMUx73_ADDRESS, AccessS3SaveWidth16, &SMUx73.Value, Gnb->StdHeader); |
| 183 | |
| 184 | } |
| 185 | |
| 186 | /** |
| 187 | * Init NB ORB clock gating |
| 188 | * |
| 189 | * |
| 190 | * |
| 191 | * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure |
| 192 | * @param[in] Gnb Pointer to global Gnb configuration |
| 193 | */ |
| 194 | |
| 195 | VOID |
| 196 | NbInitOrbClockGating ( |
| 197 | IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, |
| 198 | IN GNB_PLATFORM_CONFIG *Gnb |
| 199 | ) |
| 200 | { |
| 201 | BOOLEAN Orb_Sclk_Gating; |
| 202 | BOOLEAN Orb_Lclk_Gating; |
| 203 | D0F0x98_x49_STRUCT D0F0x98_x49; |
| 204 | D0F0x98_x4A_STRUCT D0F0x98_x4A; |
| 205 | D0F0x98_x4B_STRUCT D0F0x98_x4B; |
| 206 | FCRxFF30_01F5_STRUCT FCRxFF30_01F5; |
| 207 | |
| 208 | Orb_Sclk_Gating = NbClkGatingCtrl->Orb_Sclk_Gating; |
| 209 | Orb_Lclk_Gating = NbClkGatingCtrl->Orb_Lclk_Gating; |
| 210 | |
| 211 | // ORB clock gating (Lclk) |
| 212 | //D0F0x98_x4[A:9] |
| 213 | GnbLibPciIndirectRead ( |
| 214 | Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, |
| 215 | D0F0x98_x49_ADDRESS, |
| 216 | AccessWidth32, |
| 217 | &D0F0x98_x49.Value, |
| 218 | Gnb->StdHeader |
| 219 | ); |
| 220 | |
| 221 | D0F0x98_x49.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1; |
| 222 | D0F0x98_x49.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1; |
| 223 | D0F0x98_x49.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1; |
| 224 | D0F0x98_x49.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1; |
| 225 | D0F0x98_x49.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1; |
| 226 | D0F0x98_x49.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1; |
| 227 | D0F0x98_x49.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1; |
| 228 | |
| 229 | GnbLibPciIndirectWrite ( |
| 230 | Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, |
| 231 | D0F0x98_x49_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), |
| 232 | AccessS3SaveWidth32, |
| 233 | &D0F0x98_x49.Value, |
| 234 | Gnb->StdHeader |
| 235 | ); |
| 236 | |
| 237 | GnbLibPciIndirectRead ( |
| 238 | Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, |
| 239 | D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), |
| 240 | AccessWidth32, |
| 241 | &D0F0x98_x4A.Value, |
| 242 | Gnb->StdHeader |
| 243 | ); |
| 244 | |
| 245 | D0F0x98_x4A.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1; |
| 246 | D0F0x98_x4A.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1; |
| 247 | D0F0x98_x4A.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1; |
| 248 | D0F0x98_x4A.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1; |
| 249 | D0F0x98_x4A.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1; |
| 250 | D0F0x98_x4A.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1; |
| 251 | D0F0x98_x4A.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1; |
| 252 | |
| 253 | |
| 254 | GnbLibPciIndirectWrite ( |
| 255 | Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, |
| 256 | D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), |
| 257 | AccessS3SaveWidth32, |
| 258 | &D0F0x98_x4A.Value, |
| 259 | Gnb->StdHeader |
| 260 | ); |
| 261 | |
| 262 | //D0F0x98_x4B |
| 263 | GnbLibPciIndirectRead ( |
| 264 | Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, |
| 265 | D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), |
| 266 | AccessWidth32, |
| 267 | &D0F0x98_x4B.Value, |
| 268 | Gnb->StdHeader |
| 269 | ); |
| 270 | |
| 271 | D0F0x98_x4B.Field.SoftOverrideClk = Orb_Sclk_Gating ? 0 : 1; |
| 272 | |
| 273 | GnbLibPciIndirectWrite ( |
| 274 | Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, |
| 275 | D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), |
| 276 | AccessS3SaveWidth32, |
| 277 | &D0F0x98_x4B.Value, |
| 278 | Gnb->StdHeader |
| 279 | ); |
| 280 | |
| 281 | //FCRxFF30_01F5[CgOrbCgttLclkOverride, CgOrbCgttSclkOverride] |
| 282 | NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); |
| 283 | FCRxFF30_01F5.Field.CgOrbCgttLclkOverride = 0; |
| 284 | FCRxFF30_01F5.Field.CgOrbCgttSclkOverride = 0; |
| 285 | NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); |
| 286 | |
| 287 | } |
| 288 | |
| 289 | /** |
| 290 | * Init NB IOC clock gating |
| 291 | * |
| 292 | * |
| 293 | * |
| 294 | * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure |
| 295 | * @param[in] Gnb Pointer to global Gnb configuration |
| 296 | */ |
| 297 | |
| 298 | VOID |
| 299 | NbInitIocClockGating ( |
| 300 | IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, |
| 301 | IN GNB_PLATFORM_CONFIG *Gnb |
| 302 | ) |
| 303 | { |
| 304 | BOOLEAN Ioc_Lclk_Gating; |
| 305 | BOOLEAN Ioc_Sclk_Gating; |
| 306 | D0F0x64_x22_STRUCT D0F0x64_x22; |
| 307 | D0F0x64_x23_STRUCT D0F0x64_x23; |
| 308 | D0F0x64_x24_STRUCT D0F0x64_x24; |
| 309 | FCRxFF30_01F5_STRUCT FCRxFF30_01F5; |
| 310 | |
| 311 | Ioc_Lclk_Gating = NbClkGatingCtrl->Ioc_Lclk_Gating; |
| 312 | Ioc_Sclk_Gating = NbClkGatingCtrl->Ioc_Sclk_Gating; |
| 313 | |
| 314 | //D0F0x64_x22 |
| 315 | GnbLibPciIndirectRead ( |
| 316 | Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, |
| 317 | D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE, |
| 318 | AccessWidth32, |
| 319 | &D0F0x64_x22.Value, |
| 320 | Gnb->StdHeader |
| 321 | ); |
| 322 | |
| 323 | D0F0x64_x22.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1; |
| 324 | D0F0x64_x22.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1; |
| 325 | D0F0x64_x22.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1; |
| 326 | D0F0x64_x22.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1; |
| 327 | D0F0x64_x22.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1; |
| 328 | |
| 329 | GnbLibPciIndirectWrite ( |
| 330 | Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, |
| 331 | D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE, |
| 332 | AccessS3SaveWidth32, |
| 333 | &D0F0x64_x22.Value, |
| 334 | Gnb->StdHeader |
| 335 | ); |
| 336 | //D0F0x64_x23 |
| 337 | GnbLibPciIndirectRead ( |
| 338 | Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, |
| 339 | D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE, |
| 340 | AccessWidth32, |
| 341 | &D0F0x64_x23.Value, |
| 342 | Gnb->StdHeader |
| 343 | ); |
| 344 | |
| 345 | //D0F0x64_x23.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1; |
| 346 | D0F0x64_x23.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1; |
| 347 | D0F0x64_x23.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1; |
| 348 | D0F0x64_x23.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1; |
| 349 | D0F0x64_x23.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1; |
| 350 | |
| 351 | GnbLibPciIndirectWrite ( |
| 352 | Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, |
| 353 | D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE, |
| 354 | AccessS3SaveWidth32, |
| 355 | &D0F0x64_x23.Value, |
| 356 | Gnb->StdHeader |
| 357 | ); |
| 358 | //D0F0x64_x24 |
| 359 | GnbLibPciIndirectRead ( |
| 360 | Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, |
| 361 | D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE, |
| 362 | AccessWidth32, |
| 363 | &D0F0x64_x24.Value, |
| 364 | Gnb->StdHeader |
| 365 | ); |
| 366 | |
| 367 | D0F0x64_x24.Field.SoftOverrideClk1 = Ioc_Sclk_Gating ? 0 : 1; |
| 368 | D0F0x64_x24.Field.SoftOverrideClk0 = Ioc_Sclk_Gating ? 0 : 1; |
| 369 | |
| 370 | GnbLibPciIndirectWrite ( |
| 371 | Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, |
| 372 | D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE, |
| 373 | AccessS3SaveWidth32, |
| 374 | &D0F0x64_x24.Value, |
| 375 | Gnb->StdHeader |
| 376 | ); |
| 377 | //FCRxFF30_01F5[CgIocCgttLclkOverride, CgIocCgttSclkOverride] |
| 378 | NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); |
| 379 | FCRxFF30_01F5.Field.CgIocCgttLclkOverride = 0; |
| 380 | FCRxFF30_01F5.Field.CgIocCgttSclkOverride = 0; |
| 381 | NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); |
| 382 | } |
| 383 | /** |
| 384 | * Init NB BIF clock gating |
| 385 | * |
| 386 | * |
| 387 | * |
| 388 | * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure |
| 389 | * @param[in] Gnb Pointer to global Gnb configuration |
| 390 | */ |
| 391 | |
| 392 | VOID |
| 393 | NbInitBifClockGating ( |
| 394 | IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, |
| 395 | IN GNB_PLATFORM_CONFIG *Gnb |
| 396 | ) |
| 397 | { |
| 398 | BOOLEAN Bif_Sclk_Gating; |
| 399 | FCRxFF30_01F4_STRUCT FCRxFF30_01F4; |
| 400 | FCRxFF30_1512_STRUCT FCRxFF30_1512; |
| 401 | |
| 402 | |
| 403 | Bif_Sclk_Gating = NbClkGatingCtrl->Bif_Sclk_Gating; |
| 404 | |
| 405 | //FCRxFF30_01F4[CgBifCgttSclkOverride]. |
| 406 | NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); |
| 407 | FCRxFF30_01F4.Field.CgBifCgttSclkOverride = 0; |
| 408 | NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); |
| 409 | //FCRxFF30_1512 |
| 410 | NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader); |
| 411 | FCRxFF30_1512.Field.SoftOverride0 = Bif_Sclk_Gating ? 0 : 1; |
| 412 | NbSmuSrbmRegisterWrite (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, TRUE, Gnb->StdHeader); |
| 413 | |
| 414 | } |
| 415 | |
| 416 | /** |
| 417 | * Init NB Gmc clock gating |
| 418 | * |
| 419 | * |
| 420 | * |
| 421 | * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure |
| 422 | * @param[in] Gnb Pointer to global Gnb configuration |
| 423 | */ |
| 424 | |
| 425 | VOID |
| 426 | NbInitGmcClockGating ( |
| 427 | IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, |
| 428 | IN GNB_PLATFORM_CONFIG *Gnb |
| 429 | ) |
| 430 | { |
| 431 | BOOLEAN Gmc_Sclk_Gating; |
| 432 | FCRxFF30_01F4_STRUCT FCRxFF30_01F4; |
| 433 | FCRxFF30_01F5_STRUCT FCRxFF30_01F5; |
| 434 | |
| 435 | Gmc_Sclk_Gating = NbClkGatingCtrl->Gmc_Sclk_Gating; |
| 436 | |
| 437 | //FCRxFF30_01F4[CgMcdwCgttSclkOverride, CgMcbCgttSclkOverride] |
| 438 | NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); |
| 439 | FCRxFF30_01F4.Field.CgMcbCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; |
| 440 | FCRxFF30_01F4.Field.CgMcdwCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; |
| 441 | NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); |
| 442 | |
| 443 | //FCRxFF30_01F5[CgVmcCgttSclkOverride] |
| 444 | NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); |
| 445 | FCRxFF30_01F5.Field.CgVmcCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; |
| 446 | NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); |
| 447 | |
| 448 | } |
| 449 | |
| 450 | /** |
| 451 | * Init NB Dce Sclk clock gating |
| 452 | * |
| 453 | * |
| 454 | * |
| 455 | * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure |
| 456 | * @param[in] Gnb Pointer to global Gnb configuration |
| 457 | */ |
| 458 | |
| 459 | VOID |
| 460 | NbInitDceSclkClockGating ( |
| 461 | IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, |
| 462 | IN GNB_PLATFORM_CONFIG *Gnb |
| 463 | ) |
| 464 | { |
| 465 | BOOLEAN Dce_Sclk_Gating; |
| 466 | FCRxFF30_0134_STRUCT FCRxFF30_0134; |
| 467 | FCRxFF30_01F4_STRUCT FCRxFF30_01F4; |
| 468 | |
| 469 | Dce_Sclk_Gating = NbClkGatingCtrl->Dce_Sclk_Gating; |
| 470 | |
| 471 | //GMMx4D0[SymclkbGateDisable, SymclkaGateDisable, SclkGateDisable] |
| 472 | NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader); |
| 473 | FCRxFF30_0134.Field.SclkGateDisable = Dce_Sclk_Gating ? 0 : 1; |
| 474 | FCRxFF30_0134.Field.SymclkaGateDisable = Dce_Sclk_Gating ? 0 : 1; |
| 475 | FCRxFF30_0134.Field.SymclkbGateDisable = Dce_Sclk_Gating ? 0 : 1; |
| 476 | NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader); |
| 477 | |
| 478 | //FCRxFF30_01F4[CgDcCgttSclkOverride] |
| 479 | NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); |
| 480 | FCRxFF30_01F4.Field.CgDcCgttSclkOverride = 0; |
| 481 | NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); |
| 482 | |
| 483 | } |
| 484 | |
| 485 | /** |
| 486 | * Init NB Dce Display clock gating |
| 487 | * |
| 488 | * |
| 489 | * |
| 490 | * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure |
| 491 | * @param[in] Gnb Pointer to global Gnb configuration |
| 492 | */ |
| 493 | |
| 494 | VOID |
| 495 | NbInitDceDisplayClockGating ( |
| 496 | IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, |
| 497 | IN GNB_PLATFORM_CONFIG *Gnb |
| 498 | ) |
| 499 | { |
| 500 | BOOLEAN Dce_Dispclk_Gating; |
| 501 | FCRxFF30_0134_STRUCT FCRxFF30_0134; |
| 502 | FCRxFF30_1B7C_STRUCT FCRxFF30_1B7C; |
| 503 | FCRxFF30_1E7C_STRUCT FCRxFF30_1E7C; |
| 504 | FCRxFF30_01F5_STRUCT FCRxFF30_01F5; |
| 505 | |
| 506 | Dce_Dispclk_Gating = NbClkGatingCtrl->Dce_Dispclk_Gating; |
| 507 | |
| 508 | //GMMx4D0[DispclkRDccgGateDisable,DispclkDccgGateDisable] |
| 509 | NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader); |
| 510 | FCRxFF30_0134.Field.DispclkDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1; |
| 511 | FCRxFF30_0134.Field.DispclkRDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1; |
| 512 | NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader); |
| 513 | |
| 514 | //GMMx[79,6D]F0[CrtcDispclkGSclGateDisable, CrtcDispclkGDcpGateDisable, CrtcDispclkRDcfeGateDisable] |
| 515 | NbSmuSrbmRegisterRead (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, Gnb->StdHeader); |
| 516 | FCRxFF30_1B7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1; |
| 517 | FCRxFF30_1B7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1; |
| 518 | FCRxFF30_1B7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1; |
| 519 | NbSmuSrbmRegisterWrite (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, TRUE, Gnb->StdHeader); |
| 520 | |
| 521 | NbSmuSrbmRegisterRead (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, Gnb->StdHeader); |
| 522 | FCRxFF30_1E7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1; |
| 523 | FCRxFF30_1E7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1; |
| 524 | FCRxFF30_1E7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1; |
| 525 | NbSmuSrbmRegisterWrite (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, TRUE, Gnb->StdHeader); |
| 526 | |
| 527 | //FCRxFF30_01F5[CgDcCgttDispclkOverride] |
| 528 | NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 529 | FCRxFF30_01F5.Field.CgDcCgttDispclkOverride = 0; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 530 | NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); |
| 531 | |
| 532 | } |
| 533 | |
| 534 | /*----------------------------------------------------------------------------------------*/ |
| 535 | /** |
| 536 | * Init NB clock gating |
| 537 | * |
| 538 | * |
| 539 | * |
| 540 | * @param[in] Gnb Pointer to global Gnb configuration |
| 541 | */ |
| 542 | |
| 543 | VOID |
| 544 | NbInitClockGating ( |
| 545 | IN GNB_PLATFORM_CONFIG *Gnb |
| 546 | ) |
| 547 | { |
| 548 | NB_CLK_GATING_CTRL NbClkGatingCtrl; |
| 549 | |
| 550 | //Init the default value of control structure. |
| 551 | NbClkGatingCtrl.Smu_Sclk_Gating = GnbBuildOptions.SmuSclkClockGatingEnable; |
| 552 | NbClkGatingCtrl.Smu_Lclk_Gating = TRUE; |
| 553 | NbClkGatingCtrl.Orb_Sclk_Gating = TRUE; |
| 554 | NbClkGatingCtrl.Orb_Lclk_Gating = TRUE; |
| 555 | NbClkGatingCtrl.Ioc_Sclk_Gating = TRUE; |
| 556 | NbClkGatingCtrl.Ioc_Lclk_Gating = TRUE; |
| 557 | NbClkGatingCtrl.Bif_Sclk_Gating = TRUE; |
| 558 | NbClkGatingCtrl.Gmc_Sclk_Gating = TRUE; |
| 559 | NbClkGatingCtrl.Dce_Sclk_Gating = TRUE; |
| 560 | NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE; |
| 561 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 562 | NbFmNbClockGating (&NbClkGatingCtrl, Gnb->StdHeader); |
| 563 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 564 | IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader); |
| 565 | |
| 566 | |
| 567 | IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating Enter\n"); |
| 568 | |
| 569 | //SMU SCLK/LCLK clock gating |
| 570 | NbInitSmuClockGating (&NbClkGatingCtrl, Gnb); |
| 571 | |
| 572 | // ORB clock gating |
| 573 | NbInitOrbClockGating (&NbClkGatingCtrl, Gnb); |
| 574 | |
| 575 | //IOC clock gating |
| 576 | NbInitIocClockGating (&NbClkGatingCtrl, Gnb); |
| 577 | |
| 578 | //BIF Clock Gating |
| 579 | NbInitBifClockGating (&NbClkGatingCtrl, Gnb); |
| 580 | |
| 581 | //GMC Clock Gating |
| 582 | NbInitGmcClockGating (&NbClkGatingCtrl, Gnb); |
| 583 | |
| 584 | //DCE Sclk clock gating |
| 585 | NbInitDceSclkClockGating (&NbClkGatingCtrl, Gnb); |
| 586 | |
| 587 | //DCE Display clock gating |
| 588 | NbInitDceDisplayClockGating (&NbClkGatingCtrl, Gnb); |
| 589 | |
| 590 | GNB_DEBUG_CODE ( |
| 591 | { |
| 592 | FCRxFF30_01F4_STRUCT FCRxFF30_01F4; |
| 593 | FCRxFF30_01F5_STRUCT FCRxFF30_01F5; |
| 594 | FCRxFF30_1512_STRUCT FCRxFF30_1512; |
| 595 | NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); |
| 596 | NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); |
| 597 | NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader); |
| 598 | IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F4 - 0x%x\n", FCRxFF30_01F4.Value); |
| 599 | IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F5 - 0x%x\n", FCRxFF30_01F5.Value); |
| 600 | IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_1512 - 0x%x\n", FCRxFF30_1512.Value); |
| 601 | } |
| 602 | ); |
| 603 | IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating End\n"); |
| 604 | } |