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review.coreboot.org / coreboot / dbdf170dcdf9edbc860766606e53c6d647d89d38 / . / src / vendorcode / amd / agesa / f14 / Proc / GNB / Nb / NbInitAtPost.c
blob: 57280a1fc52ad5d0f715183d1a2dfa91b564c624 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * NB Post initialization interface
6 *
7 *
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: GNB
12 * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
13 *
14 */
15/*
16 *****************************************************************************
17 *
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]20 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]30 * from this software without specific prior written permission.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]31 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +1000[diff] [blame]42 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]43 * ***************************************************************************
44 *
45 */
46
47/*----------------------------------------------------------------------------------------
48 * M O D U L E S U S E D
49 *----------------------------------------------------------------------------------------
50 */
51#include "AGESA.h"
52#include "amdlib.h"
53#include "Ids.h"
54#include "Gnb.h"
55#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
56#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1)
57#include "NbConfigData.h"
58#include "NbInitAtPost.h"
59#include "Filecode.h"
60#define FILECODE PROC_GNB_NB_NBINITATPOST_FILECODE
61/*----------------------------------------------------------------------------------------
62 * D E F I N I T I O N S A N D M A C R O S
63 *----------------------------------------------------------------------------------------
64 */
65
66
67/*----------------------------------------------------------------------------------------
68 * T Y P E D E F S A N D S T R U C T U R E S
69 *----------------------------------------------------------------------------------------
70 */
71
72
73/*----------------------------------------------------------------------------------------
74 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
75 *----------------------------------------------------------------------------------------
76 */
77
78
79
80/*----------------------------------------------------------------------------------------*/
81/**
82 * Init NB at POST
83 *
84 *
85 *
86 * @param[in] StdHeader Standard configuration header
87 * @retval AGESA_STATUS
88 */
89
90AGESA_STATUS
91NbInitAtPost (
92 IN AMD_CONFIG_PARAMS *StdHeader
93 )
94{
95 AGESA_STATUS Status;
96 AGESA_STATUS AgesaStatus;
97 GNB_PLATFORM_CONFIG Gnb;
98 UINT32 NumberOfSockets;
99 UINT32 SocketId;
100 AgesaStatus = AGESA_SUCCESS;
101 IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Enter\n");
102 NbAllocateConfigData (StdHeader, &Gnb);
103 NumberOfSockets = GnbGetNumberOfSockets (StdHeader);
104 for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
105 UINT32 NumberOfSilicons;
106 UINT32 SiliconId;
107 if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
108 continue;
109 }
110 NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader);
111 for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) {
112 Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader);
113 Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader);
114 AGESA_STATUS_UPDATE (Status, AgesaStatus);
115 ASSERT (Status == AGESA_SUCCESS);
116 }
117 }
118 IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Exit[0x%x]\n", AgesaStatus);
119 return AgesaStatus;
120}
121
122