Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Graphics Controller family specific service procedure |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 12 | * @e \$Revision: 48498 $ @e \$Date: 2011-03-09 12:44:53 -0700 (Wed, 09 Mar 2011) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | |
| 48 | /*---------------------------------------------------------------------------------------- |
| 49 | * M O D U L E S U S E D |
| 50 | *---------------------------------------------------------------------------------------- |
| 51 | */ |
| 52 | #include "AGESA.h" |
| 53 | #include "amdlib.h" |
| 54 | #include "Ids.h" |
| 55 | #include "Gnb.h" |
| 56 | #include "GnbFuseTable.h" |
| 57 | #include "GnbPcie.h" |
| 58 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 59 | #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) |
| 60 | #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 61 | #include "NbConfigData.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 62 | #include "OptionGnb.h" |
| 63 | #include "NbLclkDpm.h" |
| 64 | #include "NbFamilyServices.h" |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 65 | #include "NbPowerMgmt.h" |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 66 | #include "GfxLib.h" |
| 67 | #include "GnbRegistersON.h" |
| 68 | #include "cpuFamilyTranslation.h" |
| 69 | #include "Filecode.h" |
| 70 | #define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE |
| 71 | /*---------------------------------------------------------------------------------------- |
| 72 | * D E F I N I T I O N S A N D M A C R O S |
| 73 | *---------------------------------------------------------------------------------------- |
| 74 | */ |
| 75 | |
| 76 | |
| 77 | /*---------------------------------------------------------------------------------------- |
| 78 | * T Y P E D E F S A N D S T R U C T U R E S |
| 79 | *---------------------------------------------------------------------------------------- |
| 80 | */ |
| 81 | |
| 82 | extern GNB_BUILD_OPTIONS GnbBuildOptions; |
| 83 | FUSE_TABLE FuseTable; |
| 84 | |
| 85 | /*---------------------------------------------------------------------------------------- |
| 86 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 87 | *---------------------------------------------------------------------------------------- |
| 88 | */ |
| 89 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 90 | /*----------------------------------------------------------------------------------------*/ |
| 91 | /** |
| 92 | * NB family specific clock gating |
| 93 | * |
| 94 | * |
| 95 | * @param[in, out] NbClkGatingCtrl Pointer to NB_CLK_GATING_CTRL |
| 96 | * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS |
| 97 | */ |
| 98 | VOID |
| 99 | NbFmNbClockGating ( |
| 100 | IN OUT VOID *NbClkGatingCtrl, |
| 101 | IN AMD_CONFIG_PARAMS *StdHeader |
| 102 | ) |
| 103 | { |
| 104 | NB_CLK_GATING_CTRL *NbClkGatingCtrlPtr; |
| 105 | CPU_LOGICAL_ID LogicalId; |
| 106 | |
| 107 | NbClkGatingCtrlPtr = (NB_CLK_GATING_CTRL *)NbClkGatingCtrl; |
| 108 | GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); |
| 109 | if ((LogicalId.Revision & AMD_F14_ON_Cx) != 0) { |
| 110 | NbClkGatingCtrlPtr->Smu_Sclk_Gating = FALSE; |
| 111 | } |
| 112 | } |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 113 | |
| 114 | /*----------------------------------------------------------------------------------------*/ |
| 115 | /** |
| 116 | * UnitID Clumping |
| 117 | * |
| 118 | * |
| 119 | * @param[in] NbPciAddress |
| 120 | * @param[in] StdHeader |
| 121 | * @retval AGESA_STATUS |
| 122 | */ |
| 123 | |
| 124 | VOID |
| 125 | NbFmClumpUnitID ( |
| 126 | IN PCI_ADDR NbPciAddress, |
| 127 | IN AMD_CONFIG_PARAMS *StdHeader |
| 128 | ) |
| 129 | { |
| 130 | return; |
| 131 | } |
| 132 | |
| 133 | /*----------------------------------------------------------------------------------------*/ |
| 134 | /** |
| 135 | * Get Fuse translation table |
| 136 | * |
| 137 | * |
| 138 | * @retval pointer to fuse translation table |
| 139 | */ |
| 140 | |
| 141 | FUSE_TABLE* |
| 142 | NbFmGetFuseTranslationTable ( |
Frank Vibrans | ccad951 | 2011-05-05 16:49:11 +0000 | [diff] [blame] | 143 | VOID |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 144 | ) |
| 145 | { |
| 146 | return &FuseTable; |
| 147 | } |
| 148 | |
| 149 | /*----------------------------------------------------------------------------------------*/ |
| 150 | /** |
| 151 | * Family specific fuse table patch |
| 152 | * Is's correct behavior if we would have 4 states, it would be |
| 153 | * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 5 |
| 154 | * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 6 |
| 155 | * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 7 |
| 156 | * If we would have 4 states it would be |
| 157 | * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 4 |
| 158 | * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 5 |
| 159 | * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 6 |
| 160 | * PP_FUSE_ARRAY->LclkDpmDid[3] - Goes to State 7 |
| 161 | * |
| 162 | * @param[in] PpFuseArray Pointer to PP_FUSE_ARRAY |
| 163 | * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS |
| 164 | */ |
| 165 | VOID |
| 166 | NbFmFuseAdjustFuseTablePatch ( |
| 167 | IN OUT PP_FUSE_ARRAY *PpFuseArray, |
| 168 | IN AMD_CONFIG_PARAMS *StdHeader |
| 169 | ) |
| 170 | { |
| 171 | UINT8 LclkDpmMode; |
| 172 | UINT8 SwSatateIndex; |
| 173 | UINT8 MaxSclkIndex; |
| 174 | UINT8 DpmStateIndex; |
| 175 | UINT8 CurrentSclkDpmDid; |
| 176 | CPU_LOGICAL_ID LogicalId; |
| 177 | |
| 178 | LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; |
| 179 | GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); |
| 180 | if ((LogicalId.Revision & (AMD_F14_ON_A0 | AMD_F14_ON_A1)) != 0) { |
| 181 | LclkDpmMode = LclkDpmDisabled; |
| 182 | } |
| 183 | IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); |
| 184 | |
| 185 | //For all CPU rev LclkDpmValid[3] = 0 |
| 186 | PpFuseArray->LclkDpmValid[3] = 0; |
| 187 | PpFuseArray->LclkDpmVid[3] = 0; |
| 188 | PpFuseArray->LclkDpmDid[3] = 0; |
| 189 | |
| 190 | // For LCLKDPM set LclkDpmVid[0] = 0, no matter if LCLK DMP enable or disable. |
| 191 | PpFuseArray->LclkDpmVid[0] = 0; |
| 192 | |
| 193 | if (LclkDpmMode != LclkDpmRcActivity) { |
| 194 | //If LCLK DPM disable (LclkDpmMode != LclkDpmRcActivity) |
| 195 | // - LclkDpmDid[1,2] = LclkDpmDid [0], LclkDpmVid[1,2] = LclkDpmVid[0] |
| 196 | // - Execute LCLK DPM init |
| 197 | |
| 198 | PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0]; |
| 199 | PpFuseArray->LclkDpmVid[2] = PpFuseArray->LclkDpmVid[0]; |
| 200 | PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0]; |
| 201 | PpFuseArray->LclkDpmDid[2] = PpFuseArray->LclkDpmDid[0]; |
| 202 | IDS_HDT_CONSOLE (NB_MISC, " F14 LCLK DPM Mode Disable -- use DPM0 fusing\n"); |
| 203 | |
| 204 | } else { |
| 205 | // If LCLK DPM enabled |
| 206 | // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage |
| 207 | // - Execute LCLK DPM init |
| 208 | PpFuseArray->LclkDpmVid[2] = PpFuseArray->PcieGen2Vid; |
| 209 | if (GfxLibIsControllerPresent (StdHeader)) { |
| 210 | //VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0). |
| 211 | for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) { |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 212 | if (PpFuseArray->PolicyLabel[SwSatateIndex] == POLICY_LABEL_PERFORMANCE) { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 213 | break; |
| 214 | } |
| 215 | } |
| 216 | MaxSclkIndex = 0; |
| 217 | CurrentSclkDpmDid = 0xff; |
| 218 | ASSERT (PpFuseArray->SclkDpmValid[SwSatateIndex] != 0); |
| 219 | for (DpmStateIndex = 0; DpmStateIndex < PP_FUSE_MAX_NUM_DPM_STATE; DpmStateIndex++) { |
| 220 | if ((PpFuseArray->SclkDpmValid[SwSatateIndex] & (1 << DpmStateIndex)) != 0) { |
| 221 | if (PpFuseArray->SclkDpmDid[DpmStateIndex] < CurrentSclkDpmDid) { |
| 222 | CurrentSclkDpmDid = PpFuseArray->SclkDpmDid[DpmStateIndex]; |
| 223 | MaxSclkIndex = DpmStateIndex; |
| 224 | } |
| 225 | } |
| 226 | } |
| 227 | PpFuseArray->LclkDpmVid[1] = PpFuseArray->SclkDpmVid[MaxSclkIndex]; |
| 228 | } else { |
| 229 | PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0]; |
| 230 | PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0]; |
| 231 | } |
| 232 | // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage |
| 233 | //Keep using actual fusing |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 234 | IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actual fusing.\n"); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 235 | } |
| 236 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 237 | //Patch SclkThermDid to 175Mhz if not fused |
| 238 | if (PpFuseArray->SclkThermDid == 0) { |
| 239 | PpFuseArray->SclkThermDid = GfxLibCalculateDid (175 * 100, GfxLibGetMainPllFreq (StdHeader) * 100); |
| 240 | } |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | |
| 244 | /*---------------------------------------------------------------------------------------- |
| 245 | * FUSE translation table |
| 246 | *---------------------------------------------------------------------------------------- |
| 247 | */ |
| 248 | |
| 249 | FUSE_REGISTER_ENTRY FCRxFE00_600E_TABLE [] = { |
| 250 | { |
| 251 | FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET, |
| 252 | FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH, |
| 253 | (UINT8) offsetof (PP_FUSE_ARRAY, MainPllId) |
| 254 | }, |
| 255 | { |
| 256 | FCRxFE00_600E_WrCkDid_OFFSET, |
| 257 | FCRxFE00_600E_WrCkDid_WIDTH, |
| 258 | (UINT8) offsetof (PP_FUSE_ARRAY, WrCkDid) |
| 259 | } |
| 260 | }; |
| 261 | |
| 262 | FUSE_REGISTER_ENTRY FCRxFE00_70A2_TABLE [] = { |
| 263 | { |
| 264 | FCRxFE00_70A2_PPlayTableRev_OFFSET, |
| 265 | FCRxFE00_70A2_PPlayTableRev_WIDTH, |
| 266 | (UINT8) offsetof (PP_FUSE_ARRAY, PPlayTableRev) |
| 267 | }, |
| 268 | { |
| 269 | FCRxFE00_70A2_SclkThermDid_OFFSET, |
| 270 | FCRxFE00_70A2_SclkThermDid_WIDTH, |
| 271 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkThermDid) |
| 272 | }, |
| 273 | { |
| 274 | FCRxFE00_70A2_PcieGen2Vid_OFFSET, |
| 275 | FCRxFE00_70A2_PcieGen2Vid_WIDTH, |
| 276 | (UINT8) offsetof (PP_FUSE_ARRAY, PcieGen2Vid) |
| 277 | } |
| 278 | }; |
| 279 | |
| 280 | FUSE_REGISTER_ENTRY FCRxFE00_70A4_TABLE [] = { |
| 281 | { |
| 282 | FCRxFE00_70A4_SclkDpmVid0_OFFSET, |
| 283 | FCRxFE00_70A4_SclkDpmVid0_WIDTH, |
| 284 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0]) |
| 285 | }, |
| 286 | { |
| 287 | FCRxFE00_70A4_SclkDpmVid1_OFFSET, |
| 288 | FCRxFE00_70A4_SclkDpmVid1_WIDTH, |
| 289 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1]) |
| 290 | }, |
| 291 | { |
| 292 | FCRxFE00_70A4_SclkDpmVid2_OFFSET, |
| 293 | FCRxFE00_70A4_SclkDpmVid2_WIDTH, |
| 294 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2]) |
| 295 | }, |
| 296 | { |
| 297 | FCRxFE00_70A4_SclkDpmVid3_OFFSET, |
| 298 | FCRxFE00_70A4_SclkDpmVid3_WIDTH, |
| 299 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3]) |
| 300 | }, |
| 301 | { |
| 302 | FCRxFE00_70A4_SclkDpmVid4_OFFSET, |
| 303 | FCRxFE00_70A4_SclkDpmVid4_WIDTH, |
| 304 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4]) |
| 305 | }, |
| 306 | }; |
| 307 | |
| 308 | FUSE_REGISTER_ENTRY FCRxFE00_70A5_TABLE [] = { |
| 309 | { |
| 310 | FCRxFE00_70A5_SclkDpmDid0_OFFSET, |
| 311 | FCRxFE00_70A5_SclkDpmDid0_WIDTH, |
| 312 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0]) |
| 313 | }, |
| 314 | { |
| 315 | FCRxFE00_70A5_SclkDpmDid1_OFFSET, |
| 316 | FCRxFE00_70A5_SclkDpmDid1_WIDTH, |
| 317 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1]) |
| 318 | }, |
| 319 | { |
| 320 | FCRxFE00_70A5_SclkDpmDid2_OFFSET, |
| 321 | FCRxFE00_70A5_SclkDpmDid2_WIDTH, |
| 322 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2]) |
| 323 | } |
| 324 | }; |
| 325 | |
| 326 | FUSE_REGISTER_ENTRY FCRxFE00_70A8_TABLE [] = { |
| 327 | { |
| 328 | FCRxFE00_70A8_SclkDpmDid3_OFFSET, |
| 329 | FCRxFE00_70A8_SclkDpmDid3_WIDTH, |
| 330 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3]) |
| 331 | }, |
| 332 | { |
| 333 | FCRxFE00_70A8_SclkDpmDid4_OFFSET, |
| 334 | FCRxFE00_70A8_SclkDpmDid4_WIDTH, |
| 335 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4]) |
| 336 | } |
| 337 | }; |
| 338 | |
| 339 | FUSE_REGISTER_ENTRY FCRxFE00_70AA_TABLE [] = { |
| 340 | { |
| 341 | FCRxFE00_70AA_SclkDpmCacBase_OFFSET, |
| 342 | FCRxFE00_70AA_SclkDpmCacBase_WIDTH, |
| 343 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmCac[4]) |
| 344 | } |
| 345 | }; |
| 346 | |
| 347 | |
| 348 | FUSE_REGISTER_ENTRY FCRxFE00_70AE_TABLE [] = { |
| 349 | { |
| 350 | FCRxFE00_70AE_DispClkDid0_OFFSET, |
| 351 | FCRxFE00_70AE_DispClkDid0_WIDTH, |
| 352 | (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[0]) |
| 353 | }, |
| 354 | { |
| 355 | FCRxFE00_70AE_DispClkDid1_OFFSET, |
| 356 | FCRxFE00_70AE_DispClkDid1_WIDTH, |
| 357 | (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[1]) |
| 358 | }, |
| 359 | { |
| 360 | FCRxFE00_70AE_DispClkDid2_OFFSET, |
| 361 | FCRxFE00_70AE_DispClkDid2_WIDTH, |
| 362 | (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[2]) |
| 363 | }, |
| 364 | { |
| 365 | FCRxFE00_70AE_DispClkDid3_OFFSET, |
| 366 | FCRxFE00_70AE_DispClkDid3_WIDTH, |
| 367 | (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[3]) |
| 368 | } |
| 369 | }; |
| 370 | |
| 371 | FUSE_REGISTER_ENTRY FCRxFE00_70B1_TABLE [] = { |
| 372 | { |
| 373 | FCRxFE00_70B1_LclkDpmDid0_OFFSET, |
| 374 | FCRxFE00_70B1_LclkDpmDid0_WIDTH, |
| 375 | (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0]) |
| 376 | }, |
| 377 | { |
| 378 | FCRxFE00_70B1_LclkDpmDid1_OFFSET, |
| 379 | FCRxFE00_70B1_LclkDpmDid1_WIDTH, |
| 380 | (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1]) |
| 381 | }, |
| 382 | { |
| 383 | FCRxFE00_70B1_LclkDpmDid2_OFFSET, |
| 384 | FCRxFE00_70B1_LclkDpmDid2_WIDTH, |
| 385 | (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2]) |
| 386 | } |
| 387 | }; |
| 388 | |
| 389 | FUSE_REGISTER_ENTRY FCRxFE00_70B4_TABLE [] = { |
| 390 | { |
| 391 | FCRxFE00_70B4_LclkDpmDid3_OFFSET, |
| 392 | FCRxFE00_70B4_LclkDpmDid3_WIDTH, |
| 393 | (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3]) |
| 394 | }, |
| 395 | { |
| 396 | FCRxFE00_70B4_LclkDpmValid0_OFFSET, |
| 397 | FCRxFE00_70B4_LclkDpmValid0_WIDTH, |
| 398 | (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0]) |
| 399 | }, |
| 400 | { |
| 401 | FCRxFE00_70B4_LclkDpmValid1_OFFSET, |
| 402 | FCRxFE00_70B4_LclkDpmValid1_WIDTH, |
| 403 | (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1]) |
| 404 | }, |
| 405 | { |
| 406 | FCRxFE00_70B4_LclkDpmValid2_OFFSET, |
| 407 | FCRxFE00_70B4_LclkDpmValid2_WIDTH, |
| 408 | (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2]) |
| 409 | }, |
| 410 | { |
| 411 | FCRxFE00_70B4_LclkDpmValid3_OFFSET, |
| 412 | FCRxFE00_70B4_LclkDpmValid3_WIDTH, |
| 413 | (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3]) |
| 414 | } |
| 415 | }; |
| 416 | |
| 417 | FUSE_REGISTER_ENTRY FCRxFE00_70B5_TABLE [] = { |
| 418 | { |
| 419 | FCRxFE00_70B5_DclkDid0_OFFSET, |
| 420 | FCRxFE00_70B5_DclkDid0_WIDTH, |
| 421 | (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[0]) |
| 422 | }, |
| 423 | { |
| 424 | FCRxFE00_70B5_DclkDid1_OFFSET, |
| 425 | FCRxFE00_70B5_DclkDid1_WIDTH, |
| 426 | (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[1]) |
| 427 | }, |
| 428 | { |
| 429 | FCRxFE00_70B5_DclkDid2_OFFSET, |
| 430 | FCRxFE00_70B5_DclkDid2_WIDTH, |
| 431 | (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[2]) |
| 432 | } |
| 433 | }; |
| 434 | |
| 435 | FUSE_REGISTER_ENTRY FCRxFE00_70B8_TABLE [] = { |
| 436 | { |
| 437 | FCRxFE00_70B8_DclkDid3_OFFSET, |
| 438 | FCRxFE00_70B8_DclkDid3_WIDTH, |
| 439 | (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[3]) |
| 440 | } |
| 441 | }; |
| 442 | |
| 443 | FUSE_REGISTER_ENTRY FCRxFE00_70B9_TABLE [] = { |
| 444 | { |
| 445 | FCRxFE00_70B9_VclkDid0_OFFSET, |
| 446 | FCRxFE00_70B9_VclkDid0_WIDTH, |
| 447 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[0]) |
| 448 | }, |
| 449 | { |
| 450 | FCRxFE00_70B9_VclkDid1_OFFSET, |
| 451 | FCRxFE00_70B9_VclkDid1_WIDTH, |
| 452 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[1]) |
| 453 | }, |
| 454 | { |
| 455 | FCRxFE00_70B9_VclkDid2_OFFSET, |
| 456 | FCRxFE00_70B9_VclkDid2_WIDTH, |
| 457 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[2]) |
| 458 | }, |
| 459 | { |
| 460 | FCRxFE00_70B9_VclkDid3_OFFSET, |
| 461 | FCRxFE00_70B9_VclkDid3_WIDTH, |
| 462 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[3]) |
| 463 | } |
| 464 | }; |
| 465 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 466 | FUSE_REGISTER_ENTRY FCRxFE00_70BC_TABLE [] = { |
| 467 | { |
| 468 | FCRxFE00_70BC_SclkDpmValid0_OFFSET, |
| 469 | FCRxFE00_70BC_SclkDpmValid0_WIDTH, |
| 470 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0]) |
| 471 | }, |
| 472 | { |
| 473 | FCRxFE00_70BC_SclkDpmValid1_OFFSET, |
| 474 | FCRxFE00_70BC_SclkDpmValid1_WIDTH, |
| 475 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1]) |
| 476 | }, |
| 477 | { |
| 478 | FCRxFE00_70BC_SclkDpmValid2_OFFSET, |
| 479 | FCRxFE00_70BC_SclkDpmValid2_WIDTH, |
| 480 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2]) |
| 481 | }, |
| 482 | { |
| 483 | FCRxFE00_70BC_SclkDpmValid3_OFFSET, |
| 484 | FCRxFE00_70BC_SclkDpmValid3_WIDTH, |
| 485 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3]) |
| 486 | }, |
| 487 | { |
| 488 | FCRxFE00_70BC_SclkDpmValid4_OFFSET, |
| 489 | FCRxFE00_70BC_SclkDpmValid4_WIDTH, |
| 490 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4]) |
| 491 | } |
| 492 | }; |
| 493 | |
| 494 | FUSE_REGISTER_ENTRY FCRxFE00_70BF_TABLE [] = { |
| 495 | { |
| 496 | FCRxFE00_70BF_SclkDpmValid5_OFFSET, |
| 497 | FCRxFE00_70BF_SclkDpmValid5_WIDTH, |
| 498 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5]) |
| 499 | } |
| 500 | }; |
| 501 | |
| 502 | FUSE_REGISTER_ENTRY FCRxFE00_70C0_TABLE [] = { |
| 503 | { |
| 504 | FCRxFE00_70C0_PolicyLabel0_OFFSET, |
| 505 | FCRxFE00_70C0_PolicyLabel0_WIDTH, |
| 506 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[0]) |
| 507 | }, |
| 508 | { |
| 509 | FCRxFE00_70C0_PolicyLabel1_OFFSET, |
| 510 | FCRxFE00_70C0_PolicyLabel1_WIDTH, |
| 511 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[1]) |
| 512 | }, |
| 513 | { |
| 514 | FCRxFE00_70C0_PolicyLabel2_OFFSET, |
| 515 | FCRxFE00_70C0_PolicyLabel2_WIDTH, |
| 516 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[2]) |
| 517 | }, |
| 518 | { |
| 519 | FCRxFE00_70C0_PolicyLabel3_OFFSET, |
| 520 | FCRxFE00_70C0_PolicyLabel3_WIDTH, |
| 521 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[3]) |
| 522 | }, |
| 523 | { |
| 524 | FCRxFE00_70C0_PolicyLabel4_OFFSET, |
| 525 | FCRxFE00_70C0_PolicyLabel4_WIDTH, |
| 526 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[4]) |
| 527 | }, |
| 528 | { |
| 529 | FCRxFE00_70C0_PolicyLabel5_OFFSET, |
| 530 | FCRxFE00_70C0_PolicyLabel5_WIDTH, |
| 531 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[5]) |
| 532 | } |
| 533 | }; |
| 534 | |
| 535 | FUSE_REGISTER_ENTRY FCRxFE00_70C1_TABLE [] = { |
| 536 | { |
| 537 | FCRxFE00_70C1_PolicyFlags0_OFFSET, |
| 538 | FCRxFE00_70C1_PolicyFlags0_WIDTH, |
| 539 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[0]) |
| 540 | }, |
| 541 | { |
| 542 | FCRxFE00_70C1_PolicyFlags1_OFFSET, |
| 543 | FCRxFE00_70C1_PolicyFlags1_WIDTH, |
| 544 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[1]) |
| 545 | }, |
| 546 | { |
| 547 | FCRxFE00_70C1_PolicyFlags2_OFFSET, |
| 548 | FCRxFE00_70C1_PolicyFlags2_WIDTH, |
| 549 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[2]) |
| 550 | } |
| 551 | }; |
| 552 | |
| 553 | FUSE_REGISTER_ENTRY FCRxFE00_70C4_TABLE [] = { |
| 554 | { |
| 555 | FCRxFE00_70C4_PolicyFlags3_OFFSET, |
| 556 | FCRxFE00_70C4_PolicyFlags3_WIDTH, |
| 557 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[3]) |
| 558 | }, |
| 559 | { |
| 560 | FCRxFE00_70C4_PolicyFlags4_OFFSET, |
| 561 | FCRxFE00_70C4_PolicyFlags4_WIDTH, |
| 562 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[4]) |
| 563 | }, |
| 564 | { |
| 565 | FCRxFE00_70C4_PolicyFlags5_OFFSET, |
| 566 | FCRxFE00_70C4_PolicyFlags5_WIDTH, |
| 567 | (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[5]) |
| 568 | } |
| 569 | }; |
| 570 | |
| 571 | |
| 572 | FUSE_REGISTER_ENTRY FCRxFE00_70C7_TABLE [] = { |
| 573 | { |
| 574 | FCRxFE00_70C7_DclkVclkSel0_OFFSET, |
| 575 | FCRxFE00_70C7_DclkVclkSel0_WIDTH, |
| 576 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0]) |
| 577 | }, |
| 578 | { |
| 579 | FCRxFE00_70C7_DclkVclkSel1_OFFSET, |
| 580 | FCRxFE00_70C7_DclkVclkSel1_WIDTH, |
| 581 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1]) |
| 582 | }, |
| 583 | { |
| 584 | FCRxFE00_70C7_DclkVclkSel2_OFFSET, |
| 585 | FCRxFE00_70C7_DclkVclkSel2_WIDTH, |
| 586 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2]) |
| 587 | }, |
| 588 | { |
| 589 | FCRxFE00_70C7_DclkVclkSel3_OFFSET, |
| 590 | FCRxFE00_70C7_DclkVclkSel3_WIDTH, |
| 591 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3]) |
| 592 | }, |
| 593 | |
| 594 | { |
| 595 | FCRxFE00_70C7_DclkVclkSel4_OFFSET, |
| 596 | FCRxFE00_70C7_DclkVclkSel4_WIDTH, |
| 597 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4]) |
| 598 | }, |
| 599 | { |
| 600 | FCRxFE00_70C7_DclkVclkSel5_OFFSET, |
| 601 | FCRxFE00_70C7_DclkVclkSel5_WIDTH, |
| 602 | (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5]) |
| 603 | }, |
| 604 | }; |
| 605 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 606 | FUSE_REGISTER_ENTRY FCRxFE00_70C8_TABLE [] = { |
| 607 | { |
| 608 | FCRxFE00_70C8_GpuBoostCap_OFFSET, |
| 609 | FCRxFE00_70C8_GpuBoostCap_WIDTH, |
| 610 | (UINT8) offsetof (PP_FUSE_ARRAY, GpuBoostCap) |
| 611 | }, |
| 612 | { |
| 613 | FCRxFE00_70C8_SclkDpmVid5_OFFSET, |
| 614 | FCRxFE00_70C8_SclkDpmVid5_WIDTH, |
| 615 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[5]) |
| 616 | }, |
| 617 | { |
| 618 | FCRxFE00_70C8_SclkDpmDid5_OFFSET, |
| 619 | FCRxFE00_70C8_SclkDpmDid5_WIDTH, |
| 620 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[5]) |
| 621 | }, |
| 622 | }; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 623 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 624 | FUSE_REGISTER_ENTRY FCRxFE00_70C9_TABLE [] = { |
| 625 | { |
| 626 | FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET, |
| 627 | FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH, |
| 628 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[0]) |
| 629 | }, |
| 630 | { |
| 631 | FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET, |
| 632 | FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH, |
| 633 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[1]) |
| 634 | } |
| 635 | }; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 636 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 637 | FUSE_REGISTER_ENTRY FCRxFE00_70CC_TABLE [] = { |
| 638 | { |
| 639 | FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET, |
| 640 | FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH, |
| 641 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[2]) |
| 642 | }, |
| 643 | { |
| 644 | FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET, |
| 645 | FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH, |
| 646 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[3]) |
| 647 | } |
| 648 | }; |
| 649 | |
| 650 | FUSE_REGISTER_ENTRY FCRxFE00_70CF_TABLE [] = { |
| 651 | { |
| 652 | FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET, |
| 653 | FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH, |
| 654 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[4]) |
| 655 | }, |
| 656 | { |
| 657 | FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET, |
| 658 | FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH, |
| 659 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[5]) |
| 660 | } |
| 661 | }; |
| 662 | |
| 663 | FUSE_REGISTER_ENTRY FCRxFE00_70D2_TABLE [] = { |
| 664 | { |
| 665 | FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET, |
| 666 | FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH, |
| 667 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimitPG) |
| 668 | } |
| 669 | }; |
| 670 | |
| 671 | FUSE_REGISTER_ENTRY FCRxFE00_70D4_TABLE [] = { |
| 672 | { |
| 673 | FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET, |
| 674 | FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH, |
| 675 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmBoostMargin) |
| 676 | } |
| 677 | }; |
| 678 | |
| 679 | FUSE_REGISTER_ENTRY FCRxFE00_70D7_TABLE [] = { |
| 680 | { |
| 681 | FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET, |
| 682 | FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH, |
| 683 | (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmThrottleMargin) |
| 684 | } |
| 685 | }; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 686 | |
| 687 | FUSE_TABLE_ENTRY FuseRegisterTable [] = { |
| 688 | { |
| 689 | FCRxFE00_70A2_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 690 | ARRAY_SIZE(FCRxFE00_70A2_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 691 | FCRxFE00_70A2_TABLE |
| 692 | }, |
| 693 | { |
| 694 | FCRxFE00_70A4_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 695 | ARRAY_SIZE(FCRxFE00_70A4_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 696 | FCRxFE00_70A4_TABLE |
| 697 | }, |
| 698 | { |
| 699 | FCRxFE00_70A5_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 700 | ARRAY_SIZE(FCRxFE00_70A5_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 701 | FCRxFE00_70A5_TABLE |
| 702 | }, |
| 703 | { |
| 704 | FCRxFE00_70A8_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 705 | ARRAY_SIZE(FCRxFE00_70A8_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 706 | FCRxFE00_70A8_TABLE |
| 707 | }, |
| 708 | { |
| 709 | FCRxFE00_600E_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 710 | ARRAY_SIZE(FCRxFE00_600E_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 711 | FCRxFE00_600E_TABLE |
| 712 | }, |
| 713 | { |
| 714 | FCRxFE00_70AA_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 715 | ARRAY_SIZE(FCRxFE00_70AA_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 716 | FCRxFE00_70AA_TABLE |
| 717 | }, |
| 718 | { |
| 719 | FCRxFE00_70AE_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 720 | ARRAY_SIZE(FCRxFE00_70AE_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 721 | FCRxFE00_70AE_TABLE |
| 722 | }, |
| 723 | { |
| 724 | FCRxFE00_70B1_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 725 | ARRAY_SIZE(FCRxFE00_70B1_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 726 | FCRxFE00_70B1_TABLE |
| 727 | }, |
| 728 | { |
| 729 | FCRxFE00_70B4_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 730 | ARRAY_SIZE(FCRxFE00_70B4_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 731 | FCRxFE00_70B4_TABLE |
| 732 | }, |
| 733 | { |
| 734 | FCRxFE00_70B5_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 735 | ARRAY_SIZE(FCRxFE00_70B5_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 736 | FCRxFE00_70B5_TABLE |
| 737 | }, |
| 738 | { |
| 739 | FCRxFE00_70B8_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 740 | ARRAY_SIZE(FCRxFE00_70B8_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 741 | FCRxFE00_70B8_TABLE |
| 742 | }, |
| 743 | { |
| 744 | FCRxFE00_70B9_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 745 | ARRAY_SIZE(FCRxFE00_70B9_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 746 | FCRxFE00_70B9_TABLE |
| 747 | }, |
| 748 | { |
| 749 | FCRxFE00_70BC_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 750 | ARRAY_SIZE(FCRxFE00_70BC_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 751 | FCRxFE00_70BC_TABLE |
| 752 | }, |
| 753 | { |
| 754 | FCRxFE00_70BF_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 755 | ARRAY_SIZE(FCRxFE00_70BF_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 756 | FCRxFE00_70BF_TABLE |
| 757 | }, |
| 758 | { |
| 759 | FCRxFE00_70C0_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 760 | ARRAY_SIZE(FCRxFE00_70C0_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 761 | FCRxFE00_70C0_TABLE |
| 762 | }, |
| 763 | { |
| 764 | FCRxFE00_70C1_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 765 | ARRAY_SIZE(FCRxFE00_70C1_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 766 | FCRxFE00_70C1_TABLE |
| 767 | }, |
| 768 | { |
| 769 | FCRxFE00_70C4_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 770 | ARRAY_SIZE(FCRxFE00_70C4_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 771 | FCRxFE00_70C4_TABLE |
| 772 | }, |
| 773 | { |
| 774 | FCRxFE00_70C7_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 775 | ARRAY_SIZE(FCRxFE00_70C7_TABLE), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 776 | FCRxFE00_70C7_TABLE |
| 777 | }, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 778 | { |
| 779 | FCRxFE00_70C8_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 780 | ARRAY_SIZE(FCRxFE00_70C8_TABLE), |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 781 | FCRxFE00_70C8_TABLE |
| 782 | }, |
| 783 | { |
| 784 | FCRxFE00_70C9_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 785 | ARRAY_SIZE(FCRxFE00_70C9_TABLE), |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 786 | FCRxFE00_70C9_TABLE |
| 787 | }, |
| 788 | { |
| 789 | FCRxFE00_70CC_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 790 | ARRAY_SIZE(FCRxFE00_70CC_TABLE), |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 791 | FCRxFE00_70CC_TABLE |
| 792 | }, |
| 793 | { |
| 794 | FCRxFE00_70CF_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 795 | ARRAY_SIZE(FCRxFE00_70CF_TABLE), |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 796 | FCRxFE00_70CF_TABLE |
| 797 | }, |
| 798 | { |
| 799 | FCRxFE00_70D2_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 800 | ARRAY_SIZE(FCRxFE00_70D2_TABLE), |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 801 | FCRxFE00_70D2_TABLE |
| 802 | }, |
| 803 | { |
| 804 | FCRxFE00_70D4_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 805 | ARRAY_SIZE(FCRxFE00_70D4_TABLE), |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 806 | FCRxFE00_70D4_TABLE |
| 807 | }, |
| 808 | { |
| 809 | FCRxFE00_70D7_ADDRESS, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 810 | ARRAY_SIZE(FCRxFE00_70D7_TABLE), |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 811 | FCRxFE00_70D7_TABLE |
| 812 | }, |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 813 | }; |
| 814 | |
| 815 | FUSE_TABLE FuseTable = { |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 816 | ARRAY_SIZE(FuseRegisterTable), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 817 | FuseRegisterTable |
| 818 | }; |