Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /** |
| 2 | * @file |
| 3 | * |
| 4 | * ALIB PSPP Pcie Smu Lib V1 |
| 5 | * |
| 6 | * |
| 7 | * |
| 8 | * @xrefitem bom "File Content Label" "Release Content" |
| 9 | * @e project: AGESA |
| 10 | * @e sub-project: GNB |
| 11 | * @e \$Revision: 25430 $ @e \$Date: 2010-01-18 22:25:55 -0800 (Mon, 18 Jan 2010) $ |
| 12 | * |
| 13 | */ |
| 14 | /* |
| 15 | ***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
Peter Lemenkov | 7bbe3bb | 2018-12-07 11:23:21 +0100 | [diff] [blame] | 19 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
Peter Lemenkov | 7bbe3bb | 2018-12-07 11:23:21 +0100 | [diff] [blame] | 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 29 | * from this software without specific prior written permission. |
Peter Lemenkov | 7bbe3bb | 2018-12-07 11:23:21 +0100 | [diff] [blame] | 30 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Peter Lemenkov | 7bbe3bb | 2018-12-07 11:23:21 +0100 | [diff] [blame] | 41 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | /*----------------------------------------------------------------------------------------*/ |
| 46 | /** |
| 47 | * SMU indirect register read |
| 48 | * |
| 49 | * Arg0 - Smu register offset |
| 50 | * |
| 51 | */ |
| 52 | Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) { |
| 53 | Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) |
| 54 | // Access 32 bit width |
| 55 | Increment (Arg0) |
| 56 | // Reverse ReqToggle |
| 57 | Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) |
| 58 | // Assign Address and ReqType = 0 |
| 59 | Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0) |
| 60 | |
| 61 | procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) |
| 62 | |
| 63 | Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0) |
| 64 | return (Local0) |
| 65 | } |
| 66 | |
| 67 | /*----------------------------------------------------------------------------------------*/ |
| 68 | /** |
| 69 | * SMU indirect register Write |
| 70 | * |
| 71 | * Arg0 - Smu register offset |
| 72 | * Arg1 - Value |
| 73 | * Arg2 - Width, 0 = 16, 1 = 32 |
| 74 | * |
| 75 | */ |
| 76 | Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) { |
| 77 | Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) |
| 78 | // Get low 16 bit value |
| 79 | Store (And (Arg1, 0xFFFF), Local1) |
| 80 | // Reverse ReqToggle |
| 81 | Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) |
| 82 | // Assign Address |
| 83 | Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0) |
| 84 | // ReqType = 1 |
| 85 | Or (Local0, 0x02000000, Local0) |
| 86 | // Assign Low 16 bit value |
| 87 | Or (Local0, Local1, Local0) |
| 88 | |
| 89 | procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) |
| 90 | |
| 91 | if (LEqual (Arg2, 1)) { |
| 92 | // Get high 16 bit value |
| 93 | Store (ShiftRight (Arg1, 16), Local1) |
| 94 | // Reverse ReqToggle |
| 95 | Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) |
| 96 | // Assign Address |
| 97 | Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0) |
| 98 | // Assign High 16 bit value |
| 99 | Or (Local0, Local1, Local0) |
| 100 | |
| 101 | procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) |
| 102 | } |
| 103 | |
| 104 | } |
| 105 | |
| 106 | /*----------------------------------------------------------------------------------------*/ |
| 107 | /** |
| 108 | * SMU Service request |
| 109 | * |
| 110 | * Arg0 - Smu service id |
| 111 | * Arg1 - Flags - Poll Ack = 1, Poll down = 2 |
| 112 | * |
| 113 | */ |
| 114 | Method (procNbSmuServiceRequest, 2, NotSerialized) { |
| 115 | Store ("NbSmuServiceRequest Enter", Debug) |
| 116 | Store ("Request id =", Debug) |
| 117 | Store (Arg0, Debug) |
| 118 | |
| 119 | Or (ShiftLeft (Arg0, 3), 0x1, Local0) |
| 120 | procNbSmuIndirectRegisterWrite (0x3, Local0, 1) |
Peter Lemenkov | 7bbe3bb | 2018-12-07 11:23:21 +0100 | [diff] [blame] | 121 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 122 | if (LAnd (Arg1, 1)) { |
| 123 | while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) { |
| 124 | Store ("--Wait Ack--", Debug) |
| 125 | } |
| 126 | } |
| 127 | if (LAnd (Arg1, 2)) { |
| 128 | while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) { |
| 129 | Store ("--Wait Done--", Debug) |
| 130 | } |
| 131 | } |
| 132 | // Clear IRQ register |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 133 | procNbSmuIndirectRegisterWrite (0x3, 0, 1) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 134 | Store ("NbSmuServiceRequest Exit", Debug) |
| 135 | } |
| 136 | |
| 137 | /*----------------------------------------------------------------------------------------*/ |
| 138 | /** |
| 139 | * Write RCU register |
| 140 | * |
| 141 | * Arg0 - Register Address |
| 142 | * Arg1 - Register Data |
| 143 | * |
| 144 | */ |
| 145 | Method (procSmuRcuWrite, 2, NotSerialized) { |
| 146 | procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) |
| 147 | procNbSmuIndirectRegisterWrite (0x5, Arg1, 1) |
| 148 | |
| 149 | } |
| 150 | |
| 151 | /*----------------------------------------------------------------------------------------*/ |
| 152 | /** |
| 153 | * Read RCU register |
| 154 | * |
| 155 | * Arg0 - Register Address |
| 156 | * Retval - RCU register value |
| 157 | */ |
| 158 | Method (procSmuRcuRead, 1, NotSerialized) { |
| 159 | procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) |
| 160 | Store (procNbSmuIndirectRegisterRead (0x5), Local0) |
| 161 | return (Local0) |
| 162 | } |
| 163 | |
| 164 | /*----------------------------------------------------------------------------------------*/ |
| 165 | /** |
| 166 | * SMU SRBM Register Read |
| 167 | * |
| 168 | * Arg0 - FCR register address |
| 169 | * |
| 170 | */ |
| 171 | Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) { |
| 172 | //SMUx0B_x8600 |
| 173 | Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) |
| 174 | //SMUx0B_x8604 |
| 175 | Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) |
| 176 | //SMUx0B_x8608 |
| 177 | Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) |
| 178 | //Write SMU RCU |
| 179 | procSmuRcuWrite (0x8600, Local0) |
| 180 | procSmuRcuWrite (0x8604, Local1) |
| 181 | procSmuRcuWrite (0x8608, Local2) |
| 182 | // ServiceId |
| 183 | if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) { |
| 184 | procNbSmuServiceRequest (0xD, 0x3) |
| 185 | } |
| 186 | if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) { |
| 187 | procNbSmuServiceRequest (0xB, 0x3) |
| 188 | } |
| 189 | return (procSmuRcuRead(0x8650)) |
| 190 | } |
| 191 | |
| 192 | |
| 193 | /*----------------------------------------------------------------------------------------*/ |
| 194 | /** |
| 195 | * SMU SRBM Register Write |
| 196 | * |
| 197 | * Arg0 - FCR register address |
| 198 | * Arg1 - Value |
| 199 | * |
| 200 | */ |
| 201 | Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) { |
| 202 | //SMUx0B_x8600 |
| 203 | Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) |
| 204 | //SMUx0B_x8604 |
| 205 | Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) |
| 206 | //SMUx0B_x8608 |
| 207 | Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) |
| 208 | Or (Local2, ShiftLeft (1, 16), Local2) |
| 209 | //Write SMU RCU |
| 210 | procSmuRcuWrite (0x8600, Local0) |
| 211 | procSmuRcuWrite (0x8604, Local1) |
| 212 | procSmuRcuWrite (0x8608, Local2) |
| 213 | //Write Data |
| 214 | procSmuRcuWrite (0x8650, Arg1) |
| 215 | // ServiceId |
| 216 | procNbSmuServiceRequest (0xB, 0x3) |
| 217 | } |