Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Family specific PCIe complex initialization services |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 34930 $ @e \$Date: 2010-07-14 02:57:05 -0700 (Wed, 14 Jul 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | 1542a6f | 2014-07-06 19:24:06 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "amdlib.h" |
| 53 | #include "Gnb.h" |
| 54 | #include "GnbPcie.h" |
| 55 | #include GNB_MODULE_DEFINITIONS (GnbCommonLib) |
| 56 | #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) |
| 57 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 58 | #include "GnbRegistersON.h" |
| 59 | #include "Filecode.h" |
| 60 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * D E F I N I T I O N S A N D M A C R O S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | /*---------------------------------------------------------------------------------------- |
| 67 | * T Y P E D E F S A N D S T R U C T U R E S |
| 68 | *---------------------------------------------------------------------------------------- |
| 69 | */ |
| 70 | |
| 71 | |
| 72 | /*---------------------------------------------------------------------------------------- |
| 73 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 74 | *---------------------------------------------------------------------------------------- |
| 75 | */ |
| 76 | |
| 77 | |
| 78 | /*----------------------------------------------------------------------------------------*/ |
| 79 | /** |
| 80 | * Get Gen1 voltage Index |
| 81 | * |
| 82 | * |
| 83 | * |
| 84 | * |
| 85 | * @param[in] StdHeader Standard configuration header |
| 86 | */ |
| 87 | UINT8 |
| 88 | PcieSiliconGetGen1VoltageIndex ( |
| 89 | IN AMD_CONFIG_PARAMS *StdHeader |
| 90 | ) |
| 91 | { |
| 92 | UINT8 Index; |
| 93 | UINT8 Gen1VidIndex; |
| 94 | UINT8 SclkVidArray[4]; |
| 95 | GnbLibPciRead ( |
| 96 | MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), |
| 97 | AccessWidth32, |
| 98 | &SclkVidArray[0], |
| 99 | StdHeader |
| 100 | ); |
| 101 | Gen1VidIndex = 0; |
| 102 | for (Index = 0; Index < 4; Index++) { |
| 103 | if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) { |
| 104 | Gen1VidIndex = Index; |
| 105 | } |
| 106 | } |
| 107 | return Gen1VidIndex; |
| 108 | } |
| 109 | |
| 110 | /*----------------------------------------------------------------------------------------*/ |
| 111 | /** |
| 112 | * Request Pcie voltage change |
| 113 | * |
| 114 | * |
| 115 | * |
| 116 | * @param[in] VidIndex The request VID index |
| 117 | * @param[in] StdHeader Standard configuration header |
| 118 | */ |
| 119 | VOID |
| 120 | PcieSiliconRequestVoltage ( |
| 121 | IN UINT8 VidIndex, |
| 122 | IN AMD_CONFIG_PARAMS *StdHeader |
| 123 | ) |
| 124 | { |
| 125 | D0F0x64_x6A_STRUCT D0F0x64_x6A; |
| 126 | D0F0x64_x6B_STRUCT D0F0x64_x6B; |
| 127 | |
| 128 | //Enable voltage client |
| 129 | GnbLibPciIndirectRead ( |
| 130 | MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), |
| 131 | D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, |
| 132 | AccessS3SaveWidth32, |
| 133 | &D0F0x64_x6A.Value, |
| 134 | StdHeader |
| 135 | ); |
| 136 | |
| 137 | D0F0x64_x6A.Field.VoltageChangeEn = 0x1; |
| 138 | |
| 139 | GnbLibPciIndirectWrite ( |
| 140 | MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), |
| 141 | D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, |
| 142 | AccessS3SaveWidth32, |
| 143 | &D0F0x64_x6A.Value, |
| 144 | StdHeader |
| 145 | ); |
| 146 | |
| 147 | D0F0x64_x6A.Field.VoltageLevel = VidIndex; |
| 148 | D0F0x64_x6A.Field.VoltageChangeReq = !D0F0x64_x6A.Field.VoltageChangeReq; |
| 149 | |
| 150 | GnbLibPciIndirectWrite ( |
| 151 | MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), |
| 152 | D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, |
| 153 | AccessS3SaveWidth32, |
| 154 | &D0F0x64_x6A.Value, |
| 155 | StdHeader |
| 156 | ); |
| 157 | do { |
| 158 | GnbLibPciIndirectRead ( |
| 159 | MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), |
| 160 | D0F0x64_x6B_ADDRESS | IOC_WRITE_ENABLE, |
| 161 | AccessS3SaveWidth32, |
| 162 | &D0F0x64_x6B.Value, |
| 163 | StdHeader |
| 164 | ); |
| 165 | } while (D0F0x64_x6A.Field.VoltageChangeReq != D0F0x64_x6B.Field.VoltageChangeAck); |
| 166 | } |
| 167 | |
| 168 | /*----------------------------------------------------------------------------------------*/ |
| 169 | /** |
| 170 | * Unhide all ports |
| 171 | * |
| 172 | * |
| 173 | * |
| 174 | * @param[in] Silicon Pointer to silicon configuration descriptor |
| 175 | * @param[in] Pcie Pointer to global PCIe configuration |
| 176 | */ |
| 177 | |
| 178 | VOID |
| 179 | PcieSiliconUnHidePorts ( |
| 180 | IN PCIe_SILICON_CONFIG *Silicon, |
| 181 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 182 | ) |
| 183 | { |
| 184 | GnbLibPciIndirectRMW ( |
| 185 | Silicon->Address.AddressValue | D0F0x60_ADDRESS, |
| 186 | D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, |
| 187 | AccessS3SaveWidth32, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 188 | ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 189 | 0x0, |
| 190 | GnbLibGetHeader (Pcie) |
| 191 | ); |
| 192 | GnbLibPciIndirectRMW ( |
| 193 | Silicon->Address.AddressValue | D0F0x60_ADDRESS, |
| 194 | D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, |
| 195 | AccessS3SaveWidth32, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 196 | ~(UINT32)BIT6, |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 197 | BIT6, |
| 198 | GnbLibGetHeader (Pcie) |
| 199 | ); |
| 200 | } |
| 201 | |
| 202 | /*----------------------------------------------------------------------------------------*/ |
| 203 | /** |
| 204 | * Hide unused ports |
| 205 | * |
| 206 | * |
| 207 | * |
| 208 | * @param[in] Silicon Pointer to silicon configuration data area |
| 209 | * @param[in] Pcie Pointer to data area up to 256 byte |
| 210 | */ |
| 211 | |
| 212 | VOID |
| 213 | PcieSiliconHidePorts ( |
| 214 | IN PCIe_SILICON_CONFIG *Silicon, |
| 215 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 216 | ) |
| 217 | { |
| 218 | D0F0x64_x0C_STRUCT D0F0x64_x0C; |
| 219 | PCIe_WRAPPER_CONFIG *WrapperList; |
| 220 | D0F0x64_x0C.Value = 0; |
| 221 | WrapperList = PcieSiliconGetWrapperList (Silicon); |
| 222 | while (WrapperList != NULL) { |
| 223 | PCIe_ENGINE_CONFIG *EngineList; |
| 224 | EngineList = PcieWrapperGetEngineList (WrapperList); |
| 225 | while (EngineList != NULL) { |
| 226 | if (EngineList->EngineData.EngineType == PciePortEngine) { |
| 227 | if (!PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) && |
| 228 | ((EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) || (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard)) && |
| 229 | !EngineList->Type.Port.IsSB) { |
| 230 | D0F0x64_x0C.Value |= 1 << EngineList->Type.Port.NativeDevNumber; |
| 231 | } |
| 232 | } |
| 233 | EngineList = PcieLibGetNextDescriptor (EngineList); |
| 234 | } |
| 235 | WrapperList = PcieLibGetNextDescriptor (WrapperList); |
| 236 | } |
| 237 | |
| 238 | GnbLibPciIndirectRMW ( |
| 239 | Silicon->Address.AddressValue | D0F0x60_ADDRESS, |
| 240 | D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, |
| 241 | AccessS3SaveWidth32, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 242 | ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 243 | D0F0x64_x0C.Value, |
| 244 | GnbLibGetHeader (Pcie) |
| 245 | ); |
| 246 | GnbLibPciIndirectRMW ( |
| 247 | Silicon->Address.AddressValue | D0F0x60_ADDRESS, |
| 248 | D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, |
| 249 | AccessS3SaveWidth32, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 250 | ~(UINT32)BIT6, |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 251 | 0x0, |
| 252 | GnbLibGetHeader (Pcie) |
| 253 | ); |
| 254 | } |
| 255 | |